TW439268B - Dynamic random access memory structure having vertical transistor and its fabricating method - Google Patents

Dynamic random access memory structure having vertical transistor and its fabricating method Download PDF

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Publication number
TW439268B
TW439268B TW88121971A TW88121971A TW439268B TW 439268 B TW439268 B TW 439268B TW 88121971 A TW88121971 A TW 88121971A TW 88121971 A TW88121971 A TW 88121971A TW 439268 B TW439268 B TW 439268B
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TW
Taiwan
Prior art keywords
formed
substrate
trench
polysilicon layer
region
Prior art date
Application number
TW88121971A
Inventor
Jia-Shuen Shiau
Jr-Yu Li
Jau-Jiue Wu
Original Assignee
Promos Technologies Inc
Mosel Vitelic Inc
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Promos Technologies Inc, Mosel Vitelic Inc, Siemens Ag filed Critical Promos Technologies Inc
Priority to TW88121971A priority Critical patent/TW439268B/en
Application granted granted Critical
Publication of TW439268B publication Critical patent/TW439268B/en

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Abstract

This invention is about the fabricating method of dynamic random access memory having vertical transistor. At first, a trench is formed in substrate. After that, a deep enough trench capacitor, which includes a storage electrode, a capacitor dielectric layer and an upper electrode, is formed in the trench. Then, the first polysilicon layer is formed in the trench and is electrically connected with the upper electrode and the first doped region, in which the first doped region is formed in the substrate and is used as a source region. After that, the second polysilicon layer is formed in the trench, in which the second polysilicon layer is electrically insulated with the first polysilicon layer and is isolated from substrate by using a gate oxide layer so as to form a channel region in substrate adjacent to gate oxide layer. On the substrate surface for the upper edge of channel region, the second doped region is formed and is used as the common drain region. A word line is then formed on substrate, in which the word line is formed on the trench capacitor in the direction parallel with the common drain region and is electrically connected with the second polysilicon layer through the use of a gate contact window. A bit line is formed on substrate, in which the bit line is formed on the trench capacitor in the direction perpendicular to the word line and is electrically connected with the common drain region through the use of a bit line contact window.
TW88121971A 1999-12-15 1999-12-15 Dynamic random access memory structure having vertical transistor and its fabricating method TW439268B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW88121971A TW439268B (en) 1999-12-15 1999-12-15 Dynamic random access memory structure having vertical transistor and its fabricating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW88121971A TW439268B (en) 1999-12-15 1999-12-15 Dynamic random access memory structure having vertical transistor and its fabricating method

Publications (1)

Publication Number Publication Date
TW439268B true TW439268B (en) 2001-06-07

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TW88121971A TW439268B (en) 1999-12-15 1999-12-15 Dynamic random access memory structure having vertical transistor and its fabricating method

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TW (1) TW439268B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7074700B2 (en) 2003-09-18 2006-07-11 Nanya Technology Corporation Method for isolation layer for a vertical DRAM
TWI406408B (en) * 2009-05-22 2013-08-21 Macronix Int Co Ltd Memory device and manufacturing method thereof
US9543404B2 (en) 2012-12-21 2017-01-10 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical BJT for high density memory

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7074700B2 (en) 2003-09-18 2006-07-11 Nanya Technology Corporation Method for isolation layer for a vertical DRAM
TWI406408B (en) * 2009-05-22 2013-08-21 Macronix Int Co Ltd Memory device and manufacturing method thereof
US9543404B2 (en) 2012-12-21 2017-01-10 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical BJT for high density memory
US9991368B2 (en) 2012-12-21 2018-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical BJT for high density memory

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