經濟部中央標準局員工消費合作社印策 321787 A7 _____B7 __ 五、發明説明（） 發明領域： 本發明與一種半導體製程之動態随機存取記億胞 (DRAM cell)有關，特别是一種高密度動態随機存取記憶 胞之製作方法。 發明背景：321787 A7 _____B7 __ Employee's Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy _____B7 __ 5. Description of the invention () Field of the invention: The present invention relates to a dynamic random access memory cell (DRAM cell) of a semiconductor process, especially a high-density dynamic Random access memory cell manufacturing method. Background of the invention:
高密度之動態随機存取記憶體（DRAM)在積體電路 技術上己有重大之進展，記憶胞通常由電容器與電晶體所 構成，電容之没極或源核與電容之一端連接，電容之另— 端則與參考電位連接’因此製造dram記憶胞包含了電 晶體與電容之製程，藉由電容器與源極區之電性接觸，數 位資訊儲存在電容器並藉金氧半場效電晶體、位元線（bit line)、字語線（word line)陣列來取得電容器之數位資科。 傳统中最常使用的電容型態爲平板形電容，主要是其較容 易製造，但是在元件缩小下以提高積禁度而使電容之表面 猜減少，因此平板形電容則不適合應用於高密度之DRAM 製造，爲使電容性能不會降低之電容製程方法與結構是電 容製程努力之方向。 爲了符合高密度之積想電路設計趨勢，動態隨機存取 記憶體製程之尺寸必須降至次微米，因爲元件之繪小化而 DRAM中之電容也相對的減小，故其儲存栽子之性能亦相 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -------------裝------訂------^ f請先閲讀背面之注意事項再填寫本頁} 321787 A7 B7 五、發明説明（） 對的降低，因此容器在讀取資料時受雜質之影響如Ot粒子 所產生之軟記錯（soft errors)將大大提高，並且"重新 (refresh)"之類率增加。 爲了解決上述之問題，電容朝向增加電容表面積之方 向發展，因此發展了溝渠式電容（如 U.S. Patent No· 5,374,580)與堆疊式電容，溝渠式電容有時會有漏電流 之現象，其次降低電容介電層之厚度也可以增加電容儲存 能力，但是基於良率及穩定性之考量此方法也有其限制。 一種具有半球形晶粒之複晶矽之COB電容（a capacitor-over-bit-line [COB] cell with a hemispherical-grain (HSG〉polysilicon storage node)也已發表在文獻中，如"A Capacitor-Over-Bit-Line Cell With Hemispherical-Grain Storge Node For 64Mb Drams", M. Sakao etc. microelectr research laboratories, NEC Corporation.該半球形晶粒之複晶石夕是以 化學氣相沈積法於非晶形轉變至晶形之相變溫度下沈 積。另外一種爲具有半球形晶粒複晶矽之中空圓柱形電容（a cylindrical capacitor using Hemispherical-Grained Si)參閱"A New Cylindrical Capacitor Using Hemispherical Grained Si For 256 Mb Drams^, H. Watanabe et al., Tech Dig,Dec. 1992, pp.259-262。 I----„--------裝------訂------線- (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作社印聚 本紙張尺度適用中國國家楳準（CNS ) A4規格（2丨〇X297公羞） 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（） 癸明目的及概述： 本發明之目的爲一種動態随機存取記憶體（DRAM) 之形成方法。 本發明之另一目的爲提供_種利用具有水平指狀物_ 柱狀體之皇冠形（crown-fin-piUar)電容以增加電容表面 積以提昇動態隨機存取記憶胞性能之方珐。 本發明所要揭示的爲利用增加表面積方式以提异動 態随機存取記憶體性能之方法，另外本發明利用硼磷矽玻 璃（BPSG)對CVD-氡化物之高選擇性飪刻形成具有水平 指狀物-柱狀之皇冠形（crown-fin-pillar)電容结構以大 量增加電容表面積，此高選擇性蝕刻之蝕刻比大約爲 2000 : 1，本發明之方法將於下述之。 場氧化區域形成於半導體基板之上，接著一厚度約爲 100埃之二氧化矽層形成於基板之上做爲閘極氧化層，此 二氧化梦層一般爲利用熱氧化法形成，第一複晶發層沈積 於·一氧化發廣、％氧化層以及基板之上、’一做爲絶緣廣之 介電層形成於上述之閘極結構、場氧化層、以及基板之 上’以較佳實施例而言該介電層爲利用TEOS形成之二氣 化矽。第_導電層隨後形成於介電層之上，—组成爲确辑 矽玻璃（BPSG)與二氧化矽之複合層交替重複沈積於第 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 裝 訂 旅 (請先閲讀背面之注意事項再填寫本頁) 321787 A7 B7 五、發明説明（） 一導電層之上，一光阻圖案形成於上述之複合層之上，以 蝕刻技術蝕刻複合層至第一導電層表面，接著施以高選擇 性之蝕刻，在此步驟中蝴磷矽玻璃（BPSG)之蝕刻速率遠 大於二氧化矽，以最佳實施例而言，此高選擇性蝕刻之姓 刻劑爲使用低壓HF蒸氣。 一光阻形成於複合層之上用以定義接觸洞之區域，接 著施以蝕刻技術複合層、第_導電層以及介電層至基板表 面。第二導電層接著沈積於第一導電層、硼磷矽玻璃（bpsg) 以及二氧化矽層之上，随後將第二導電層施以非等向性乾 蝕刻，在此步驟之後第二導電層隨即形成附著於複合層側 壁上之側壁間隙。下一步驟爲利用BOE溶液將複合層之 二氧化矽以及硼磷矽玻璃（BPSG)完全去除形成具有水平 指狀物（horizontal fins)與垂直柱狀體（vertical pillar) 之皇冠形結構（crown shape structure)。廷著皇冠形複晶 矽結構之表面沈積一介電薄膜做爲電容之介電層，第三導 電層以LPCVD方式沈積於上述之電容介電薄膜之上用以 做爲電容之頂部電極。 ----„--------1------,訂------Μ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作杜印裝 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公董） A7 B7 五、發明説明（） 垦式簡箪説明： 第一圈爲本發明之形成閘極結構之截面圈； 第二圈爲本發明之形成第一介電層與第一導電層之截面 阐； 第三圖爲本發明之形成碉磷矽玻璃（BPSG)與CVD氧化物 之複合層於第一導電層之上之截面圖； 第四圖爲本發明之高選擇性蝕刻複合層中之硼磷矽玻璃 (BPSG)之截面圏； 第五圖爲本發明之形成接觸洞於複合層、第一介電層與第 —導電層之中之截面圏； 第六圈爲本發明之蝕刻第二介電層形成柱狀介電層之截 面圈； 第七圖爲本發明之形成第二導電層之截面圈； 第八圖爲本發明之去除硼磷矽玻璃（BPSG). CVD氧化物 複合層之截面圖；及 第九圏爲本發明之形成電容介電層與第三導電層之截面 圖、。 裝------訂-------旅 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消費合作社印装 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 B7 五、發明説明（） 發明詳細説明： 經濟部中央標準局員工消費合作社印裝 本發明所要揭示的爲利用增加表面積方式以提昇動 態隨機存取記憶體性能之方法，另外本發明利用硼磷矽玻 璃（BPSG)對CVD-氧化物之高選擇性蝕刻形成具有水平 指狀物-柱狀之皇冠形（croWn_fin_piUar)電容結構以大 量增加電容表面積，此高選擇性蝕刻之蝕刻比大约爲 2000 : 1，本發明之方法將於了述之。 參閲第一圏’一晶向爲< 10〇>之單晶矽做爲基板 2，一場氧化區域4形成於半導體基板2之上，場氧化區 域4可以使用LOCOS或是其他相關之場氧化絶緣區域技 術形成於該基板2之上做爲元件間之絶緣作用，一般而 言’可以藉由微影與蝕刻技術蝕刻氮化矽及氧化矽複合層 後再以氧化製程形成場氧化層4於基板2之上，完成之後 以熱碑酸去除上述之氮化矽層，以氫氟酸去除氡化矽層， 場氧化區域4之厚度约爲3000-8000埃之間。 接著’一厚度約爲1〇〇埃之二氧化矽層6形成於基板 2之上做爲閘極氧化層，此二氧化矽層一般爲利用熱氧化 法形成’製程溫度约爲800至1100 1〇之間形成厚度約30 至300埃，當然一般之技術如化學氣相沈積法以te〇s爲 反應物’製程溫度約600至800 °C，壓力约1至1〇托耳也 可以形成二氧化矽層6。 本紙張尺度適用中國围家標準（CNS ) A4规格（21〇χ297公釐） (請先閲讀背面之注意事項再填寫本頁} -裝. 訂 -線 經濟部中央標準局員工消費合作社印装 五、發明説明（ 仍請參閲第一圉，第一複晶矽層8沈積於二氧化矽層 6、場氧化層4以及基板2之上，以一實施例而言此第一 複晶矽層8利用化學氣相沈積法（CVD)形成，厚度約爲5〇〇 至3000埃之間，接著以習知技術形成字語線、位元線 12、具有保護層14之閘極結構以及側壁間隙’然後以離 子植入方式形成摻雜區，上述製程非本發明之重點囡此在 此不加以詳述。 如第二圖所示，—做爲絶緣層之介電層18形成於上 述之閘極結構、場氧化層4、以及基板2之上，以較佳實 施例而言該介電層18爲利用TEOS形成之二氧化矽。接 著厚度约爲300至3000埃之第一導電層20形成於介電層 18之上，以最佳實施例而言本發明之第一導電層2〇爲以 化學氣相沈積形成之複晶矽，此第一導電層20可以爲摻 雜之複晶矽（doped polysilicon)或是同步摻雜之複晶矽 (in-situ doped poly silicon)，金屬如銘、銅、鶏、白金 或鈦亦可以做爲此第一導電層2·0。 參閲第三圖，一組成爲硼磷矽玻璃（BPSG) 22與二氧 化矽之複合層交替重複沈積於第一導電層20之上，此複 合層爲奇數層與偶數層所組成，奇數層爲二氧化矽，偶數 層爲硼磷矽玻璃（BPSG)，或著相反，偶數層爲二氧化矽， 本紙張尺度適用中國國家標準（CNS ) Α4規格（21〇X297公釐） (請先閲请背面之注意事項再填寫本頁) 裝· 訂 經濟部中央標準局員工消費合作社印製 A7 B7__五、發明説明（） 奇數層爲碉磷矽玻璃（BPSG)。碉磷矽玻璃（BPSG)可以使 用低壓化學氣相沈積法以TEOS爲反應物在形成碉磷矽 玻璃製程中摻雜碉與磷，硼磷矽玻璃（BPSG)厚度約爲200 至2000埃之間。二氧化矽層利用任何適合之方式形成如 化學氣相沈積法以TEOS爲反應物，製程溫度约600至800 eC，壓力约1至托耳形成二氧化矽層，厚度約爲200 至2000埃之間。 如第四圖所示，一光阻圖案形成於上述之複合層之 上，以蝕刻技術蝕刻複合層至第一導電層20表面，接著 施以高選擇性之蝕刻，在此步驟中硼磷矽玻璃（BPSG) 22 之蝕刻速率遠大於二氧化矽24，其次碉磷矽玻璃（BPSG) 22之蝕刻速率也遠大於BSG，因此可以使用BSG用來取 代二氧化矽24，以最佳實施例而言，此高選擇性蝕刻之 蝕刻劑爲使用低壓HF蒸氣，堋磷矽玻璃（BPSG) 22對二 氧化矽24之蝕刻比大約爲2000 : 1 。（參閲"A New Cylindrical Capacitor Using Hemispherical Grained Si For 256 Mb Drams", H. Watanabe et al·, 1992, IEEE)。因此确嶙石夕玻璃 (BPSG) 22明顯地比二氧化矽24蝕刻得多。 參閱第五圖，一光阻形成於複合層之上用以定義接觸 洞之區域，接著施以蝕刻技術複合層、第一導電層20以 及介電層18至基板2表面。此步驟所使用蝕刻複晶矽之 蝕刻劑爲 SiCl4 /Cl2、 BC13 /Cl2、 HBr/Cl2 /02、 ^ i 訂 據 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 五、發明説明（）HBr/02、 Br2/SF6 !SF6。用來去除二氧化矽之蝕刻 劑爲 CC12F2、 CHF3/CF4 > chf3/ 02 ' CH3CHF2 ' cf4/o2’氮化發則藉由 CF4/H2、 CHF3 或 ch3chf2 去除。控制不同之蝕刻劑可以將複合層、第一導電層2〇 以及介電層18分别蝕刻形成接觸洞2〇。完成接觸洞2〇 之蝕刻後則將光阻去除。 參閲第六圖’第二導電層28接著沈積於第—導電層 20、研鱗石夕玻璃（BPSG) 22以及二氧化石夕層24之上，當 然，第二導電層28亦形成於發玻璃（bpsg) 22與二氧 化矽層24之間，以較佳實施例而言，第二導電層28爲掺 雜之複晶矽（doped polysilicon)或是利用同步掺雜製程 沈積之複晶矽（in-situ doped polysilicon)，另外，鋁' 銅、僞或鈦亦可以做爲此第二導電層28。第二導電層28 之厚度约爲500至5000埃。 如第七圖所示，随後將第二導電層28施以非等向性 乾蝕刻，在此步驟之後第二導電層28隨即形成附著於複 合層側壁上之側壁間隙（spacers)28a » 參閲第八圏，下一步驟爲利用BOE (buffer oxide etching)溶液將複合層之二氧化矽24以及碉磷矽玻璃 (BPSG) 22完全去除形成具有水平指狀物（horizontal fins)28b與垂直柱狀趙（vertical pillar)28c之皇冠形結構 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） (锖先閲讀背面之注意事項再填寫本頁) *澤· b Γ 經濟部中央標準局員工消費合作社印裝 A7 ___________ B7_ 五、發明説明（） (crown shape structure)28a，利用此結構做爲電容之底 部電極將大幅提昇電容之表面積。 參閱第九圏，下一步驟爲沿著皇冠形複晶矽結構 28a、28b、28c之表面沈積一介電薄膜30做爲電容之介 電層，一般此介電層30可以利用N/O、O/N/O之複合 薄膜或是利用高介電之薄膜如Ta 20 5、 BST 、 PZT 、 PLZT ° 參閲第九圈，第三導電層32以LPCVD方式沈積於上 述之電容介電薄膜30之上用以做爲電容之頂部電極，第 二導電廣32可以利用捧雜複晶石夕（doped polysilicon)、 同步捧雜複晶石夕（in-situ doped polysilicon)、銅、銘、 鈦、鎢或白金等。 本發明之電容將大量增加電容之表面積，其次本發明 利用介於硼磷矽玻璃（BPSG)與二氧化矽間之高選擇性蝕 刻形成具有水平指狀物28b與垂直柱狀體28c之皇冠形結 構28a’因此本發明將提昇電容之儲存能力。 本發明以較佳實施例説明如上，而熟悉此領域技藝 者’在不脱離本發明之精神範園内，當可作些許更動潤 飾’例如高選擇性之蝕刻以形成皇冠形結構並不局限於本 發明實施例之介電質材質爲碉磷矽玻璃（BPSG)與二氧化 -----Γ------^------1T------终 (請先閲讀背面之注意事項再填寫本頁) 11High-density dynamic random access memory (DRAM) has made significant progress in integrated circuit technology. The memory cell is usually composed of a capacitor and a transistor. The step of the capacitor or the source core is connected to one end of the capacitor. The other end is connected to the reference potential. Therefore, the manufacturing of the dram memory cell includes the process of the transistor and the capacitor. Through the electrical contact between the capacitor and the source region, the digital information is stored in the capacitor and borrowed from the metal oxide half field effect transistor, Arrays of bit lines and word lines are used to obtain the digital information of capacitors. The most commonly used capacitor type in the tradition is the plate-shaped capacitor, mainly because it is easier to manufacture, but under the reduction of components to increase the forbidden degree and reduce the surface of the capacitor, the plate-shaped capacitor is not suitable for high-density capacitors. In the manufacture of DRAM, the method and structure of the capacitor manufacturing process so as not to reduce the performance of the capacitor are the direction of the efforts of the capacitor manufacturing process. In order to meet the trend of high-density product circuit design, the size of the dynamic random access memory system process must be reduced to sub-micron, because the size of the device is reduced and the capacitance in the DRAM is relatively reduced, so its storage performance The paper size is also applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) ------------- installed ------ ordered ------ ^ fPlease read first Note on the back and fill in this page} 321787 A7 B7 V. Description of invention () Right, so the container is affected by impurities when reading data, such as soft errors generated by Ot particles will be greatly improved, And the rate of "refresh" increases. In order to solve the above problems, capacitors have been developed in the direction of increasing the surface area of capacitors. Therefore, trench capacitors (such as US Patent No. 5,374,580) and stacked capacitors have been developed. Ditch capacitors sometimes have a phenomenon of leakage current, and secondly reduce the capacitance. The thickness of the electrical layer can also increase the storage capacity of the capacitor, but this method has its limitations based on yield and stability. A capacitor-over-bit-line [COB] cell with a hemispherical-grain (HSG> polysilicon storage node) has also been published in the literature, such as " A Capacitor -Over-Bit-Line Cell With Hemispherical-Grain Storge Node For 64Mb Drams ", M. Sakao etc. microelectr research laboratories, NEC Corporation. The hemispherical grains of polycrystals are amorphous by chemical vapor deposition It is deposited at the phase transition temperature of the crystalline form. The other is a cylindrical capacitor using Hemispherical-Grained Si with hemispherical grains. See " A New Cylindrical Capacitor Using Hemispherical Grained Si For 256 Mb Drams ^, H. Watanabe et al., Tech Dig, Dec. 1992, pp. 259-262. I ---- „-------- installed ------ order ----- -Line- (Please read the precautions on the back before filling in this page) The paper standard of the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs is applicable to the China National Standard (CNS) A4 specification (2 丨 〇297) Printed by the Bureau of Standards and Staff Consumer Cooperative A7 B7 Fifth, the description of the invention () Gui Ming purpose and summary: The purpose of the present invention is a dynamic random access memory (DRAM) formation method. Another object of the present invention is to provide a variety of use with horizontal fingers _ A column-shaped crown-fin-piUar capacitor to increase the surface area of the capacitor to improve the performance of the dynamic random access memory cell. What the present invention discloses is to use the increased surface area to enhance the dynamic random access The method of memory performance, in addition, the present invention utilizes the high selectivity of borophosphosilicate glass (BPSG) to CVD-radon compound to form a crown-fin-pillar capacitor structure with horizontal fingers-columns. The surface area of the capacitor is greatly increased. The etching ratio of this highly selective etching is about 2000: 1. The method of the present invention will be described below. The field oxidation region is formed on the semiconductor substrate, followed by a silicon dioxide with a thickness of about 100 angstroms. A layer is formed on the substrate as a gate oxide layer. The dream oxide layer is generally formed by thermal oxidation, and the first polycrystalline hair layer is deposited on the oxidized and oxidized layer, the% oxide layer and the substrate 'As an extension dielectric insulating layer is formed, and an upper substrate of the above gate structure, a field oxide layer' in terms of the preferred embodiment of the dielectric layer of silicon is formed by using two gas of TEOS. The _ conductive layer is then formed on the dielectric layer, which is composed of a composite layer consisting of silicate glass (BPSG) and silicon dioxide, which are alternately and repeatedly deposited on the first paper scale. The Chinese national standard (CNS) A4 specification (210X297 )) Binding Brigade (please read the precautions on the back before filling in this page) 321787 A7 B7 5. Description of the invention () A conductive layer and a photoresist pattern are formed on the above composite layer, which is etched by etching Layer to the surface of the first conductive layer, followed by high-selectivity etching. In this step, the etching rate of Phosphosilicate Glass (BPSG) is much greater than that of silicon dioxide. In the preferred embodiment, this high-selectivity etching The lasting agent is the use of low-pressure HF vapor. A photoresist is formed on the composite layer to define the area of the contact hole, and then the composite layer, the first conductive layer and the dielectric layer are etched to the surface of the substrate. The second conductive layer is then deposited on the first conductive layer, borophosphosilicate glass (bpsg) and silicon dioxide layer, and then the second conductive layer is subjected to anisotropic dry etching, after this step the second conductive The layer then forms a side wall gap attached to the side wall of the composite layer. The next step is to use BOE solution to completely remove the silicon dioxide and borophosphosilicate glass (BPSG) of the composite layer to form a crown shape with horizontal fins and vertical pillars. structure). On the surface of the crown-shaped polycrystalline silicon structure, a dielectric film is deposited as the dielectric layer of the capacitor, and the third conductive layer is deposited on the above-mentioned capacitor dielectric film by LPCVD to serve as the top electrode of the capacitor. ---- „-------- 1 ------, subscribe ------ Μ (Please read the precautions on the back before filling this page) Employee consumption of the Central Standard Falcon Bureau of the Ministry of Economic Affairs The size of the paper for the cooperative printing is applicable to the Chinese National Standard (CNS) Α4 specification (210X297 company director) A7 B7 5. Description of the invention () Reclamation description: The first circle is the cross-section circle forming the gate structure of the invention; The second circle is the cross-sectional view of the first dielectric layer and the first conductive layer of the present invention; the third figure is the composite layer of the BPSG and CVD oxide formed on the first conductive layer of the present invention The fourth cross-sectional view of the borophosphosilicate glass (BPSG) in the highly selective etched composite layer of the present invention; the fifth cross-sectional view of the contact hole formed in the composite layer and the first dielectric layer of the present invention; The cross-sectional ring in the first conductive layer; the sixth circle is the cross-sectional circle of the second dielectric layer formed by etching the second dielectric layer of the present invention; the seventh figure is the cross-sectional circle of the present invention forming the second conductive layer; The eighth figure is the cross-sectional view of the borophosphosilicate glass (BPSG) of the present invention. The CVD oxide composite layer; and the ninth ring is the shape of the present invention The cross-sectional view of the capacitor dielectric layer and the third conductive layer. Installation ------ order ------- Travel (please read the precautions on the back before filling out this page) The paper size of the printed version of the consumer cooperative is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) A7 B7 5. Description of the invention () Detailed description of the invention: Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. The method of increasing the surface area to improve the performance of the dynamic random access memory. In addition, the present invention uses borophosphosilicate glass (BPSG) to etch the CVD-oxide with high selectivity to form a crown shape with horizontal fingers and columns (croWn_fin_piUar ) The capacitor structure increases the surface area of the capacitor by a large amount. The etching ratio of this highly selective etching is about 2000: 1, and the method of the present invention will be described. Refer to the first coil for a crystal orientation of < 10〇 > Single-crystal silicon is used as the substrate 2 and a field oxide region 4 is formed on the semiconductor substrate 2. The field oxide region 4 can be formed on the substrate 2 using LOCOS or other related field oxide insulating region technology as elements In general, the insulating function can be etched by photolithography and etching technology to form a silicon oxide and silicon oxide composite layer, and then an oxide process is used to form a field oxide layer 4 on the substrate 2, and the above is removed by thermal steatoic acid after completion The silicon nitride layer is hydrofluoric acid to remove the radon silicon layer. The thickness of the field oxidation region 4 is between 3000-8000 angstroms. Then, a silicon dioxide layer 6 with a thickness of about 100 angstroms is formed on the substrate 2 is used as the gate oxide layer. The silicon dioxide layer is generally formed by thermal oxidation. The process temperature is about 800 to 1100 and the thickness is about 30 to 300 Angstroms. Of course, the general technology is chemical vapor. The deposition method uses te〇s as the reactant 'process temperature is about 600 to 800 ° C, and the pressure is about 1 to 10 Torr can also form the silicon dioxide layer 6. The size of this paper is applicable to the Chinese Weijia Standard (CNS) A4 specification (21〇297 mm) (please read the precautions on the back and then fill in this page) 2. Description of the invention (Please still refer to the first sect. The first polycrystalline silicon layer 8 is deposited on the silicon dioxide layer 6, the field oxide layer 4 and the substrate 2. According to an embodiment, the first polycrystalline silicon layer 8. It is formed by chemical vapor deposition (CVD) with a thickness of about 500 to 3000 angstroms, and then the word line, bit line 12, gate structure with protective layer 14 and sidewall gap are formed by conventional techniques 'Then doped regions are formed by ion implantation, the above process is not the focus of the present invention and will not be detailed here. As shown in the second figure, a dielectric layer 18 as an insulating layer is formed on the gate On the electrode structure, the field oxide layer 4, and the substrate 2, in a preferred embodiment, the dielectric layer 18 is silicon dioxide formed by TEOS. Then, a first conductive layer 20 with a thickness of about 300 to 3000 angstroms is formed On the dielectric layer 18, the first guide of the invention The layer 20 is polycrystalline silicon formed by chemical vapor deposition. The first conductive layer 20 may be doped polysilicon or in-situ doped poly silicon , Metals such as Ming, Copper, Zinc, Platinum or Titanium can also be used as the first conductive layer 2 · 0. Referring to the third figure, a group of borophosphosilicate glass (BPSG) 22 and silicon dioxide composite layers alternate Repeatedly deposited on the first conductive layer 20, the composite layer is composed of an odd layer and an even layer, the odd layer is silicon dioxide, the even layer is borophosphosilicate glass (BPSG), or vice versa, the even layer is dioxide Silicone, the standard of this paper is in accordance with Chinese National Standard (CNS) Α4 specification (21〇X297mm) (please read the precautions on the back first and then fill out this page). Packed and ordered A7 B7_ _5. Description of the invention () The odd-numbered layer is BPSG (BPSG). BPSG can use low-pressure chemical vapor deposition method with TEOS as a reactant in the process of forming PBSG to form PBSG. Phosphorus, borophosphosilicate glass (BPSG) thickness is about 200 to 2000 Angstroms The silicon dioxide layer is formed by any suitable method such as chemical vapor deposition using TEOS as the reactant, the process temperature is about 600 to 800 eC, and the pressure is about 1 to Torr to form the silicon dioxide layer, and the thickness is about 200 to Between 2000 Angstroms. As shown in the fourth figure, a photoresist pattern is formed on the above-mentioned composite layer, and the composite layer is etched to the surface of the first conductive layer 20 by an etching technique, followed by high-selectivity etching. In this step, the etching rate of borophosphosilicate glass (BPSG) 22 is much higher than that of silicon dioxide 24. Secondly, the etching rate of BPSG 22 (BPSG) 22 is also much higher than that of BSG. Therefore, BSG can be used to replace silicon dioxide 24 to In the preferred embodiment, the etchant for the highly selective etching is the use of low-pressure HF vapor, and the etching ratio of phosphorosilicate glass (BPSG) 22 to silicon dioxide 24 is about 2000: 1. (See " A New Cylindrical Capacitor Using Hemispherical Grained Si For 256 Mb Drams ", H. Watanabe et al ·, 1992, IEEE). Therefore, it is true that BPSG 22 is significantly etched much more than silicon dioxide 24. Referring to the fifth figure, a photoresist is formed on the composite layer to define the area of the contact hole, and then an etching technique is applied to the composite layer, the first conductive layer 20 and the dielectric layer 18 to the surface of the substrate 2. The etchant used to etch polycrystalline silicon in this step is SiCl4 / Cl2, BC13 / Cl2, HBr / Cl2 / 02, ^ i Order (please read the precautions on the back before filling in this page) This paper size is applicable to Chinese national standards (CNS) A4 specification (210X297mm) Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Invention Instructions () HBr / 02, Br2 / SF6! SF6. The etchant used to remove silicon dioxide is CC12F2, CHF3 / CF4 > chf3 / 02 'CH3CHF2' cf4 / o2 'nitride hair is removed by CF4 / H2, CHF3 or ch3chf2. Controlling different etching agents can etch the composite layer, the first conductive layer 20 and the dielectric layer 18 to form contact holes 20 respectively. After the etching of the contact hole 20 is completed, the photoresist is removed. Referring to the sixth figure, the second conductive layer 28 is then deposited on the first conductive layer 20, BPSG glass 22 (BPSG) 22 and the silica layer 24. Of course, the second conductive layer 28 is also formed on the Between the glass (bpsg) 22 and the silicon dioxide layer 24, in a preferred embodiment, the second conductive layer 28 is doped polysilicon (doped polysilicon) or polysilicon deposited using a synchronous doping process (In-situ doped polysilicon), in addition, aluminum 'copper, pseudo or titanium can also be used as the second conductive layer 28. The thickness of the second conductive layer 28 is about 500 to 5000 angstroms. As shown in the seventh figure, the second conductive layer 28 is then subjected to anisotropic dry etching. After this step, the second conductive layer 28 then forms sidewall spacers 28a attached to the sidewalls of the composite layer »see Reading the eighth circle, the next step is to use BOE (buffer oxide etching) solution to completely remove the silicon dioxide 24 and BPSG 22 of the composite layer to form horizontal fins 28b and vertical columns The crown-shaped structure of the vertical pillar 28c. The paper size is in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm) (Read the precautions on the back before filling this page) * Ze · b Γ Ministry of Economic Affairs A7 ___________ B7_ printed by the Central Standards Bureau employee consumer cooperative. V. Invention description () (crown shape structure) 28a. Using this structure as the bottom electrode of the capacitor will greatly increase the surface area of the capacitor. Referring to the ninth ring, the next step is to deposit a dielectric film 30 as the capacitor dielectric layer along the surface of the crown-shaped polycrystalline silicon structure 28a, 28b, 28c. Generally, the dielectric layer 30 can utilize N / O, O / N / O composite film or high dielectric films such as Ta 20 5, BST, PZT, PLZT ° Refer to the ninth circle, the third conductive layer 32 is deposited on the above-mentioned capacitive dielectric film 30 by LPCVD The top electrode is used as the top electrode of the capacitor. The second conductive layer 32 can use doped polysilicon, in-situ doped polysilicon, copper, inscription, titanium, Tungsten or platinum, etc. The capacitor of the present invention will greatly increase the surface area of the capacitor. Secondly, the present invention utilizes highly selective etching between borophosphosilicate glass (BPSG) and silicon dioxide to form a crown shape with horizontal fingers 28b and vertical columns 28c The structure 28a 'therefore improves the storage capacity of the capacitor. The present invention has been described above with preferred embodiments, and those skilled in the art can do a little modification within the spirit of the present invention, such as highly selective etching to form a crown-shaped structure is not limited to The dielectric material of the embodiment of the present invention is BPSG (BPSG) and dioxide ----- Γ ------ ^ ------ 1T ------ End (please first Read the precautions on the back and fill out this page) 11
經濟部中央標準局員工消費合作社印製 A7 _B7_ 五、發明説明（） 矽，其專利保護範圍更當視後附之申請專利範圍及其等同 領域而定。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 裝 訂 線.. (請先閱讀背面之注意事項再填寫本頁)The A7 _B7_ printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Invention description () Silicon, the scope of patent protection depends more on the scope of the attached patent application and its equivalent areas. The paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) binding line. (Please read the notes on the back before filling this page)