^'对十少^^^只-1"介^ I 43268 3 3U2tw l'.dLic/006 A7 B7 五、發明説明（i ) 本發明是有關於一種動態隨機存取記憶體（DRAM)的 製造方法，且特別是有關於一種使用非晶矽和半球型矽晶 粒(HSG)多晶矽之堆疊電容器的製造方法。 現已有縮減記憶胞的尺寸以增加積集度就如同增加一 DRAM晶片的記憶容量的趨勢。當DRAM的尺寸減小，使 用在DRAM之電容器的容量也相對縮小。 DRAM的記憶胞一般包括儲存電容器和存取電晶體。 隨著大型積集度DRAM元件的出現，該元件的尺寸已愈來 愈小以致單一記憶胞的可用面積變的非常小。這使電容器 的面積減少，導致記憶胞的電容量減少。 一種增加電容量面積的方法，係在非晶矽上形成半球 型矽晶粒多晶矽且增加電容器高度。然而，增加電容器高 度迫使非晶矽層增加’其迫使非晶矽層的沉積時間增加。 沉積時間的增加，導致非晶矽結晶化。非晶矽層的結晶化 會抑制矽的遷移，導致在非晶矽上的半球型矽晶粒難以形 成。對於非晶矽沉積’大多使用矽甲烷(SlH4)爲反應氣體。 雖然使用砂乙烷（Si2H6)可減少沉積時間，但改變現行的設 備需求非常昂貴。 因此’需要一種能降低非晶矽結晶且使用現有的設備 來製造堆疊電容器的改進方法。 -種在基底上製造堆疊電容器之寧部儲存節點的方 法，包含下列步驟：U)在基底上形成一第一介電層；（2)在 弟一介電層上形成一氮化矽層；（3)微影及蝕刻第一介電層 和氮化矽層直到達基底，以形成一接觸窗口；在氮化 _______ 本纸张X度賴巾戰1諸彳（FnS ) Λ4規格（2iOX 297公楚.)' 〜------ (誚先閱讀背面之注意事項再填寫本頁) 裝- 腺 43268 3 3KK2t\vt*.d〇c/()06 A 7 B7 五、發明説明（：！） 矽層上，形成一第—導電層塡入前述接觸窗口；（5)移除一 部份在第一介電層上的第一導電層，藉以在接觸窗口形成 一插塞；（6)在氮化矽層和插塞之上形成一第二介電層；（7) 微影及蝕刻第二介電層，藉以在插塞上形成一溝渠；（8)在 第二介電層上’形成一非晶矽層塡入前述溝渠；移除一 部份在第二介電層上的非晶矽層；（1〇)移除第二介電層之 殘留部分；以及（11)在非晶矽層上形成一半球型矽晶粒多 晶砂層。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A-1C圖是一半導體基底的剖面圖，圖示使用習知 技術方法形成一堆疊儲存節點的步驟。 第2-7圖是一半導體基底的剖面圖，圖示本發明形成 一電容器的基底儲存節點。 圖式之標記說明： 102 :介電層 104 :接觸窗口 106 :非晶矽層 108 :光阻層 110 :半球型矽晶粒多晶矽124 112 :基底 114 :第一介電層 116 118 120 122 接觸窗口 多晶砂插塞 第二介電層 溝渠 光阻層 126 =非晶矽層 128 :半球型矽晶粒多晶矽 本紙張尺皮珀州屮國囚家行4* ( ΓΝ$ ) Λ4规格{ 210X 297公釐〉 - j (誚先閲讀背面之注意事項再填寫本頁) -6^ 'To ten less ^^^ only -1 " introduction ^ I 43268 3 3U2tw l'.dLic / 006 A7 B7 V. Description of the invention (i) The present invention relates to the manufacture of a dynamic random access memory (DRAM) Method, and in particular, relates to a method for manufacturing a stacked capacitor using amorphous silicon and hemispherical silicon grain (HSG) polycrystalline silicon. There has been a trend to reduce the size of the memory cells to increase the degree of accumulation as if to increase the memory capacity of a DRAM chip. When the size of the DRAM is reduced, the capacity of the capacitor used in the DRAM is also relatively reduced. DRAM memory cells generally include storage capacitors and access transistors. With the advent of large-scale DRAM devices, the size of the devices has become smaller and smaller, so that the usable area of a single memory cell has become very small. This reduces the area of the capacitor and reduces the capacitance of the memory cell. One method to increase the capacitance area is to form hemispherical silicon grain polycrystalline silicon on amorphous silicon and increase the height of the capacitor. However, increasing the capacitor height forces the amorphous silicon layer to increase 'which forces the deposition time of the amorphous silicon layer to increase. The increase in deposition time leads to crystallization of amorphous silicon. Crystallization of the amorphous silicon layer inhibits the migration of silicon, making it difficult to form hemispherical silicon grains on the amorphous silicon. For amorphous silicon deposition ', silicon methane (SlH4) is mostly used as a reactive gas. Although the use of sand ethane (Si2H6) can reduce deposition time, changing existing equipment requirements is very expensive. Therefore, there is a need for an improved method that can reduce the crystallization of amorphous silicon and use existing equipment to manufacture stacked capacitors. -A method for manufacturing a storage node of a stacked capacitor on a substrate, comprising the steps of: U) forming a first dielectric layer on the substrate; (2) forming a silicon nitride layer on the dielectric layer; (3) Lithography and etching the first dielectric layer and the silicon nitride layer until reaching the substrate to form a contact window; in the nitride _______ this paper X degree Lai Zhan war 1 Zhun (FnS) Λ4 specifications (2iOX 297 Gongchu.) '~~ ---- (诮 Read the precautions on the back before filling this page) Equipment-Gland 43268 3 3KK2t \ vt * .d〇c / () 06 A 7 B7 V. Description of the invention ( :!) On the silicon layer, a first-conductive layer is inserted into the aforementioned contact window; (5) a part of the first conductive layer on the first dielectric layer is removed to form a plug in the contact window; ( 6) forming a second dielectric layer on the silicon nitride layer and the plug; (7) lithography and etching the second dielectric layer to form a trench on the plug; (8) on the second dielectric Forming an amorphous silicon layer on the layer into the aforementioned trench; removing a portion of the amorphous silicon layer on the second dielectric layer; (10) removing the remaining portion of the second dielectric layer; and (11 In Africa Forming a hemispherical grain silicon polycrystalline silicon layer on the sand. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: Section 1A- Figure 1C is a cross-sectional view of a semiconductor substrate, illustrating the steps of forming a stacked storage node using conventional techniques. Figures 2-7 are cross-sectional views of a semiconductor substrate, illustrating a substrate storage node forming a capacitor according to the present invention. Explanation of the marks of the drawings: 102: dielectric layer 104: contact window 106: amorphous silicon layer 108: photoresist layer 110: hemispherical silicon grain polycrystalline silicon 124 112: substrate 114: first dielectric layer 116 118 120 122 contact Window polycrystalline sand plug second dielectric layer trench photoresist layer 126 = amorphous silicon layer 128: hemispherical silicon grain polycrystalline silicon paper ruler Pipper State Gao Guo prison house line 4 * (ΓΝ $) Λ4 specification {210X 297 mm>-j (诮 Please read the notes on the back before filling this page) -6
T 4 3268 3 j N K2t w l'.doc/ΟΟίι A7 _ ______B7 五、發明説明（彡） ^ 115 :氮化矽層 較佳竇施例 本發明將配合所附圖式，於下詳細敘述。本發明係 提出一種堆疊電容器的製造方法，此堆疊電容器具有更多 的記憶胞電容量與更高積集度。 習知做法請參考第1A-1C圖，首先請參考第ία圖， 在一基底100上形成〜介電層102。接著，形成—接觸窗 口 104。然後，在介電層1〇2上形成非晶矽層1〇6。之後， 使用一光阻層108當罩幕，蝕刻非晶矽層106。接著’去 除光阻層108，形成如第iB圖所示的結構。之後’在非晶 矽層106上形成半球型矽晶粒多晶矽11〇，完成如第1(：圖 所示的底部儲存節點。 在此習知技術中，係藉由增加非晶矽層丨〇6的厚度以 增加堆疊底部儲存節點的高度，而增加儲存電荷的面積。 然而’增加非晶矽層106的厚度需要較長的沉積時間。 較長的沉積時間會使非晶矽層106結晶化，而導致半 球型砂晶粒多晶矽110形成不良。 本·發明的描述從第2圖繪示的半導體基底112開始， 如熟習此藝者所知，基底可以包括一半導體晶片、在晶片 上的主動與被動元件、和在晶片表面形成的各層。名辭 ''基 底〃表示包括在一半導體晶片上的元件和覆蓋該晶片的各 層。 ' 在第2圖中，在基底112上形成一第一介電層U4 ^ 第一介電層Π4可由二氧化矽、硼磷矽玻璃（BPSG)、旋塗 --------------.——，1T------- (誚先閲讀背而之注意事項再填寫本頁) Α7 Β7 五、發明説明（爷） 式玻璃（SOG)、或任何相關組合所形成。第一介電層114 的厚度最好約]，〇〇〇到2,000埃。接箸1藉由使用傳統技 術在第一介電層114上形成一氮化矽層115。在此較佳實 施例中，氦化矽層〗15係由低壓化學氣相沉積法(LPCVD) 沉積，使用二氯甲烷當沉積源’在溫度約700到800°C之 間，在壓力約0.1到1 torr之間。氮化矽層115的厚度約50 到200埃之間。形成氮化矽層115用以當蝕刻終止層。 接著，一接觸窗口 116使用傳統微影和蝕刻技術製 成。蝕刻程度控制在到達基底112時終止。此外，接觸窗 口 116照例置於在DRAM記憶胞之存取電晶體的汲極上。 在第一介電層114上，一沉積且摻雜（in-situ doped)多 晶矽層沉積入該接觸窗口 116,且最好使用傳統化學氣相 沉積法（CVD)。接著蝕刻該多晶矽層，最好使用反應性離 子蝕刻法（RIE)或化學機械硏磨法（CMP)。飩刻在到達氮化 矽層U5時停止，留下一多晶矽插塞ns在接觸窗口 116 內。在氮化矽層115和多晶矽插塞118之上沉積一第二介 電層120。第二介電層丨20可由二氧化矽、BPSG、S0G、 或任何相關組合所形成。第二介電層120的厚度最好約 4,000 到 15,000 埃。 參考第3圖，一溝渠122使用傳統微影與蝕刻技術在 第二介電層120形成。例如，一光阻層124可沉積在第二 介電層120之上接著，光阻層丨24微影且顯影以顯露出 溝渠122。第二介電層120用氮化矽層115當蝕刻終止層 進行蝕刻，然後剝除光阻層124。 ----------^-----..--ΐτ------1 ^ (謫先閱讀背面之注項再填寫本頁} 本紙張尺度珀州中囡K家標今(rMS )八视格（210X297公# ) "" ' ™ ^"""" 匿43268 3 3SH2Uvr.tioc/006 A7 B7T 4 3268 3 j N K2t w l'.doc / ΟΟίι A7 _ ______B7 V. Description of the Invention (ii) ^ 115: Silicon nitride layer Preferred sinus embodiment The present invention will be described in detail below with the accompanying drawings. The invention proposes a method for manufacturing a stacked capacitor. The stacked capacitor has more memory cell capacitance and higher accumulation degree. For a conventional method, please refer to FIGS. 1A-1C. First, refer to FIG. 1a to form a dielectric layer 102 on a substrate 100. Next, a contact window 104 is formed. Then, an amorphous silicon layer 106 is formed on the dielectric layer 102. Then, a photoresist layer 108 is used as a mask, and the amorphous silicon layer 106 is etched. Next, the photoresist layer 108 is removed to form a structure as shown in FIG. IB. After that, a hemispherical silicon grain polycrystalline silicon 11 is formed on the amorphous silicon layer 106, and the bottom storage node shown in FIG. 1 is completed. In this conventional technique, an amorphous silicon layer is added. 6 to increase the height of the storage node at the bottom of the stack and increase the area of stored charge. However, 'increasing the thickness of the amorphous silicon layer 106 requires a longer deposition time. A longer deposition time causes the amorphous silicon layer 106 to crystallize , Resulting in poor formation of hemispherical sand grain polycrystalline silicon 110. The description of this invention begins with the semiconductor substrate 112 shown in Figure 2. As known to those skilled in the art, the substrate may include a semiconductor wafer, active and Passive components and layers formed on the surface of the wafer. The term "substrate" refers to the components included on a semiconductor wafer and the layers covering the wafer. 'In the second figure, a first dielectric is formed on the substrate 112. Layer U4 ^ The first dielectric layer Π4 may be made of silicon dioxide, borophosphosilicate glass (BPSG), spin coating --------------.----, 1T ------- (Please read the precautions before filling in this page) Α7 Β7 V. Invention (Grand) type glass (SOG), or any combination thereof. The thickness of the first dielectric layer 114 is preferably about 1000 to 2,000 angstroms. Then, by using conventional techniques, the first dielectric layer 114 A silicon nitride layer 115 is formed on 114. In this preferred embodiment, the silicon helium layer 15 is deposited by low pressure chemical vapor deposition (LPCVD) using methylene chloride as the deposition source at a temperature of about 700 to Between 800 ° C and a pressure of about 0.1 to 1 torr. The thickness of the silicon nitride layer 115 is about 50 to 200 angstroms. A silicon nitride layer 115 is formed to serve as an etching stopper. Next, a contact window 116 It is made using traditional lithography and etching techniques. The degree of etching control is terminated when it reaches the substrate 112. In addition, the contact window 116 is placed on the drain of the access transistor of the DRAM memory cell as usual. On the first dielectric layer 114, An in-situ doped polycrystalline silicon layer is deposited into the contact window 116, preferably using conventional chemical vapor deposition (CVD). The polycrystalline silicon layer is then etched, preferably using reactive ion etching (RIE) ) Or chemical mechanical honing method (CMP). U5 stops, leaving a polycrystalline silicon plug ns in the contact window 116. A second dielectric layer 120 is deposited on the silicon nitride layer 115 and the polycrystalline silicon plug 118. The second dielectric layer 20 may be made of silicon dioxide , BPSG, SOG, or any combination thereof. The thickness of the second dielectric layer 120 is preferably about 4,000 to 15,000 Angstroms. Referring to FIG. 3, a trench 122 uses traditional lithography and etching techniques on the second dielectric layer 120. For example, a photoresist layer 124 may be deposited on the second dielectric layer 120. Then, the photoresist layer 24 is lithographed and developed to expose the trench 122. The second dielectric layer 120 is etched using a silicon nitride layer 115 as an etch stop layer, and then the photoresist layer 124 is stripped. ---------- ^ -----..-- ΐτ ------ 1 ^ (谪 Please read the notes on the back before filling this page} This paper size Jia Biao Jin (rMS) Eight Views (210X297 公 #) " " '™ ^ " " " " 匿 43268 3 3SH2Uvr.tioc / 006 A7 B7
好# 部屮士«ii-AS-T消 frA«K7l印 V 五、發明説明（夕） I 參考第4圖，在第二介電層120之上’一非晶矽層126 使用任何已知傳統技術沉積入該溝渠，例如使用砂甲烷或 矽乙烷當該反應氣體。最好，在第二介電層丨20上之非晶 矽層126的厚度約3,000埃。非晶矽層126的沉積溫度最 好低於550X：。 參考第5圖，在第二介電層120上之部分非晶矽層126 使用傳統蝕刻技術或由化學機械硏磨法(CMP)移除。 參考第6圖，藉由任何傳統技術移除殘留的第二介電 層120。例如，第二介電層120可藉由傳統濕式氧化蝕刻 移除。蝕刻劑可使用稀釋氟化氫溶液。 參考第7圖，在非晶矽層126上形成半球型矽晶粒多 晶矽128。半球型矽晶粒多晶矽128藉由高溫真空回火形 成。高真空回火溫度最好在560和660°C之間。最好半球 型矽晶粒多晶矽128使用高真空晶種技術形成。簡單的說， 使用矽甲烷或矽乙烷於非晶矽126表面成晶。於是，底部 儲存節點形成。 最後，使用傳統沉積的介電層和頂部儲存節點完成 電容器。這些傳統”完成”步驟在該技術上已經知曉，在此 就不再多加討論。 本發明增加生產率並且降低或減少非晶矽126結晶化 以改進半球型矽晶粒多晶矽成長。這是藉由縮短非晶矽層 的沉積時間而達成。該非晶矽層沿著溝渠122壁上形成， 其意指沿第二介電層的側壁。因此，沉積時間是依據溝渠 12.2的寬度，甚於非晶矽層的高度（或厚度）。堆疊的寬度 ---1 (—---- - I-- 士 K ------ ----n 丁 __n J——ΛΚ1 0¾.-5 (誚先閱讀背而之注項再填寫本頁} 本紙认尺度鸿;丨]中囚S家標埤（（、NS )八4说格（210X297公犮） A7 B7 ^、發明説明（6 ) 短於堆疊的高度可得到更短的沉積時間。再者，有更進一 步降低堆疊的寬度和增加高度使該電容器的尺寸降低的趨 勢。因此，在本發明下之非晶矽層的沉積時間將更進一步 較習知技術方法的沉積時間縮短。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (硝先閱讀背而之注意事項再填寫本頁) ? 、ν3 4m 尺ϋ 则,ΚΙSM.讨{ rNS ) A4 規格 <210X297 公楚）好 # 部 屮 士 «ii-AS-T 消 frA« K7l 印 V 5. Description of the Invention (Even) I Refer to Figure 4, above the second dielectric layer 120 'an amorphous silicon layer 126 using any known Traditional techniques deposit into the trench, for example using sand methane or silicon as the reactive gas. Preferably, the thickness of the amorphous silicon layer 126 on the second dielectric layer 20 is about 3,000 angstroms. The deposition temperature of the amorphous silicon layer 126 is preferably lower than 550X :. Referring to FIG. 5, a portion of the amorphous silicon layer 126 on the second dielectric layer 120 is removed using a conventional etching technique or by a chemical mechanical honing method (CMP). Referring to FIG. 6, the remaining second dielectric layer 120 is removed by any conventional technique. For example, the second dielectric layer 120 may be removed by conventional wet oxidation etching. As the etchant, a diluted hydrogen fluoride solution can be used. Referring to FIG. 7, a hemispherical silicon grain polycrystalline silicon 128 is formed on the amorphous silicon layer 126. Hemispherical silicon grain polycrystalline silicon 128 is formed by high temperature vacuum tempering. The high vacuum tempering temperature is preferably between 560 and 660 ° C. It is preferred that hemispherical silicon grain polycrystalline silicon 128 be formed using high vacuum seeding technology. In short, the surface of the amorphous silicon 126 is crystallized using silicon methane or silicon. Thus, the bottom storage node is formed. Finally, the capacitor is completed using a conventionally deposited dielectric layer and a top storage node. These traditional "complete" steps are already known in the art and will not be discussed further here. The present invention increases productivity and reduces or reduces crystallization of amorphous silicon 126 to improve hemispherical silicon grain polycrystalline silicon growth. This is achieved by shortening the deposition time of the amorphous silicon layer. The amorphous silicon layer is formed along the wall of the trench 122, which means along the sidewall of the second dielectric layer. Therefore, the deposition time is based on the width of the trench 12.2, rather than the height (or thickness) of the amorphous silicon layer. Stacking width --- 1 (-------I-- 士 K ------ ---- n 丁 __n J——ΛΚ1 0¾.-5 (诮 read the note below first Fill out this page again} This paper recognizes the standard hong; 丨] The prisoner ’s family standard 埤 ((, NS) 44 grid (210X297) A, A7 B7 ^, invention description (6) shorter than the height of the stack can be shorter In addition, there is a tendency to further reduce the width of the stack and increase the height to reduce the size of the capacitor. Therefore, the deposition time of the amorphous silicon layer under the present invention will be further compared to that of conventional techniques The time is shortened. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the invention Therefore, the scope of protection of the present invention shall be subject to the definition of the scope of the attached patent application. (Please read the precautions before filling in this page)? Ν3 4m Ruler, KISM. Discuss {rNS) A4 Specifications < 210X297 Gongchu)