541667 A7 __ 五、發明説明（） 發明領诚： 本發明係有關於一種半導體元件之製作方法，特別 是一種形成動態隨機存取記憶體（DRAM)記憶胞•的方法， 而更加獨特地是本發明係有關於形成一 DRAM記憶胞電 容之方法。 發明脅景： 最近幾年半導體元件的發展為將許多的元件整合在 一晶片上’高密度記憶體記憶胞已被發展，特別是動態隨 機存取記憶體（DRAM)已朝向高密度封裝發展。DRAM被 廣泛地使用於電腦科技，且已利用高密度積體電路技術製 成，產業界已由16K位元容量DRAM發展至高於64M位 元容量DRAM。 傳統上DRAM記憶胞被應用於儲存電腦數據，這此 經濟部中央標率局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁 線！ 半導體記憶體元件有大的電容量來讀出及儲存訊息，因其 即使電源持續供應亦只能暫時保留訊息，故又文炎& 八石為動態隨 機存取記憶體（DRAM);因此記憶體必須每隔週期 β期即被讀 取及充電。一積體電路DRAM元件傳統上有許客々也 巧。卞夕圮憶胞， 實際上一個記憶胞提供一個位元儲存於dram - /φ — 1午’母 本紙張尺度適用中國國家標準（CNS ) Α4規格（21〇Χ2972^釐） 541667 A7 經濟部中央標準局員工消費合作社印掣 五、發明説明 個記憶胞傳統上包含一個儲存電容及一^ 個通路電晶體，通 路電晶體的源極或汲極其中之一接於常冤谷态一端，電晶體 通道的另-端及電晶體的問極連接於外接電路分別為位元線（bit line)及字元線（ word line)。雷六空 包谷另一端接一參考電 壓’ DRAM記憶胞的形成包含電晶體、電容器及外接電路的製作。 為了得到高密度dram元件’記憶胞尺寸必須縮小 至次微米範圍，如此因電容面積減少而造成記憶胞容量減 小’先前的技術已發展出堆i.式電容幾乎克服這些問題， Tuan已申請一有崎嶇不平表面的電容以增加電容面積（美 國專利第5,266’14號）。非晶碎在約攝氏875度下回火 以將其表面粗糙化。另一型電容又稱為溝渠式電容，先前 技術之一有關逢ϋΐ：容可見美國專利第5·374,580號。 此外，其他相近的亦可見，例如“ Trench Storage Node Technology for Gigabit DRAM Generations, K. P. Muller et al. 1 996 IEEE，IEDM 96-507” ，請見 “ A 0 · 6 μπι2 2 5 6Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST), L. Nesbit et al, 1 993 IEEE， IEDM 93-627 ” 以及 “ SCALABILITY OF A TRENCH CAPACITOR CELL FOR 64 MBIT DRAM, B. W. Shen et al, 1 989 IEEE, IEDM 89-2 7，， 〇 (請先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準·（ CNS ) A4規格（210X 297+釐） 541667 A7 B7 五、發明説明（） 另一增加每單位面積容量的方法是在電容末端蝕刻 一凹槽，如此可增加電容面積，例見美國專利第4 J25,945 號及美國專利第5,374 J80淼- 發明概述= 形成一包含二氧化石夕層及氮化石夕層之堆疊層，钱刻 堆疊層以侵蝕二氧化矽層或氮化矽層，利用具高選擇性蝕 刻法可達到目的。在此狀況下，二氧化矽層及氮化矽層有 不同的蝕刻速率，一多晶矽層以傳統的 LPCVD製程沉積 於已被蝕刻的堆疊層上，利用乾式蝕刻法蝕刻多晶矽層使 氮化矽層之上端暴露出，多晶矽以非等向性回蝕，因此在 堆疊層之側壁形成間隙壁，二氧化矽層及氮化矽層分別以 不同蝕刻劑除去，形成具有多晶矽水平鰭狀之冠狀結構， .絕緣層沿著冠狀結構表面形成，隨後一多晶矽層沉積在絕 緣層上。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) Μ式ffi單說明z 參考下述說明連同隨附圖式，此發明的前述關點及 許多附帶的優點將變得更容易認識及較多的了解，其中： 本纸張尺度適用中國國家標準（CNS ) A4規格（21〇X29*7备瘦） 經濟部中央標準局員工消費合作社印製 541667 A7 B7 五、發明説明（） 圖1為一半導體晶圓之剖面圖說明半導體基材形成 導電結構之步驟。 圖 2為一半導體晶圓之剖面圖說明於導電結構上形 成一堆疊層之步驟，电含間隔的二氧化矽層及 氮化矽層。 圖3為一半導體晶圓之剖面圖說明蝕刻堆疊層之步 騾。 圖 4為一半導體晶圓之剖面圖說明於堆疊層上形成 多晶矽層之步驟。 圖 5為一半導體晶圓之剖面圖說明回蝕多晶矽層形 成間隙壁之步驟。 圖 6為一半導體晶圓之剖面圖說明除去堆疊層之步 騾。 圖 7為一半導體晶圓之剖面圖說明依據本發明形成 絕緣層及多晶矽層之步驟。 發明掸細說明： 利用氮化矽層及CVD二氧化矽層之間高蝕刻選擇性 形成一水平.鰭狀電容，如下所示’此技術可形成具有水平 鰭狀之冠狀電容。 本紙張尺度適用中國國家標隼（CNS ) Α4規格（210Χ29»脅） ---------ί——^^-Iΐτ------^ (請先閱讀背面之注意事項再填寫本頁) 541667 A7 _____ _B7 五、發明説明（） -一- 參考圖1，準備一有<100>結晶方向的 J平日日石夕基材2， 形成一厚的場氧化區域（F0X)4提供隔離基 1 J △工 < 7L 件， FOX區域4以傳統方法產生。 其次，於基材2表面上方形成二氧化矽層6做為隨 後形成之金氧矽場效電晶體（Μ 〇 S F E T)之閘氧化‘，在此 實施例中二氧化矽層6之厚度約3〇_2〇〇Α ;利用低壓化學 氣相沉積製程（LPCVD)在FOX區域4及二氧化碎層6上 形成摻雜多晶矽層8，此實施例中，多晶矽層8厚度約 5 00-2000入。然後利用標準微影及蝕刻方法用來形成閘結 構1 2及内連線1 4，隨後主動區域} 6 (即源極和汲極）利用 已知製程摻雜適當的雜質於那些區域而形成，然後在基材 2上形成一金屬層，微影及蝕刻製程用來蝕刻金屬層而形 成一位元線1 8，位元線製程之前，需一傳統位元線製程 以分隔位元線/字元線。 經濟部中央標準局員工消費合作社印^ 構成dram電晶體為已知技術且與本發明並無密切 關係’例如氧化物間隙壁20目的為分隔鄰近的結構，利 用化學氣相沉積（CVD)長成氧化層20，以TEOS為來源， 溫度介於攝氏650至750度，壓力為1至1〇〇托耳（t〇jrr)， 厚度約1000-20000 A，然後於氧化層20中暴露出部份基 材2形成接觸窗。 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨〇><297·备瘦） 541667 A7 B7 五、發明説明（ 導電結構24包含一導電栓塞於接觸窗22中，在接 觸窗22及氧化層20之上形成，此實施例中導電結構24 為多晶矽以傳統的低壓化學氣相沉積（LPCVD)形成，導電 結構24之厚度最理想為5〇〇-1〇〇〇人，導電結構選自摻雜 夕a曰石夕或同步摻雜多晶石夕，而銘、銅、鎢、鈦皆可用為導 電結構24。 接圖2，一堆疊層包含間隔的二氧化矽層26及氮化 矽層28形成在導電結構24上，堆疊層可以在堆疊層上* 覆地沉積而形成，堆疊層為奇數層和偶數層所構成，奇數 層可能是一乳化石夕層而偶數層可能是氮化石夕層，或者=數 層為氮化矽層而偶數層為二氧化矽層，堆疊層的541667 A7 __ 5. Description of the invention () The invention of Cheng Cheng: This invention relates to a method for manufacturing a semiconductor device, especially a method for forming a dynamic random access memory (DRAM) memory cell. The invention relates to a method for forming a DRAM memory cell capacitance. The threat of the invention: In recent years, the development of semiconductor devices is to integrate many components on one chip. 'High-density memory cells have been developed, especially dynamic random access memory (DRAM) has been developed towards high-density packaging. DRAM is widely used in computer technology, and has been manufactured using high-density integrated circuit technology. The industry has grown from 16K-bit capacity DRAM to higher than 64M-bit capacity DRAM. Traditionally, DRAM memory cells are used to store computer data. This is printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling in the page line! Semiconductor memory components have large capacitance to read Output and store information, because it can only temporarily retain information even if the power is continuously supplied, so Wenyan & Yaishi is dynamic random access memory (DRAM); therefore, the memory must be read every period β period And charging. A integrated circuit DRAM element has traditionally been a guest. It is also a coincidence. In fact, a memory cell provides a bit to be stored in dram-/ φ — 1 o'clock. The paper size of the mother paper is applicable to China. Standard (CNS) A4 specification (21〇 × 2972 ^ centimeter) 541667 A7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention A memory cell traditionally contains a storage capacitor and a ^ pass transistor. One of the source or drain is connected to one end of the valley, and the other end of the transistor channel and the transistor's question terminal are connected to the external circuit as a bit line and a word line, respectively. word line). The other end of Lei Liukong Baogu is connected to a reference voltage. The formation of DRAM memory cells includes the production of transistors, capacitors, and external circuits. In order to obtain high-density dram components, the memory cell size must be reduced to the sub-micron range. Reduction in capacitance area leads to reduction in memory cell capacity. Previous technologies have developed stack i. Capacitors to almost overcome these problems. Tuan has applied for a capacitor with a rugged surface to increase the capacitance area (US Patent No. 5,266'14). Amorphous pieces are tempered at about 875 degrees Celsius to roughen their surface. Another type of capacitor is also referred to as a trench capacitor. One of the previous technologies is related to each other: see US Patent No. 5.374,580. In addition, Other similar ones can also be seen, for example, "Trench Storage Node Technology for Gigabit DRAM Generations, KP Muller et al. 1 996 IEEE, IEDM 96-507", see "A 0 · 6 μπι2 2 5 6Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST), L. Nesbit et al, 1 993 IEEE, IEDM 93-627 "and" SCALABILITY OF A TRENCH CAPACITOR CELL FOR 64 MBIT D RAM, BW Shen et al, 1 989 IEEE, IEDM 89-2 7 ,, 〇 (Please read the notes on the back before filling out this page) The size of the paper is applicable to the Chinese national standard ((CNS) A4 specification (210X 297+ (%) 541667 A7 B7 V. Explanation of the invention () Another method to increase the capacity per unit area is to etch a groove at the end of the capacitor, which can increase the area of the capacitor. For example, see US Patent No. 4 J25,945 and US Patent No. 5,374 J80miao-Summary of the invention = Form a stacked layer including a dioxide dioxide layer and a nitrided stone layer, and engraved stacked layers to etch the silicon dioxide layer or silicon nitride layer. The purpose can be achieved by using a highly selective etching method. Under this condition, the silicon dioxide layer and the silicon nitride layer have different etching rates. A polycrystalline silicon layer is deposited on the etched stack layer by a conventional LPCVD process, and the polycrystalline silicon layer is etched by dry etching to make the silicon nitride layer. The upper end is exposed, and the polycrystalline silicon is etched back anisotropically. Therefore, a gap wall is formed on the side wall of the stacked layer. The silicon dioxide layer and the silicon nitride layer are respectively removed with different etchant to form a crown structure with horizontal polycrystalline silicon fins. The insulating layer is formed along the surface of the crown structure, and then a polycrystalline silicon layer is deposited on the insulating layer. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). Description of the M-type list. Z Refer to the following description together with the accompanying drawings. The aforementioned points of the invention and many additional advantages. It will become easier to understand and understand more, of which: This paper size applies the Chinese National Standard (CNS) A4 specification (21 × 29 * 7 thin) Printed by the Central Consumers Bureau of the Ministry of Economic Affairs Consumer Cooperatives 541667 A7 B7 5 Explanation of the invention () FIG. 1 is a cross-sectional view of a semiconductor wafer to explain the steps of forming a conductive structure on a semiconductor substrate. FIG. 2 is a cross-sectional view of a semiconductor wafer illustrating the steps of forming a stacked layer on a conductive structure, electrically containing a spaced silicon dioxide layer and a silicon nitride layer. FIG. 3 is a cross-sectional view of a semiconductor wafer illustrating the steps of etching a stacked layer. FIG. 4 is a cross-sectional view of a semiconductor wafer illustrating the steps of forming a polycrystalline silicon layer on a stacked layer. FIG. 5 is a cross-sectional view of a semiconductor wafer illustrating a step of etching back a polycrystalline silicon layer to form a spacer. FIG. 6 is a cross-sectional view of a semiconductor wafer illustrating the steps of removing the stacked layers. FIG. 7 is a cross-sectional view of a semiconductor wafer illustrating the steps of forming an insulating layer and a polycrystalline silicon layer according to the present invention. Detailed description of the invention: A horizontal fin capacitor is formed by using a high etching selectivity between a silicon nitride layer and a CVD silicon dioxide layer, as shown below 'This technique can form a crown capacitor with a horizontal fin shape. This paper size applies to China National Standard (CNS) Α4 specification (210 × 29 »threat) --------- ί —— ^^-Iΐτ ------ ^ (Please read the precautions on the back before (Fill in this page) 541667 A7 _____ _B7 V. Description of the invention ()-a-Referring to Figure 1, prepare a J weekday stone evening substrate 2 with a crystal orientation of < 100 > to form a thick field oxidation area (F0X) 4 provides a spacer 1 J △ < 7L pieces, and the FOX region 4 is produced by a conventional method. Secondly, a silicon dioxide layer 6 is formed on the surface of the substrate 2 as a gate oxide of a subsequently formed gold-oxide-silicon field-effect transistor (MOSFET). In this embodiment, the thickness of the silicon dioxide layer 6 is about 3 〇_2〇〇Α; The low-pressure chemical vapor deposition process (LPCVD) is used to form a doped polycrystalline silicon layer 8 on the FOX region 4 and the fragmentary oxide layer 6. In this embodiment, the thickness of the polycrystalline silicon layer 8 is about 500-2000 Å. . Then, standard lithography and etching methods are used to form the gate structure 12 and interconnects 14 and then the active regions} 6 (that is, the source and drain) are formed by doping appropriate regions with appropriate impurities in known processes. A metal layer is then formed on the substrate 2. The lithography and etching process is used to etch the metal layer to form a bit line 18. Before the bit line process, a traditional bit line process is required to separate the bit lines / words. Yuan line. Printed by the Consumers 'Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ The formation of a dram transistor is a known technology and is not closely related to the present invention.' For example, the oxide spacer 20 is used to separate adjacent structures and is grown by chemical vapor deposition (CVD) The oxide layer 20 uses TEOS as the source, the temperature is between 650 and 750 degrees Celsius, the pressure is 1 to 100 Torr (t0jrr), and the thickness is about 1000-20000 A. Then, a part of the oxide layer 20 is exposed The base material 2 forms a contact window. This paper size applies the Chinese National Standard (CNS) A4 specification (2 丨 〇 < 297 · prepared thin) 541667 A7 B7 V. Description of the invention (The conductive structure 24 includes a conductive plug in the contact window 22, and the contact window 22 And the oxide layer 20 is formed. In this embodiment, the conductive structure 24 is formed of polycrystalline silicon by conventional low-pressure chemical vapor deposition (LPCVD). The thickness of the conductive structure 24 is preferably 5,000 to 100,000. The conductive structure is It is selected from the group consisting of doped stone and polycrystalline stone, and Ming, copper, tungsten, and titanium can be used as the conductive structure 24. As shown in FIG. 2, a stacked layer includes a spaced silicon dioxide layer 26 and nitrogen. The siliconized layer 28 is formed on the conductive structure 24. The stacked layer can be formed on top of the stacked layer *. The stacked layer is composed of odd and even layers. The odd layer may be an emulsified stone layer and the even layer may be Nitride stone layers, or = several layers are silicon nitride layers and even layers are silicon dioxide layers.
丄故4 口J 持續地進行藉由連續地改變加入反應室的氣體。 接下圖3’堆疊層利用光阻（未圖示）定義儲存電極區 域’堆疊層被回姓直到導電結構24，然後濕式钱刻法用 經濟部中央標隼局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 來侵餘二氧化石夕層26 ’如圖4。在此實施例中，一一 1 一具有向 選擇性蝕刻法被用來達成此目的，在此狀況下，二氧化石夕 層26及氮化矽層28有不同的蝕刻速率，例如稀釋的氮鼠 酸溶液為蝕刻劑，BOE(緩衝氧化蝕刻劑）溶液或稀釋的氮 氟酸溶液以氟化銨緩衝亦可作為堆疊層之蝕刻劑。此外， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 541667 五、發明説明（) HF洛氣亦可被利用。本發明的關鍵在於 性甚大於氮彳匕石夕，此沾果^ π 氧化石夕被链刻 4, 果在於-乳化石夕層26 t匕氮… U刻t顯者’熱錢溶液可被選擇性地使用㈣ 幻氣化石夕層28，使用餘刻劑可得到高選擇性姓刻的目的。 參考圖4,多晶石夕層30利用傳統的Lpc 在被蝕刻的堆疊層及導，紝 红/儿積 导電結構24上，多晶矽層3 於二氧化❹26&氮化石夕層2 被真 夕日日矽層3 0選自 摻雜多晶矽及同步摻雜多晶矽。 、㈢ 其次，如圖5，乾式姓刻法被用於姓刻多晶石夕而暴露 出堆疊層的頂端（氮化矽層28或二氧化 層則皮非等向性回钱，因此形成間隙壁在堆叠層 上。 土 經濟部中央標隼局員工消費合作社印聚 接下圖6,氮切層28及：氧切層26以改變餘刻 劏分別除去，氮化矽層28可利用熱磷酸溶液剝落而二氧 化矽層可利用HF或B0E(緩衝氧化蝕刻劑）溶液剝除，因 此形成具有水平趙狀的多晶矽冠肤钴搆，具水平鰭狀的冠 狀結構做為電容的第一館存電極。 如圖7，絕緣層3 2沿著冠狀結構及導電結構24表 % 本紙張尺度適用中國國家標準（CNS ) A4規格（210X势7公釐） 541667 A7 B7 五、發明説明（） 形成，絕緣層3 2最好形成氮化物/氧化物雙層薄膜或氧化 物/氮化物/氧化物三層薄膜或其他高絕緣薄膜如氧化钽 (Ta205)。最後多晶矽層34以傳統LPCVD製程沉積在絕 緣層 3 2上方作為第二儲存電極，來自摻雜多晶矽及同步 換雜多晶石夕。本發明因此提供加大表面積之電容，所以本 發明增加電容的性能。 本發明以一較佳實施例說明如上，僅用於藉以幫助 了解本發明之實施，非用以限定本發明之精神，而熟悉此 領域技藝者於領悟本發明之精神後，在不脫離本發明之精 神範圍内，當可作些許更動潤飾及等同之變化替換，其專 禾】保護範圍當視後附之申請專利範圍及其等同領域而定。 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X炎7公釐）For this reason, port J is continuously performed by continuously changing the gas to be added to the reaction chamber. Continued in Figure 3 below. The stacked layer uses a photoresist (not shown) to define the storage electrode area. The stacked layer is returned to the conductive structure 24, and then the wet money engraving method is printed using the staff consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please First read the notes on the back and then fill out this page) to invade the dioxide dioxide layer 26 'as shown in Figure 4. In this embodiment, a one-to-one selective etching method is used to achieve this purpose. Under this condition, the SiO 2 layer 26 and the silicon nitride layer 28 have different etching rates, such as diluted nitrogen. The murine acid solution is an etchant. A buffered BOE (buffered oxidizing etchant) solution or a dilute nitric acid solution buffered with ammonium fluoride can also be used as an etchant for stacked layers. In addition, this paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) 541667 5. Description of the invention () HF gas can also be used. The key point of the present invention is that the property is much higher than that of nitrogen dagger stone, and this dipped fruit ^ π oxidized stone is carved by chain 4, the fruit lies in-emulsified stone layer 26 t nitrogen ... U carved t display 'hot money solution can be selected The use of ㈣ magic gas fossil evening layer 28, and the use of residual etching agent can achieve the purpose of highly selective surname engraving. Referring to FIG. 4, the polycrystalline silicon layer 30 uses a conventional LPC on the etched stacked layer and the conductive red / earth conductive structure 24, and the polycrystalline silicon layer 3 is formed on the hafnium dioxide 26 & nitride nitride layer 2 The silicon layer 30 is selected from doped polycrystalline silicon and synchronously doped polycrystalline silicon. Second, as shown in Figure 5, the dry-type surname engraving method is used to sculpt polycrystalline stones to expose the top of the stacked layer (the silicon nitride layer 28 or the dioxide layer is anisotropic to return money, so a gap is formed. The walls are on stacked layers. The following figure 6 shows the nitrogen consumption layer 28 and the oxygen cutting layer 26 to change the remaining cuts. The silicon nitride layer 28 can use hot phosphoric acid. The solution is peeled off and the silicon dioxide layer can be peeled off using HF or B0E (buffered oxide etchant) solution. Therefore, a polycrystalline silicon crown-cobalt structure with horizontal Zhao shape is formed, and a crown structure with horizontal fins is used as the first storage of the capacitor. Electrode. As shown in Figure 7, the insulating layer 32 is along the crown structure and the conductive structure 24%. This paper size applies the Chinese National Standard (CNS) A4 specification (210X potential 7 mm). 541667 A7 B7. The insulating layer 32 is preferably formed as a nitride / oxide double-layer film or an oxide / nitride / oxide triple-layer film or other highly insulating film such as tantalum oxide (Ta205). Finally, the polycrystalline silicon layer 34 is deposited on the insulation by a conventional LPCVD process. Above layer 3 2 is used as the second stored electricity It comes from doped polycrystalline silicon and synchronously doped polycrystalline stone. The invention therefore provides a capacitor with increased surface area, so the invention increases the performance of the capacitor. The invention is described above with a preferred embodiment, and is only used to help understand the present invention. The implementation of the invention is not intended to limit the spirit of the present invention, and those skilled in the art can understand the spirit of the present invention and make minor changes and replacements without departing from the spirit of the present invention. Specialty] The scope of protection depends on the scope of the patent application and its equivalent fields. (Please read the precautions on the back before filling out this page.) Printed on the paper standard printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. (CNS) A4 specification (210X Yan 7 mm)