GB2336716A

GB2336716A - DRAM cell capacitor and method for fabricating thereof

Info

Publication number: GB2336716A
Application number: GB9905192A
Authority: GB
Inventors: Byung-Jun Park
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1998-04-25
Filing date: 1999-03-05
Publication date: 1999-10-27
Anticipated expiration: 2019-03-05
Also published as: GB9905192D0; CN1236993A; TW412828B; JP2000022099A; GB2336716B; KR19990081113A; FR2778019A1; DE19908446A1; KR100270210B1

Abstract

A double pole type stacked capacitor is constituted by a first pole 38 and a second pole 44 which are spaced apart from each other but electrically connected to each other through a conductive pattern 24a. The method for fabricating the capacitor on a substrate 10 includes the step of forming a conductive layer pattern 24a over a first layer 18, 20 having a storage contact pad 16 thereunder, sequentially forming a second insulating layer 28 and a first material layer 30 over the first insulating layer including the conductive layer pattern 24a, sequentially etching the first material layer 30, the second insulating layer 28, and the conductive layer pattern 24a using a first photolithography, and thereby forming a first opening 32 to the first a insulating layer over the one of the storage contact pads, the first opening penetrating one end of the pattern 24a, forming conductive sidewall spacers 34 in the first opening, using the sidewall spacers 34 and the first material layer as a mask and etching the first insulating layer down to the one of the storage contact pads 16, and thereby forming a second opening 36, depositing a conductive material in the first and second openings and over the first material layer and planarizing down to the second insulating layer 28 to form a first conductive pole 38, etching the second insulating layer until the first insulating layer and the other end of the conductive layer pattern 24a is exposed using a second photolithography, and thereby forming a third opening (42) spaced apart from the first opening, and filling the third opening with the same material as the first conductive pole to form a second conductive pole 44.

Description

0 2336716 DRAM CELL CAPACITOR AND METHOD FOR FABRICATING THEREOF The

present invention relates to a semiconductor device, and more particularly to a DRAM cell capacitor with increased surface areas and a method for fabricating thereof.

The acquisition of sufficient charge-storage capacitance in a small area is one of the most challenging design problems of Ultra Large Scale Integration( ULSI) Dynamic Random Access Memory( DRAM) technology. As the push for higher density DRAMs increases, the charge-storage device of each memory cell must physically fit into a smaller and smaller area. The decrease in cell capacitance caused by reduced memory cell area is a serious obstacle to increasing packing density in DRAMs. Thus, the problem of decreased cell capacitance must be solved to achieve higher packing density in a semiconductor memory device.

In order to keep a capacitance of such capacitor at an acceptable value, stacked capacitors having a three-dimensional structure have been suggested. Such stacked capacitors include, for example, cylindrical and simple box structured capacitors. Since both outer and inner surfaces can be utilized as an effective capacitor area, the cylindrical structure is favorably suitable to the three-dimensional stacked capacitor. Recently, new technologies have been developed for increasing the effective surface area by modifying the surface morphology of the polysilicon storage electrode itself by engraving or controlling the nucleation and growth condition of polysilicon. A hemispherical - grain(H SG) polysilicon layer can be deposited over a storage electrode to increase surface area and capacitance.

However, the limits of the photolithography process make it difficult to pattern such cylindrical capacitor in ultra large scale integrated circuits application and the formation of 1 HSG silicon is subjected to cause short between adjacent storage electrodes and requires the process complexity. On the other hand, the simple box structured capacitor has disadvantages that it cannot provide sufficient capacitance.

Accordingly there is a strong need for a process which can provide a capacitor with a very large surface area of a storage electrode for high capacitance while minimizing process complexity.

The present invention was made in view of the above problem, and it is therefore an object of the invention to provide a capacitor with significantly increased surface areas and a method for fabricating thereof with process simplicity. To this end, the present invention provides a double pole type capacitor wherein one conductive pole of polysilicon is electrically connected to the other conductive pole of polysilicon through a conductive layer pattern of polysilicon(i.e., connecting bridge). One of the conductive poles penetrates through the polysilicon pattem and insulating layers, and reaches to underlying contact pad(or diffusion layer). The connecting bridge is formed after forming one of the conductive pole contact with the contact pad and before forming the other conductive pole. The conductive pole in contact with the contact pad( or diffusion layer) is formed in self aligned manner by using conductive side wall spacers of polysilicon. To briefly, a first opening is formed in an insulating layer and then side wall spacers are formed therein. After that, a second opening is formed in underlying another insulating to contact pad using the spacers as a mask. A conductive layer for storage electrode is deposited in the first and second openings to form the first conductive pole. Therefore, there is no possibility of misalignment between first opening and second opening, corresponding to misalignment between storage contact hole and storage electrode.

To achieve these and other advantages and in accordance with the purpose of the present invention, the method for fabricating the double pole type capacitor includes forming a device isolating layer on a semiconductor substrate to define active and inactive regions.

2 gate electrode and a source/drain region are formed on and in the semiconductor substrate.

first oxide layer is formed over the entire semiconductor substrate. A storage contact pad is formed in the oxide layer to the source/drain region by a suitable method. A second oxide layer is formed over the first oxide layer and on the contact pad. A bit line is formed on the second oxide layer. A third oxide layer and a silicon nitride layer are sequently formed over the second oxide layer and on the bit line.

A first polysilicon layer is deposited over the silicon nitride layer for use as the connecting bridge between two conductive poles. The first polysilicon layer is then pattern to form a first poly pattern novel to this invention which overlaps contact pad and extends in a side direction of the contact pad. A fourth oxide layer called, sacrificial oxide layer is formed over the silicon nitride layer and on the poly pattern. This sacrificial oxide layer has a thickness to that determines the height of the storage electrode, therefore the thickness thereof varies depending on the desired capacitance. Preferably to a thickness of about 8,oooA to i mook A material layer having an etch selectivity with respect to the fourth oxide layer is deposited thereover for use as an etch mask in subsequent etching of the fourth oxide layer. For example polysilicon layer may be used as this material layer., A first photoresist layer is coated over the material layer of polysilicon and patterned to form an opening portion aligned over one end portion of the poly pattern. Using this first patterned photoresist layer, the material layer, the fourth oxide layer, the poly pattern, and the silicon nitride layer are etched to form a first opening having substantially vertical side walls down to third oxide layer. It must be noted that a portion of the poly pattern is buried in the fourth oxide layer and aligned to one side wall of the first opening and over the silicon nitride layer. After removing the first patterned photoresist layer, a conductive side wall spacers of polysilicon are formed in the first opening to a thickness of about 250A. Using the polysilicon material layer and polysilicon side wall spacers as etch mask, the third and second oxide layers are etched down to the contact pad thereby to form a second opening.

Due to these side wall spacers, the second opening is self aligned to the first opening. A storage electrode material, i.e., polysilicon layer is deposited in the first and second openings 3 and over the polysilicon material layer and then planarized down to the fourth oxide layer thereby forming a first conductive pole of polysilicon for the double pole type storage electrode.

A second photoresist layer is coated over the fourth oxide layer and patterned to form an opening portion aligned over the poly pattern and a portion of the silicon nitride layer. Using the second patterned photoresist layer, the fourth oxide layer is etched down to the poly pattern and silicon nitride layer, and thereby to form a third opening. Herein, a portion of the poly pattern is buried in the fourth oxide layer and aligned to the side wall of the first conductive pole. This third opening is separated from the first conductive pole by about 1 0Onm and electrically connected to the first conductive pole through the remainder of the poly pattern buried in the fourth oxide layer. Namely, the remainder of the poly pattern protrudes from thee one side wall of the first conductive pole into the third opening. After removing the second patterned photoresist, a conductive material for storage electrode, i.e., polysilicon is deposited in the third opening to form a second conductive pole for the double pole type storage electrode. As understood from the above explanation, the second conductive pole is connected to the first conductive pole through remainder of the poly pattern at the bottom portion. Accordingly, double pole type capacitor is completely formed.

The number the second conductive pole can be increased so as to further increase the surface areas. Subsequently, a dielectric film and a top electrode are formed over the storage electrode and thereby forming the capacitor.

This capacitor has advantages that it has increased surface area by forming additional storage electrode(second conductive pole) and connecting to the main storage electrode through the connecting bridge( poly pattern). Furthermore, the main storage electrodeffirst conductive pole) is formed in a self aligned manner by utilizing polysilicon side wall spacers and the process step of main storage electrode can be simplified.

The invention may be understood and its objects will become apparent to those 4 skilled in the art by reference to the accompanying drawings as follows:

Fig.1A to Fig.1G show, at selected stages of fabricating, the crosssectional views taken along bit line direction of a DRAM cell capacitor in accordance with an embodiment of the present invention; Fig.2A to Fig.2G show, at selected stages of fabricating, the cross- sectional views taken along word line direction of a DRAM cell capacitor in accordance with an embodiment of the present invention; Fig.3 is a top plan view of a DRAM cell capacitor after forming a poly pattern in accordance with the embodiment of the present invention; Fig.4 is a top plan view of a DRAM cell capacitor after forming a first opening in accordance with the embodiment of the present invention; Fig.5 is a top plan view of a DRAM cell capacitor after forming side wall poly spacers in the first opening and then forming a second opening in accordance with the embodiment of the present invention; Fig.6 is a top plan view of a DRAM cell capacitor after forming a second conductive pole in accordance with the embodiment of the present invention; and Fig.7 shows schematically resultant double pole type storage electrode structures in accordance with the embodiment of the present invention.

A preferred embodiment of the present invention will now be described by way of example with reference to the accompanying drawings. The present invention relates to a DRAM cell capacitor and a method for fabricating the same. 7he process for forming the field oxide layer and the field effect transistor structure as presently practiced in manufacturing DRAM cells are only briefly described in order to better understand the current invention. Fig. 1 A to Fig. 1 G show, at selected stages of fabricating, the cross-sectional views taken along bit line direction of a DRAM cell capacitor in accordance with an embodiment of the present invention and Fig.2A to Fig.2G show, at selected stages of fabricating, the cross-sectional views taken along word line direction of a DRAM cell capacitor in accordance with an embodiment of the present invention. In Fig.2A to Fig. 2G, the same parts function as shown in Fig. IA to Fig.1G are identified with same reference numbers and for the shake of better understanding of this invention, the preferred embodiment of the present invention 5 will be described with reference to Fig. 1 and Fig.2 concurrently.

Referring now to Fig. IA and Fig.2A, a device isolation layer 12, i.e., field oxide layer, is formed at a predetermined region of a semiconductor substrate 10 to define an active region 11 and an inactive region thereon. The device isolation layer 12 is formed by conventional techniques such as shallow trench isolation. Local oxidation of silicon may be alternatively used. A plurality of gate electrodes 14 with protecting insulating layer(i.e., hard mask and side wall spacers) are formed on the semiconductor substrate 10 using conventional photolithography and etching process. A plurality of source/drain regions(not shown) are formed in the semiconductor substrate 10 aligned with lateral edges of the gate electrodes 14 using conventional ion implanting process. A first oxide layer 15 is formed over the entire semiconductor substrate 10 including the gate electrodes 14. A plurality of storage contact pads 16 are formed in the first oxide layer 15 to the source/drain regions by a suitable method. A second oxide layer 18 is formed over the first oxide layer 15 and on the contact pads 16. A plurality of bit lines 19 are formed on the second oxide layer 18. A third oxide layer 20 is formed over the second oxide layer 18 and on the bit lines 19. A layer 22 which has an etch selectivity with respect to the third oxide layer 20, for example a silicon nitride layer 22 is formed on the third oxide layer 20. This silicon nitride layer 22 is used as an etch stop layer in subsequent etching of a fourth oxide layer and may not be formed.

The next step is critical to this invention. A first polysilicon layer 24 is deposited over the silicon nitride layer 22 for use as the electrical connecting bridge 24a between two conductive poles 3 8 and 44 of Fig. 1 G which constitute a storage electrode 46 together with the connecting bridge 24a. This first polysilicon layer 24 is formed to have a thickness of about 550 AO to 1,000A.

6 Referring to Fig. 1 B and Fig.213, a first photoresist layer is coated over the first polysilicon layer 24 and patterned 26. Using this first patterned photoresist layer 26, the first polysilicon layer 24 is then etched down to the silicon nitride layer 22 to forTn a plurality of poly patterns (connecting bridges) novel to this invention. For example a poly pattern 24a is formed which overlaps the contact pad 16 and extends in a lateral direction of the contact pad 16. Detailed explanation will be given with reference to Fig.3, a top plan view of a DRAM cell capacitor after forming the poly patterns 24a. In Fig.3, the poly pattern 24a is formed over the silicon nitride layer 22 at a predetermined pattern. The poly pattern 24a is formed to overlap a portion of the active region 11, more specifically aligned over the contact pad 16 for the storage electrode and concurrently disposing the contact pad 16 below at one end of the poly pattern 24a. The poly pattern 24a has eclipse shape or rectangle shape and the longer direction(" a") of the poly pattern 24a is about 35Onin, the shorter direction("c ") thereof is about 150nm. The distance between adjacent poly patterns aligned along with bit line direction(" b ") is about 250run and the distance between adjacent poly patterns aligned along with word line direction("d") is about 150nm.

Referring now to Fig. 1 C and Fig.2C, after removing the first patterned photoresist layer 26, a fourth oxide layer 28, called sacrificial oxide layer, is formed over the silicon nitride layer 22 and on the poly pattern 24a. This sacrificial oxide layer 28 has a thickness to that determines the height of the storage electrode, therefore the thickness thereof varies depending on the desired capacitance. In this embodiment, the sacrificial oxide layer 28 is formed to have a thickness of about 8,OOOA to 1 1,000A. A material layer 30 having an etch selectivity with respect to the fourth oxide layer 28 is deposited over the fourth oxide layer 28 for use as an etch mask in subsequent etching of the fourth oxide layer28. For example polysilicon layer may be used as this material layer and has a thickness of about 1,500A to 2,oooA, A second photoresist layer is coated over the material layer 30 and patterned 31 to form opening portions aligned over one end of the poly pattern 24a which is aligned over the contact pad 16. Using this second patterned photoresist layer 3 1, the material layer 30, 7 the fourth oxide layer 28, the poly patterns 24a, and the silicon nitride layer 22 are etched to form a plurality of first openings. For example a first opening 32 is formed which has substantially vertical side walls down to the third oxide layer 20. It must be noted that a portion of the poly pattern 24a is buried in the fourth oxide layer 28 and aligned to one side walls of the first opening 32 and over the silicon nitride layer 22. This first opening 32 is formed to have an opening size("e") of about 150rim. Fig.4 is a top plan view of a DRAM cell capacitor after forming the first opening32. Referring to Fig.4, thefirst opening 32 is aligned at one end of the poly pattern 24a over contact pad 16.

After removing the second patterned photoresist layer 3 1, a conductive side wall spacers 34 are formed in the first openings 32 with polysilicon to a thickness of about 250A as shown in Fig. IE and Fig.2E. Using the polysilicon material layer 30 and polysilicon side wall spacers 34 as etch mask, the third and second oxide layers 20 and 18 are etched down to the contact pads 16 thereby to form a plurality of second opening. For example a second opening 36 is formed to have an opening size of about 10Onm. Due to these side wall spacers 32, the second opening 36 is self aligned to the first opening 32. Herein the second opening 32 is corresponding to contacthole for storage electrode of conventional simple box type capacitor. Therefore, misalignment between storage contact hole and storage electrode encountered in the prior art can be avoided. Fig.5 is a top plan view of a DRAM cell capacitor after forming side wall poly spacers 34 in the first opening 32 and forming the second opening 36. As can be seen, the second opening 36 is smaller than the first opening 32 by the thickness of the side wall poly spacers 34.

Referring to Fig. IF and Fig.2F, a conductive material such as polysilicon for storage electrode is deposited in the first and second openings 32 and 36 and over the polysilicon material layer 30. Planarization etching is performed on the polysilicon and polysilicon material layer 30 down to the fourth oxide layer 28 to form a plurality of first conductive poles for the storage electrodes. For example a first conductive pole 38 is formed to the contact pad 16. Planarization etching may be CMP(chernical mechanical polishing) or etchback technique. As described above, the poly pattern 24a is electrically connected to one 8 lateral edge of first conductive pole 3 8 and outward extends on the silicon nitride layer 22. Formation of second conductive poles is next addressed. The second conductive pole is required to be connected to the first conductive pole 38 through poly pattern 24a protruding from the lateral edge of the first conductive pole 38. To this end, a second photoresist layer is coated on the fourth oxide layer 28 and patterned 40 to form opening portions aligned over the other end portion of poly pattern 24a and the silicon nitride layer 22. Using this patterned third photoresist layer 40, the fourth oxide layer 28 is etched to form a plurality of third opening. For example a third opening 42 is formed to the other end portion of the poly pattern 24a and the silicon nitride layer 22. Herein, the poly pattern 24a and silicon nitride layer 22 serve as etch stop layers. In case that the silicon nitride layer 22 is not formed, this etching the fourth oxide layer 28 is carried out by time etch. In this embodiment, the third opening 42 has an opening size(W) of about 20Onm and is spaced apart from the first conductive pole 32 by about 10Onm("g").

After removing the third patterned photoresist layer 40, a conductive material for storage electrode, i.e., polysilicon is deposited in the third openings and over the fourth oxide layer 28. Planarization etching is carried out on the polysilicon down to the fourth oxide layer 28 and thereby to forTn a plurality of second conductive poles for the storage electrodes. For example a second conductive pole 42 is formed to be electrically connected to the first conductive pole 38 through the poly pattern 24a. After that, the fourth oxide layer 28 is then removed in wet etchant and thereby forming a plurality of double pole type storage electrodes 46 each constituted by the first conductive pole 3 8, the second conductive pole 44, and the poly pattern 24a as shown in Fig. 1 G and Fig.2G. The number of the second conductive pole 44 can be increased so as to further increase the surface areas.

Fig.6 is a top plan view of a DRAM cell capacitor after forming the second conductive pole 44. Referring to Fig.6, the doble pole type storage electrode includes the first conductive pole 3 8 which is in contact with storage contact pad(not shown), the second conductive pole 44, and the poly pattern 24a which connects them. The distance("i") between adjacent storage electrodes measured along the bit line direction is about 150nm.

9 i The distance between adjacent storage electrodes measured along the word line direction is about 150nm.

Subsequently, a dielectric film(not shown) and a top electrode(not shown) are formed on the storage electrode 46 and thereby forming the double pole type capacitor. Thus formed capacitor has advantages that it has increased surface area by forming additional storage electrode(second conductive pole) and connecting to the main storage electrode through the connecting bridge(poly pattern). Furthermore, the main storage electrodeffirst conductive pole) is formed in a self aligned manner by utilizing polysilicon side wall spacers and the process step of main storage electrode can be simplified. According to this invention, since the surface areas of the capacitor are increased sufficiently, desired capacitance can be obtained using Ta20, as the dielectric film though not using ferroelectric dielectric material such as BST whose formation is requiring high temperature and causes undesirable stress.

Fig.7 shows schernatically two neighbouring double pole type storage electrode structures in accordance with the present invention. The double pole type storage electrode structure will be addressed with reference to Fig. 1 G and Fig.7. The double pole type storage electrode 46 includes the first conductive pole 38, the second conductive pole 44, and the poly pattern 24a. The first and second conductive poles 3 8 and 44 are electrically connected to each other by the poly pattern 24a. The first conductive pole 38 penetrates the one end of the poly pattern 24a and reaches to the storage contact pad 16 which is in contact with the source/drain region. The second conductive pole 44 is in contact with the other end of the poly pattern 24a. The first conductive pole below the poly pattern 24a has a smaller size than that above the poly pattern 24a. It is apparent to one in the art that the number of the second conductive pole 44 may increase due to its size and the size of the poly pattern 24a.

The upper size of the first conductive pole 38 is about 150rim and bottom size thereof is about 1 0Onm. The size of the second conductive pole 44 is about 20Onm. The distance between adjacent storage electrodes is about 150nm and the distance between the first and second conductive pole is about 1 0Onm.

While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of this invention.

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Claims

What is claimed is:

1. A method for fabricating a DRAM cell capacitor comprising the steps of.

providing a semiconductor substrate having a gate electrode and a pair of sourceldrain regions aligned with lateral edges of said gate electrode; forming a pair of storage contact pads to said source/drain regions; forming a first insulating layer over said semiconductor substrate; forming a conductive layer pattern over said first insulating layer, said conductive layer pattern overlapping one of said storage contact pad and extending in a lateral direction of said one of said storage contact pad, said conductive pattern having two opposing ends; sequentially forming a second insulating layer and a first material layer over said first insulating layer including said conductive layer pattern, said first material layer having etch selectivity with respect to said second insulating layer; sequentially etching said first material layer, said second insulating layer, and said conductive layer pattern using a first photolithography, and forming a first opening to said first insulating layer over said one of said storage contact pad, said first opening penetrating one end of said conductive pattern; forming a conductive sidewall spacers in said first opening; using said sidewall spacers and said first material layer as a mask and etching said first insulating layer down to said one of said storage contact pad, and forming a second opening; depositing a conductive material in said first and second openings and over said first material layer and planarizing down to said second insulating layer to form a first conductive pole; etching said second insulating layer until said first insulating layer and the other end of said conductive layer pattern is exposed using a second photolithography, and forming a third opening spaced apart from said first opening; and filling said third opening with the same material as said first conductive pole to form 12 a second conductive pole, said second conductive pole being connected to said first conductive pole through said conductive layer pattern, wherein said first conductive pole, said second conductive pole, and conductive layer pattern constitutes a storage electrode of said DRAM cell capacitor.

2. A method according to claim 1, wherein said conductive layer pattern is made of the same material as said first conductive pole.

3. A method according to claim 1, wherein said second insulating layer has at 10 least the same thickness as said storage electrode.

4. A method according to claim 1, wherein said second insulating layer comprises an oxide layer and said first material layer comprises a polysilicon layer.

5. A method according to claim 1, wherein said conductive layer pattern has a thickness of about 550A to 1,000A and said second insulating layer has a thickness of about 8,OOOA to 11,000 A and said first material layer has a thickness of about 1,500A to 2,oooA.

6. A method according to claim 1, wherein said side wall spacers is made of the same material as said first pole.

7. A method according to claim 1, wherein said planarizing is carried out by CNIP or etch-back.

8. A method according to claim 1, wherein said first opening has a diameter of about 150nm, said second opening has a diameter of about 1 0Onm, and said third opening has a diameter of about20Onm.

13

9. A method according to claim 1, wherein said first conductive pole and said second conductive pole are spaced apart from each other by about 1 0Onm and said storage electrode is spaced apart from adjacent storage electrode by bout 150nm.

10. A method according to claim 1, further comprising, before said step of forming said conductive layer pattern, forming a second material layer over said first insulating layer, said second material layer having an etch selectivity with respect to said second insulating layer and serving as an etch stop layer during said step of forming third opening.

A method according to claim 10, wherein said second material layer is made of a silicon nitride layer.

12. A DRAM cell capacitor comprising:

a storage contact pad formed over a semiconductor substrate and electrically connected to a source/drain region of said semiconductor substrate; an insulating layer over said semiconductor substrate including said storage contact pad; and a storage electrode of said DRAM cell capacitor having a first and a second conductive poles, said first and second conductive poles being spaced apart from each other but electrically connected to each other though a conductive layer pattern formed over said insulating layer, said first conductive pole penetrating through said insulating layer and electrically being connected to said storage contact pad.

13. A DRAM cell capacitor according to claim 12, wherein said first conductive pole has a diameter of about 150nm at top portion and has a diameter of about 100= at bottom part in said insulating layer, and said second conductive pole has a diameter of about 20Onm.

14 1 14. A DRAM cell capacitor according to claim 12, wherein said first and second are spaced apart from each other by about 1 0Onm and said storage electrode is spaced apart from adjacent storage electrode by about 150nm.

15. A method of fabricating a DRAM cell capacitor substantially as hereinbefore described with reference to the accompanying drawings.

16. A DRAM cell a capacitor substantially as hereinbefore described with reference to the accompanying drawings.