KR100546112B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100546112B1 KR100546112B1 KR1019990063571A KR19990063571A KR100546112B1 KR 100546112 B1 KR100546112 B1 KR 100546112B1 KR 1019990063571 A KR1019990063571 A KR 1019990063571A KR 19990063571 A KR19990063571 A KR 19990063571A KR 100546112 B1 KR100546112 B1 KR 100546112B1
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- charge storage
- storage electrode
- polysilicon layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 38
- 229920005591 polysilicon Polymers 0.000 claims abstract description 30
- 150000004767 nitrides Chemical class 0.000 claims abstract description 11
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 52
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 6
- 239000010408 film Substances 0.000 description 40
- 239000003990 capacitor Substances 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로서, 질화막을 하드마스크로하여 비트라인들을 형성하고, 그 측벽에 스페이서를 형성한 후에 전하저장전극 콘택 플러그를 비트라인 사이에 형성하고, 전면에 산화막-질화막-전하저장전극 산화막-다결정실리콘층을 도포하고 전하저장전극 마스크로 상기 적층막들을 패턴닝하여 전하저장전극 콘택 플러그를 노출시키는 홈을 형성하고, 다시 다결정실리콘층을 도포하고 여분의 다결정실리콘층을 CMP 방법으로 식각하여 전하저장전극을 정의하였으므로, 전하저장전극 형성 공정이 간단하고 공정여유도가 증가되어 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein bit lines are formed using a nitride film as a hard mask, spacers are formed on the sidewalls, and a charge storage electrode contact plug is formed between the bit lines, and an oxide film-nitride film is formed on the entire surface. Applying a charge storage electrode oxide film-polycrystalline silicon layer and patterning the laminated films with a charge storage electrode mask to form a groove exposing the charge storage electrode contact plug, and then apply a polysilicon layer and replace the extra polysilicon layer Since the charge storage electrode is defined by etching by the CMP method, the charge storage electrode forming process is simple and the process margin is increased to improve the process yield and the reliability of device operation.
Description
도 1a 내지 도 1g는 본 발명에 따른 반도체소자의 제조공정도.1A to 1G are manufacturing process diagrams of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>
10 : 층간절연막 12 : 비트라인10: interlayer insulating film 12: bit line
13 : 마스크 절연막 패턴 14 : 스페이서 13 mask
15 : 전하저장전극 콘택 플러그 20 : 산화막15: charge storage electrode contact plug 20: oxide film
21 : 질화막 22 : 전하저장전극 산화막21
23,25 : 다결정실리콘층 24 : 감광막 패턴 23,25
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 비트라인 형성후에 콘택 플러그를 형성하고, 산화막-질화막-전하저장전극 산화막-다결정실리콘층의 적층 상태에서 전하저장전극 콘택을 형성하여 자기정렬 방법으로 용이하게 전하저장전극을 형성할 수 있어 공정이 간단하고 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a contact plug is formed after a bit line is formed, and a charge storage electrode contact is formed in a stacked state of an oxide film-nitride-charge storage electrode oxide film-polycrystalline silicon layer. The present invention relates to a method for manufacturing a semiconductor device, which can easily form a charge storage electrode, thereby simplifying a process and improving process yield and device operation reliability.
최근 반도체 소자의 고집적화 추세에 따라 셀 크기가 감소되어 충분한 정전 용량을 갖는 캐패시터를 형성하기가 어려워지고 있으며, 특히, 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자는 칩에서 많은 면적을 차지하는 캐패시터의 정전용량을 크게 하면서, 면적을 줄이는 것이 디램 소자의 고집적화에 중요한 요인이 된다.Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size. In particular, a DRAM device including one MOS transistor and a capacitor has a large area in the chip. Reducing the area while increasing the capacity is an important factor for high integration of the DRAM device.
이때 상기 캐패시터는 주로 다결정 실리콘을 도전체로 하여 산화막, 질화막 또는 그 적층막인 오.엔.오(oxide-nitride-oxide)막을 유전체로 사용하고 있다. At this time, the capacitor mainly uses an oxide film, a nitride film, or an O-oxide film (oxide-nitride-oxide) film as a dielectric, using polycrystalline silicon as a conductor.
따라서 캐패시터의 정전용량(C)은 C=(ε0×εr×A)/T (여기서 ε0 은 진공 유전율(permitivity of vacuum), εr 은 유전막의 유전상수(dielectric constant), A는 캐패시터의 표면적, T는 유전막의 두께)로 표시되는 캐패시터의 정전용량(C)을 증가시키기 위하여 유전상수가 높은 물질을 유전체로 사용하거나, 유전막을 얇게 형성하거나 또는 캐패시터의 표면적을 증가시키는 등의 방법이 있다.Therefore, the capacitance C of the capacitor is C = (ε 0 × ε r × A) / T, where ε 0 is the permittivity of vacuum, ε r is the dielectric constant of the dielectric film, and A is the capacitor. In order to increase the capacitance (C) of the capacitor represented by the surface area of the film, T is the thickness of the dielectric film, a material having a high dielectric constant is used as the dielectric, a thin dielectric film is formed, or the surface area of the capacitor is increased. have.
그러나 이러한 방법들은 모두 각각의 문제점을 가지고 있다.However, all these methods have their own problems.
즉, 높은 유전상수를 갖는 유전물질, 예를 들어 Ta2O5, TiO2 또는 SrTiO3등이 연구되고 있으나, 이러한 물질들의 접합 파괴전압등과 같은 신뢰도 및 박막특성등이 확실하게 확인되어 있지 않아 실제 소자에 적용하기가 어렵고, 식각이나 공정재현성등이 떨어지며, 제조단가가 높은 단점이 있고, 유전막 두께를 감소시키는 것은 소자 동작시 유전막이 파괴되어 캐패시터의 신뢰도에 심각한 영향을 준다.That is, dielectric materials having high dielectric constants , such as Ta 2 O 5 , TiO 2 or SrTiO 3 , have been studied, but reliability and thin film characteristics such as junction breakdown voltage of these materials have not been confirmed. It is difficult to apply to the actual device, the etching or process reproducibility, etc. are disadvantageous, the manufacturing cost is high, and reducing the thickness of the dielectric film has a serious impact on the reliability of the capacitor because the dielectric film is destroyed during operation of the device.
더욱이 캐패시터의 전하저장전극의 표면적을 증가시키기 위하여 다결정 실리콘층을 다층으로 형성한 후, 이들을 관통하여 서로 연결시키는 핀(Fin) 구조로 형 성하거나, 콘택의 상부에 실린더 형상의 전하저장전극을 형성하는 등의 방법을 사용하기도 한다. Furthermore, in order to increase the surface area of the capacitor's charge storage electrode, a polycrystalline silicon layer is formed in multiple layers and then formed into a fin structure through which they are connected to each other, or a cylindrical charge storage electrode is formed on the contact. Other methods may be used.
그러나 상기와 같은 종래 기술에 따른 반도체 소자의 캐패시터 제조방법에서 핀형이나 실린더형 캐패시터는 캐패시터간의 미세브릿지 불량으로 인하여 공정수율을 저하시키고, 복잡한 공정에 비하여 정전용량의 증가가 작으며, 실린더형 캐패시터의 는 주안정 다결정실리콘층(meta-stable poly silicon)을 성장시켜 면적을 증가시키고 있으나 미세 브릿지 현상이 더욱 증가되고 미세화가 어려운 문제점이 있다. However, in the capacitor manufacturing method of the semiconductor device according to the prior art as described above, the pin-type or cylindrical-type capacitors decrease the process yield due to the poor microbridges between the capacitors, and the increase in capacitance is small compared to the complicated process, and the capacitance of the cylindrical capacitors The main stable polysilicon layer (meta-stable poly silicon) is grown to increase the area, but there is a problem that the fine bridge phenomenon is further increased and difficult to refine.
또한 상기의 미세 브릿지를 해결하기 위하여 적층형 캐패시터가 다시 주목받고 있으나, 적층막들의 높이가 증가됨에 따라 두꺼운 막을 식각하는 공정이 용이하지 않고, 토폴로지에 의한 문제가 발생되는 등의 문제점이 있다. In addition, in order to solve the fine bridge, the stacked capacitor has been attracting attention again, but as the height of the laminated films is increased, the process of etching a thick film is not easy, and there are problems such as problems due to topology.
또한 셀 효율을 증가시키기 위하여 비트라인당 셀수를 기존에 비해 2배 이상으로 설계를 가져가고 있어 셀 캐패시터의 정전용량은 더욱 증가되어야 하는데, 캐패시터의 사용 가능한 표면적은 감소되고 있어, 현재 사용되는 핀형이나 실린더형 캐패시터에서는 캐패시터의 높이를 증가시키고, 전하저장전극 사이의 간격을 감소시키며, 반구형실리콘(hemi spherical silicon grain; 이하 HSG라 칭함)을 사용하는 등의 방법으로 유효표면적을 증가시키고 있다. Also, in order to increase cell efficiency, the number of cells per bitline has been designed more than twice as much as before, so the capacitance of the cell capacitor should be further increased, and the usable surface area of the capacitor is decreasing. In the cylindrical capacitor, the effective surface area is increased by increasing the height of the capacitor, decreasing the gap between the charge storage electrodes, and using a hemi-spherical silicon grain (hereinafter referred to as HSG).
상기와 같은 종래 기술에 따른 반도체 소자의 캐패시터는 전하저장전극 사이의 간격 감소로 인하여 이 부분에서의 디자인 룰이 여유가 없어져 인접한 전하저장전극 사이의 브릿지 불량 발생이 증가되고 있으며, 이러한 현상은 HSG를 사용하는 경우 더욱 증가되는 것으로 보고되고 있어 수율이 더욱 떨어진다. In the capacitor of the semiconductor device according to the prior art as described above, due to the reduction in the distance between the charge storage electrodes, the design rules in this part cannot be afforded, resulting in an increase in the failure of bridges between adjacent charge storage electrodes. It is reported to increase even more when used, the yield is even lower.
또한 종래 기술의 다른 실시 예로서, 전하저장전극 산화막을 전하저장전극 마스크로 패턴닝하여 콘택 플러그가 노출되는 홈을 형성하고, 전면에 다결정실리콘층을 도포하여 전하저장전극으로 사용하는 방법이 있다. In another embodiment of the prior art, there is a method of patterning a charge storage electrode oxide film with a charge storage electrode mask to form a groove exposing a contact plug, and using a polysilicon layer on the entire surface to use the charge storage electrode.
종래 기술에 따른 반도체소자의 제조방법을 살펴보면 다음과 같다. Looking at the method of manufacturing a semiconductor device according to the prior art as follows.
먼저, 반도체기판상에 소정의 하부 구조물, 예를들어 소자분리 산화막과 모스 전계효과 트랜지스터(Metal Oxide Semiconductor Field Effect Transistor; 이하 MOS FET라 칭함) 를 형성한 후, 상기 구조의 전표면에 제1층간절연막을 형성한다. First, a predetermined substructure, for example, an element isolation oxide film and a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOS FET) is formed on a semiconductor substrate, and then a first interlayer is formed on the entire surface of the structure. An insulating film is formed.
그다음 상기 반도체기판에서 비트라인 콘택과 전하저장전극 콘택으로 예정되어있는 부분상의 제1층간절연막을 제거하여 콘택홀들을 형성하고, 상기 콘택홀을 통하여 반도체기판과 접촉되는 콘택 플러그들을 형성한 후 비트라인을 형성한다. Then, contact holes are formed by removing the first interlayer insulating layer on the portion of the semiconductor substrate, which is intended as a bit line contact and a charge storage electrode contact, and forming contact plugs contacting the semiconductor substrate through the contact hole. To form.
그후 상기 구조의 전표면에 제2층간절연막과 전하저장전극 산화막을 형성하고, 전하저장전극 마스크를 사용하여 상기 산화막과 제2층간절연막을 식각하여 콘택 플러그를 노출시킨 후, 전하저장전극을 형성한다. Thereafter, a second interlayer insulating film and a charge storage electrode oxide film are formed on the entire surface of the structure, and the contact plug is exposed by etching the oxide film and the second interlayer insulating film using a charge storage electrode mask to form a charge storage electrode. .
상기와 같은 종래 기술에 따른 반도체소자의 제조방법은 공정이 복잡하고 자기정렬에 의한 공정이면서도 공정 난이도가 높아 공정수율 및 소자동작의 신뢰성이 떨어지는 문제점이 있다. The method of manufacturing a semiconductor device according to the prior art as described above has a problem in that the process is complicated and the process difficulty due to self-alignment is high, but the process yield and device operation reliability are low.
본 발명은 상기와 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 비트 라인 형성후 산화막-질화막-전하저장전극 산화막-다결정실리콘층을 적층하고 이를 전하저장전극 마스크로 패턴닝하여 홈을 형성한 후에 전하저장전극을 형성하여 공정이 용이하며 간단해져 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공함에 있다. SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object of the present invention is to form an oxide-nitride-charge storage electrode oxide film-polycrystalline silicon layer after forming a bit line and pattern it with a charge storage electrode mask to form a groove. The present invention provides a method of manufacturing a semiconductor device that can form a charge storage electrode, thereby making the process easy and simple, thereby improving process yield and reliability of device operation.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자 제조방법의 특징은, Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,
반도체기판 상에 형성된 층간절연막상에 마스크 절연막 패턴을 하드 마스크로 하여 비트라인을 형성하는 공정과, Forming a bit line on the interlayer insulating film formed on the semiconductor substrate using the mask insulating film pattern as a hard mask;
상기 비트라인과 마스크 절연막 패턴의 측벽에 절연 스페이서를 형성하는 공정과, Forming an insulating spacer on sidewalls of the bit line and the mask insulating film pattern;
상기 비트라인들의 사이에 전하저장전극 콘택 플러그를 형성하는 공정과, Forming a charge storage electrode contact plug between the bit lines;
상기 구조의 전표면에 산화막-질화막-전하저장전극 산화막-다결정실리콘층을 순차적으로 도포하는 공정과, Sequentially applying an oxide film-nitride film-charge storage electrode oxide film-polycrystalline silicon layer to the entire surface of the structure;
상기 다결정실리콘층상에 전하저장전극 마스크인 감광막 패턴을 형성하는 공정과, Forming a photoresist pattern as a charge storage electrode mask on the polysilicon layer;
상기 감광막 패턴에 의해 노출되어있는 다결정실리콘층에서 산화막까지 제거하여 상기 전하저장전극 콘택 플러그를 노출시킨 후, 상기 감광막 패턴을 제거하는 공정과, Removing the photoresist pattern after exposing the charge storage electrode contact plug by removing the oxide film from the polysilicon layer exposed by the photoresist pattern;
상기 구조의 전표면에 다결정실리콘층을 도포하는 공정과, Applying a polysilicon layer to the entire surface of the structure;
상기 전하저장전극 산화막 상부의 다결정실리콘층을 제거하여 다결정실리콘층 패턴으로된 전하저장전극을 형성하는 공정을 구비함에 있다. And removing the polysilicon layer on the charge storage electrode oxide layer to form a charge storage electrode having a polysilicon layer pattern.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체소자의 제조방법에 대하여 상세히 설명을 하기로 한다. Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1g는 본 발명에 따른 반도체소자의 제조 공정도이다. 1A to 1G are manufacturing process diagrams of a semiconductor device according to the present invention.
먼저, 도시되어있지는 않으나, 반도체기판 상에 소자분리산화막을 형성하여 활성영역을 정의하고, MOSFET를 형성한 후, 비트라인 콘택 플러그와 하부 전하저장전극 콘택 플러그를 구비하는 층간절연막(10)을 형성한다. Although not shown, first, an isolation region is formed on a semiconductor substrate to define an active region, a MOSFET is formed, and an
그다음 상기 층간절연막(10)상에 질화막 재질의 하드 마스크인 마스크 절연막 패턴(13)과 중첩되어있는 비트라인(12)을 W 등의 재질로 형성하고, 상기 패턴들의 측벽에 질화막 스페이서(14)를 형성한 후, 상기 비트라인(12)들의 사이에 상부전하저장전극 콘택 플러그(15)를 다결정실리콘재질로 구비하도록 형성한다. Next, a
상기 콘택 플러그(15) 형성 공정은 질화막 스페이서(14) 형성 후에 전면에 다결정실리콘층을 도포하고, 마스크 절연막 패턴(13)을 식각 정지층으로하여 화학-기계적 연마(CMP) 방법으로 다결정실리콘층의 상부를 제거하여 분리시키고, 사진식각 방법으로 전하저장전극과 접촉되는 부분만 남도록 한다. The
다른 방법으로는 질화막 스페이서(14) 형성 후에 전면에 산화막을 형성하고, 전하저장전극 콘택 플러그를 형성할 부분을 패턴닝하여 제거한 후에, 전면에 다결정실리콘층을 도포하고, CMP 방법으로 연마하여 비트라인을 경계로 고립시켜 산화막에 둘러싸인 전하저장전극 콘택 플러그를 형성할 수도 있다. (도 1a 참조). Alternatively, after forming the
그후, 상기 구조의 전표면에 산화막(20)과 질화막(21)을 순차적으로 형성한 후, (도 1b 참조), 다시 상대적으로 두꺼운 희생산화막인 전하저장전극 산화막(22)과 다결정실리콘층(23)을 순차적으로 형성하고, 상기 다결정실리콘층(23)상에 전하저장전극 마스크용 감광막 패턴(24)을 형성한다. 여기서 상기 전하저장전극 산화막(22)은 PSG 나 PE-TEOS막으로 형성한다. (도 1c 참조). Thereafter, after the
그다음 상기 감광막 패턴(24)에 의해 노출되어있는 다결정실리콘층(24)에서 질화막(21)까지 식각하여 산화막(20)을 노출시킨 후, 상기 감광막 패턴(24)의 남아 있는 부분을 제거한다. 그러나 상기 남아 있는 감광막 패턴(24)은 후에 산화막(20) 제거 후에 제거할 수도 있다. (도 1d 참조). Next, the
그후, 상기 다결정실리콘층(24)을 마스크로 노출된 산화막(20)을 제거하여 전하저장전극 콘택 플러그(15)를 노출시키고, (도 1e 참조), 상기 구조의 전표면에 다결정실리콘층(25)을 형성한다. (도 1f 참조). Thereafter, the
그다음 상기 전하저장전극 산화막(22) 상의 다결정실리콘층(25),(24)을 CMP 방법으로 제거하여 다결정실리콘층(25) 패턴으로된 전하저장전극을 형성한다. (도 1g 참조). Then, the polysilicon layers 25 and 24 on the charge storage
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은 질화막을 하드마스크로하여 비트라인들을 형성하고, 그 측벽에 스페이서를 형성한 후에 전하저장전극 콘택 플러그를 비트라인 사이에 형성하고, 전면에 산화막-질화막-전하저장전극 산화막-다결정실리콘층을 도포하고 전하저장전극 마스크로 상기 적층막 들을 패턴닝하여 전하저장전극 콘택 플러그를 노출시키는 홈을 형성하고, 다시 다결정실리콘층을 도포하고 여분의 다결정실리콘층을 CMP 방법으로 식각하여 전하저장전극을 정의하였으므로, 전하저장전극 형성 공정이 간단하고 공정여유도가 증가되어 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 이점이 있다. As described above, in the method of manufacturing a semiconductor device according to the present invention, bit lines are formed using a nitride film as a hard mask, spacers are formed on the sidewalls, and a charge storage electrode contact plug is formed between the bit lines, Apply oxide-nitride-charge storage electrode oxide-polycrystalline silicon layer and pattern the stacked layers with a charge storage electrode mask to form grooves exposing the charge storage electrode contact plugs, and then apply polycrystalline silicon layer and excess polycrystal Since the charge storage electrode is defined by etching the silicon layer by the CMP method, the process of forming the charge storage electrode is simple and the process margin is increased, thereby improving process yield and reliability of device operation.
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| KR940004825A (en) * | 1992-08-25 | 1994-03-16 | 문정환 | DRAM Cell Manufacturing Method |
| KR19980020386A (en) * | 1996-09-09 | 1998-06-25 | 김주용 | Capacitor Formation Method of Semiconductor Device |
| JPH1145983A (en) * | 1997-05-06 | 1999-02-16 | Natl Sci Council | Manufacture of dram capacitor by utilizing chemical mechanical polishing method |
| KR19990084959A (en) * | 1998-05-12 | 1999-12-06 | 윤종용 | How to form a conductive pad |
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| KR940004825A (en) * | 1992-08-25 | 1994-03-16 | 문정환 | DRAM Cell Manufacturing Method |
| KR19980020386A (en) * | 1996-09-09 | 1998-06-25 | 김주용 | Capacitor Formation Method of Semiconductor Device |
| JPH1145983A (en) * | 1997-05-06 | 1999-02-16 | Natl Sci Council | Manufacture of dram capacitor by utilizing chemical mechanical polishing method |
| KR19990084959A (en) * | 1998-05-12 | 1999-12-06 | 윤종용 | How to form a conductive pad |
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