KR20020043959A - A method for manufacturing a capacitor of a semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to improve yield and reliability, by preventing a defect of a charge storage electrode caused by a step between a cell region and a peripheral circuit region when a well capacitor is formed by using a core sacrificial layer. CONSTITUTION: A nitride layer(12) and a core oxide layer(14) are formed on a semiconductor substrate(10) having the cell region and the peripheral circuit region in which a predetermined lower structure is formed. The core oxide layer and the nitride layer on a portion for a charge storage electrode contact of the semiconductor substrate are eliminated to form a core oxide layer pattern having a charge storage electrode contact hole. A conductive layer(18) is formed on the entire surface of the resultant structure. The first photoresist layer(20) for planarization is applied on the conductive layer. The entire surface of the upper portion of the first photoresist layer is exposed and developed to make the first photoresist layer left only in a space between the core oxide layer patterns. The second photoresist layer(30) is formed on the resultant structure to planarize the upper portion. The conductive layers on the second photoresist layer and the core oxide layer pattern are sequentially etched to form a charge storage electrode composed of a conductive layer pattern applied inside the contact hole.

Description

A method for manufacturing a capacitor of a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. In particular, in the process of forming a well-type capacitor using a core sacrificial layer, a process yield and device operation are prevented by preventing formation of a charge storage electrode due to a difference between a cell region and a peripheral circuit region. The present invention relates to a method for manufacturing a capacitor of a semiconductor device capable of improving reliability.

Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size. In particular, DRAM devices composed of one MOS transistor and capacitors have a large area in the chip. Reducing the area while increasing the capacity is an important factor for high integration of the DRAM device.

At this time, the capacitor mainly uses an oxide film, a nitride film, or an O-oxide film (oxide-nitride-oxide) film as a dielectric, using polycrystalline silicon as a conductor.

Therefore, the capacitance C of the capacitor is C = (ε ₀ × ε _r × A) / T, where ε ₀ is the permittivity of vacuum, ε _r is the dielectric constant of the dielectric film, and A is the capacitor. In order to increase the capacitance (C) of the capacitor represented by the surface area of the film, T is the thickness of the dielectric film, a material having a high dielectric constant is used as the dielectric, a thin dielectric film is formed, or the surface area of the capacitor is increased. have.

However, all these methods have their own problems.

That is, dielectric materials having high dielectric constants _, such as Ta ₂ O ₅ , TiO ₂ or SrTiO ₃ , have been studied, but reliability and thin film characteristics such as junction breakdown voltage of these materials have not been confirmed. It is difficult to apply to the actual device, the etching or process reproducibility, etc. are disadvantageous, the manufacturing cost is high, reducing the thickness of the dielectric film is destroyed during operation of the device has a serious impact on the reliability of the capacitor.

Furthermore, in order to increase the surface area of the charge storage electrode of the capacitor, a polycrystalline silicon layer is formed in multiple layers, and then formed into a fin structure through which they are connected to each other, or a cylindrical charge storage electrode is formed on the contact. Other methods may be used.

However, in the method of manufacturing a capacitor of a semiconductor device according to the prior art as described above, the pin-type or cylindrical capacitor has a low process yield due to poor microbridges between capacitors, and an increase in capacitance is small compared to a complicated process. The main stable polysilicon layer (meta-stable poly silicon) is grown to increase the area, but there is a problem that the fine bridge phenomenon is further increased and difficult to refine.

In addition, in order to solve the fine bridge, the stacked capacitor has been attracting attention again, but as the height of the laminated films is increased, the process of etching a thick film is not easy, and there are problems such as problems due to topology.

Also, in order to increase cell efficiency, the number of cells per bitline has been designed more than twice as much as before, so the capacitance of the cell capacitor has to be increased further, and the usable surface area of the capacitor is decreasing. In cylindrical casings, the effective surface area is increased by increasing the height of the capacitors, decreasing the spacing between the charge storage electrodes, and using hemispherical silicon grains (hereinafter referred to as HSG).

In the capacitor of the semiconductor device according to the prior art as described above, due to the reduction in the distance between the charge storage electrodes, the design rule in this part cannot be afforded, resulting in an increase in the failure of bridges between adjacent charge storage electrodes. It is reported to increase even more when used, the yield is even lower.

1A to 1E are diagrams illustrating a capacitor manufacturing process of a semiconductor device according to the related art.

First, a predetermined lower structure, for example, an element isolation oxide film and a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOS FET), is formed on the semiconductor substrate 10, and then the entire surface of the structure. The photoresist pattern 16, which is a charge storage electrode mask for forming a nitride film 12 and a core oxide film 14 on the semiconductor substrate 10 and exposing a portion of the semiconductor substrate 10 that is intended as a charge storage electrode contact, is formed on the core oxide film ( 14) form on. (See FIG. 1A).

Then, the nitride film 12 and the core oxide film 14 having contact holes exposing the semiconductor substrate 10 by sequentially removing the core oxide film 14 and the nitride film 12 exposed by the photosensitive film pattern 16. After the pattern is formed, the photoresist pattern 16 is removed, a conductive layer 18 serving as a charge storage electrode is applied to the entire surface of the structure, and the planarization photoresist 20 is applied to planarize. (See FIG. 1B).

Thereafter, the photoresist film 20 is removed with an etch back, and at the same time, the conductive layer 18 on the core oxide film 14 pattern is removed to separate each charge storage electrode, and then the remaining portions of the photoresist film 20 are removed. do. (See FIG. 1C).

Then, the remaining core oxide film 14 pattern is removed, thereby forming a charge storage electrode having a conductive layer 18 pattern connected to the semiconductor substrate 10 (see FIG. 1D), and on the entire surface of the structure. The dielectric film 22 and the plate electrode 24 are formed to form a capacitor. (See FIG. 1E).

In the conventional capacitor manufacturing method as described above, after the core oxide film is formed, the conductive layer is applied, the photoresist film is flattened, and then etched back. The planarization of the photoresist film pattern becomes an important factor in the process yield.

That is, as shown in FIG. 2A, the top surface of the planarized photoresist film 20 is not formed flat between the cell region I and the peripheral circuit region II due to the pattern density difference. This is because the capacitor is not formed in the peripheral circuit area so that the core oxide film 14 is not patterned. Therefore, the photoresist film 20 flows into the concave portion of the pattern of the core oxide film 14 in the cell region. In the circuit region (II), the photosensitive film 20 is thickly applied.

After that, as shown in FIG. 2B, when the photoresist film is etched back, the photoresist film remains on the core oxide film 14 in the peripheral circuit region (II), so that the conductive layer 18 is not removed from the region, and the capacitor operates properly. There is a problem.

Figure 3 is a cross-sectional picture of the state of Figure 2b, showing a good state of failure.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and an object of the present invention is to provide a method for patterning charge storage electrode patterning by a difference in pattern density between a cell region and a peripheral circuit region in a charge storage electrode manufacturing process using a core oxide film pattern. The present invention provides a method of manufacturing a capacitor of a semiconductor device that can prevent defects and improve process yield and device operation reliability.

1A to 1E are views illustrating a capacitor manufacturing process of a semiconductor device according to the prior art.

2a and 2b is a process chart for explaining the problems of the prior art.

3 is a cross-sectional photograph of the state of FIG.

Figures 4a to 4d is a manufacturing process of the capacitor of the semiconductor device according to the present invention.

<Description of Symbols for Main Parts of Drawings>

10 semiconductor substrate 12 nitride film

14 core oxide film 16 photosensitive film pattern

18: conductive layer 20, 30: planarized photosensitive film

22 dielectric film 24 plate electrode

Ⅰ: Cell area Ⅱ: Peripheral circuit area

Features of the capacitor manufacturing method of a semiconductor device according to the present invention for achieving the above object,

Forming a nitride film and a core oxide film on the entire surface of the semiconductor substrate having a cell region and a peripheral circuit region in which a predetermined substructure is formed;

Removing a core oxide film and a nitride film on a portion of the semiconductor substrate, the core oxide film pattern having a charge storage electrode contact hole, by removing the core oxide film and the nitride film on the predetermined portion;

Forming a conductive layer on the entire surface of the structure;

Applying a planarizing first photosensitive film on the conductive layer;

Exposing the entire upper surface of the first photoresist layer and developing the same so that the first photoresist layer remains in the space between the core oxide layer patterns;

Forming a second photosensitive film on the entire surface of the structure to planarize the upper portion;

And forming a charge storage electrode having a conductive layer pattern applied to the inside of the contact hole by sequentially etching the conductive layer over the second photoresist layer and the core oxide layer pattern.

In addition, another feature of the present invention is that the conductive layer is a polysilicon layer, and an interlayer insulating film is formed on a semiconductor substrate having a lower structure in a step before the nitride film forming process, and a contact open and a plug are formed.

Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

4A to 4D are diagrams illustrating a capacitor manufacturing process of a semiconductor device according to the present invention.

First, as shown in FIG. 2B, a substructure such as an isolation layer, a MOS FET, and a bit line is formed on a semiconductor substrate 10 such as a silicon wafer having a cell region I and a peripheral circuit region B. In the photolithography process, a nitride film 12 as an etch barrier and a core oxide film 14 made of an oxide film are sequentially formed on the entire surface of the structure, and a photoresist pattern using a photoresist pattern as a charge storage electrode mask is formed on the core oxide film 14. A pattern of the nitride film 12 and the core oxide film 14 having contact holes exposing the semiconductor substrate 10 is formed.

Thereafter, the conductive layer 18 serving as the charge storage electrode is applied to the entire surface of the structure with polysilicon or the like, and the planarized photoresist film 20 is applied to planarize. At this time, the photosensitive film 20 is positive, and the photoresist film is formed on the pattern of the core oxide film 14 in the peripheral circuit region (II) due to the difference in the core oxide film 14 pattern between the cell region (I) and the peripheral circuit region (B). (20) is formed thicker than the cell region (I). (See FIG. 4A).

Then, the entire photoresist film 20 is exposed to light and then developed with an alkaline developer so that the photoresist film 20 remains only in the space between the core oxide film 14 patterns. When the exposure energy is properly adjusted during the exposure process, all of the photoresist film 20 in the peripheral circuit region II can be removed. (See FIG. 4B).

Then, by applying the planarized photosensitive film 30 to the entire surface of the structure, it is possible to obtain a planarized top surface with no difference in thickness over the cell region I and the peripheral circuit region II. (See FIG. 4C).

Then, the planarized photoresist layer 30 is etched by an etch back process and the conductive layer 18 on the core oxide layer 14 pattern is also etched and removed to obtain a conductive layer 18 pattern that becomes an independent charge storage electrode. . At this time, the conductive layer 18 is not left in the peripheral circuit region (II). (See FIG. 4D).

Thereafter, although not shown, the remaining photoresist layers 30 and 20 and the core oxide layer 14 pattern are removed, and a dielectric film and a plate electrode are formed to complete the capacitor.

In the above example, the charge storage electrode contact plug is not formed. However, an interlayer insulating film may be formed on a semiconductor substrate having a lower structure, and the process of the present invention may be performed after the contact is opened and the plug is formed.

As described above, in the method of fabricating a capacitor of a semiconductor device according to the present invention, a core between a cell region and a peripheral circuit region is defined in a process of defining a charge storage electrode by etching a conductive layer using a core oxide film pattern by a front etch back method. Due to the difference in oxide pattern, the planarized photoresist film is formed thick in the peripheral circuit area.The first photoresist film is removed by front exposure and development so that it remains only in the space between the patterns, and is flattened by the secondary photoresist film. Since it is separated by the charge storage electrode, there is an advantage of improving the process yield and the reliability of the device operation by preventing the pattern defect due to the difference in the thickness of the photosensitive film in addition to one photosensitive film coating process.

Claims (3)

Forming a nitride film and a core oxide film on the entire surface of the semiconductor substrate having a cell region and a peripheral circuit region in which a predetermined substructure is formed; Removing a core oxide film and a nitride film on a portion of the semiconductor substrate, the core oxide film pattern having a charge storage electrode contact hole, by removing the core oxide film and the nitride film on the predetermined portion; Forming a conductive layer on the entire surface of the structure; Applying a planarizing first photosensitive film on the conductive layer; Exposing the entire upper surface of the first photoresist layer and developing the same so that the first photoresist layer remains in the space between the core oxide layer patterns; Forming a second photosensitive film on the entire surface of the structure to planarize the upper portion; And forming a charge storage electrode having a conductive layer pattern applied to the inside of the contact hole by sequentially etching the conductive layer over the second photoresist layer and the core oxide layer pattern. The method of claim 1, The conductive layer is a polysilicon layer, characterized in that the capacitor manufacturing method of the semiconductor device. The method of claim 1, And forming an interlayer insulating film on the semiconductor substrate having a lower structure, contact opening, and plug forming in a step before forming the nitride film.