JP2014053361A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem in which if a silicon nitride film having a relatively high dielectric constant is used on the top and side wall of a bit line, the parasitic capacitance of adjacent wirings increases and thereby disadvantages are sometimes brought to a circuit operation.SOLUTION: A method of manufacturing a semiconductor device includes the steps of: forming a plurality of conductive wirings having a side surface and top surface covered with an insulating film on a semiconductor substrate, so as to extend in a first direction; covering with a polymer film a space between the plurality of conductive wirings on the semiconductor substrate; patterning the polymer film in a second direction intersecting with the first direction, to leave the film on the semiconductor substrate; forming an interlayer insulating film on the semiconductor substrate that includes the polymer film and the plurality of conductive wirings; removing the interlayer insulating film until the top surface of the polymer film appears; removing the polymer film whose top surface has appeared; and embedding a conductive layer in portions where the polymer film is removed.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  2. Description of the Related Art Conventionally, in a semiconductor device having elements such as DRAM (Dynamic Random Access Memory), in a bit line, a mask nitride and a silicon nitride film serving as a third wall are formed on the upper and side walls of the conductive film, and an interlayer is formed on the silicon nitride film. A silicon oxide film to be an insulating film has been formed. Using the fact that the etching rate of the silicon nitride film on the upper and side walls of the bit line is slower than the etching rate of the silicon oxide film that becomes the interlayer insulating film, a capacitor contact is formed on the silicon oxide film that becomes the interlayer insulating film by self-alignment It was.

  For example, in Patent Document 1, a bit line having a mask film made of a silicon nitride film is patterned on a conductive film (a bottom conductive film and a metal film laminated from below), and then the silicon is formed so as to cover the bit line. A nitride film is formed, and then the silicon nitride film is etched to form a sidewall made of a silicon nitride film on the sidewall of the conductive film. A liner film made of a silicon nitride film is formed on the entire surface including the bit line, and then a deposited film made of SOD (spin on dielectric) is deposited and modified between the bit lines on the liner film, and then the bit line Then, an interlayer insulating film made of a silicon oxide film is formed on the entire surface including the deposited film, and then an opening communicating with the semiconductor substrate is formed by self-alignment, and then a sidewall made of a silicon nitride film is formed on the inner wall of the opening. Then, it is disclosed that a polysilicon film is embedded in the bottom of the opening.

JP 2012-84738 A

  The following analysis is given by the inventor.

  However, when a silicon nitride film having a relatively high dielectric constant is used for the upper portion and side wall of the bit line, the parasitic capacitance of the adjacent wiring increases, which may be disadvantageous in circuit operation.

  According to a first aspect, in a method for manufacturing a semiconductor device, a step of forming a plurality of conductive wirings whose side surfaces and upper surface are covered with an insulating film on a semiconductor substrate so as to extend in a first direction; Covering the plurality of conductive wirings on the substrate with a polymer film, patterning the polymer film in a second direction intersecting the first direction, and leaving on the semiconductor substrate, the polymer film and Forming an interlayer insulating film on the semiconductor substrate including the plurality of conductive wirings; removing the interlayer insulating film until an upper surface of the polymer film appears; and removing the polymer film exposed on the upper surface And a step of embedding a conductive layer in the portion from which the polymer film has been removed.

  In a second aspect, in a method for manufacturing a semiconductor device, a step of forming a first interlayer insulating film having an opening on a semiconductor substrate, and a side surface and an upper surface are insulated from each other in the opening on the semiconductor substrate Forming a plurality of conductive wires covered with a film so as to extend in a first direction, a step of covering the plurality of conductive wires on the first interlayer insulating film with a polymer film, and Patterning in a second direction intersecting the first direction and leaving on the semiconductor substrate; and forming a second interlayer insulating film on the semiconductor substrate including the polymer film and the plurality of conductive wirings And removing the second interlayer insulating film until the upper surface of the polymer film appears, removing the polymer film showing the upper surface until the upper surface of the first interlayer insulating film appears, and an upper surface appeared. The first delamination Removing the membrane to appear the upper surface of the semiconductor substrate, characterized in that it comprises a burying a conductive layer on the polymer film and the first interlayer insulating film is removed partially.

  In a third aspect, in a method for manufacturing a semiconductor device, a step of depositing a conductive film and a first silicon oxide film in this order on a semiconductor substrate, and the conductive film and the first silicon oxide film are formed in a first Forming a plurality of bit lines by patterning to extend in a direction; depositing a second silicon oxide film on the semiconductor substrate including the plurality of bit lines; and etching back the plurality of bits. Forming a sidewall leaving the second silicon oxide film on the side wall of the line, applying a polymer film between the plurality of bit lines on the semiconductor substrate, and attaching the polymer film to the first Patterning in a second direction intersecting the direction and leaving on the semiconductor substrate, exposing the semiconductor substrate, the remaining polymer film and the plurality of bits Forming a third silicon oxide film on the semiconductor substrate including wiring; removing the third silicon oxide film until an upper surface of the polymer film appears; and removing the polymer film to form the semiconductor substrate. The method includes a step of forming a communication opening and a step of embedding a conductive layer in the opening on the semiconductor substrate.

  In a fourth aspect, in a method for manufacturing a semiconductor device, a step of forming an interlayer silicon oxide film having an opening on a semiconductor substrate, and a conductive film and a first silicon oxide in the opening on the semiconductor substrate Depositing a film in this order, forming a plurality of bit lines by patterning the conductive film and the first silicon oxide film to extend in a first direction, and the plurality of bit lines A step of depositing a second silicon oxide film on the semiconductor substrate including the step of forming a sidewall by etching back leaving the second silicon oxide film on sidewalls of the plurality of bit lines, and the interlayer silicon oxide Applying a polymer film between the plurality of bit lines on the film; and patterning the polymer film in a second direction intersecting the first direction to form the interlayer film. Leaving the interlayer oxide film on the con oxide film and exposing the interlayer silicon oxide film; and forming a third silicon oxide film on the interlayer silicon oxide film including the remaining polymer film and the plurality of bit line wirings; Removing the third silicon oxide film until the upper surface of the polymer film appears, and removing the polymer film and the interlayer silicon oxide film exposed from the upper surface to form another opening that communicates with the semiconductor substrate. And a step of embedding a conductive layer in the other opening on the semiconductor substrate.

  According to the present invention, by using an insulating film having a dielectric constant smaller than that of the silicon nitride film as the insulating film formed on the upper surface and side wall of the bit line, the parasitic capacitance can be made smaller than that of the prior art.

FIG. 3A is a cross-sectional view taken along a line AA ′ in FIG. 2, and FIG. 3B is a cross-sectional view taken along a line BB ′ schematically illustrating a configuration of a memory cell unit of the semiconductor device according to the first embodiment. FIG. 3 is a partial plan view corresponding to FIG. 1 schematically showing a configuration of a memory cell portion of the semiconductor device according to the first embodiment. FIG. 5A is a cross-sectional view taken along a line AA ′ in FIG. 4 and FIG. 5B is a cross-sectional view taken along a line BB ′ schematically illustrating a method for manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a partial plan view corresponding to FIG. 3 schematically showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4A is a cross-sectional view taken along a line AA ′ and FIG. 4B is a cross-sectional view taken along a line BB ′ following FIG. 3 schematically illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view taken along a line A-A ′ and a cross-sectional view taken along a line B-B ′ following FIG. 5 schematically illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 7A is a cross-sectional view taken along a line AA ′ and FIG. 7B is a cross-sectional view taken along a line BB ′ following FIG. 6 schematically showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8A is a cross-sectional view taken along a line AA ′ and FIG. 8B is a cross-sectional view taken along a line BB ′ following FIG. 7 schematically showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 9 is a partial plan view corresponding to FIG. 8 schematically showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 9A is a cross-sectional view taken along the line AA ′ and FIG. 9B is a cross-sectional view taken along the line BB ′ following FIG. 8 schematically illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 11 is a cross-sectional view taken along a line AA ′ and a cross-sectional view taken along a line BB ′ following FIG. 10 schematically illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIGS. 11A and 11B schematically illustrate the method for manufacturing the semiconductor device according to the first embodiment, and are cross-sectional views between (a) AA ′ and (b) BB ′. FIG. 13 is a partial plan view corresponding to FIG. 12 schematically showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 13A is a cross-sectional view taken along a line AA ′ and FIG. 13B is a cross-sectional view taken along a line BB ′ following FIG. 12 schematically showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 15A is a cross-sectional view taken along a line AA ′ and FIG. 15B is a cross-sectional view taken along a line BB ′ following FIG. 14 schematically showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 16A is a cross-sectional view taken along a line AA ′ and FIG. 15B is a cross-sectional view taken along a line BB ′ following FIG. 15 schematically illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 17 is a partial plan view corresponding to FIG. 16 schematically showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 18A is a cross-sectional view taken along a line AA ′ and FIG. 18B is a cross-sectional view taken along a line BB ′ following FIG. 17 schematically illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 19A is a cross-sectional view taken along the line AA ′ and FIG. 18B is a cross-sectional view taken along the line BB ′ following FIG. 18 schematically illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 20 is a partial plan view corresponding to FIG. 19 schematically showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 20A is a cross-sectional view taken along line AA ′ and FIG. 19B is a cross-sectional view taken along line BB ′ following FIG. 19 schematically illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 22 is a partial plan view corresponding to FIG. 21 schematically showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 23A is a cross-sectional view taken along line AA ′ and FIG. 22B is a cross-sectional view taken along line BB ′ following FIG. 22 schematically illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 24A is a cross-sectional view taken along the line A-A ′ and FIG. 24B is a cross-sectional view taken along the line BB ′ following FIG. 23 schematically showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 25 is a cross-sectional view taken along a line AA ′ and a cross-sectional view taken along a line BB ′ following FIG. 24 schematically showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 26 is a cross-sectional view taken along a line A-A ′ and a cross-sectional view taken along a line B-B ′ following FIG. 25 schematically illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 27 is a partial plan view corresponding to FIG. 26 schematically showing the method for manufacturing the semiconductor device according to the first embodiment. 27A is a cross-sectional view taken along line AA ′ and FIG. 27B is a cross-sectional view taken along line BB ′ following FIG. 26 schematically illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 29 is a cross-sectional view taken along a line A-A ′ and a cross-sectional view taken along a line B-B ′ following FIG. 28 schematically showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 30A is a cross-sectional view taken along line AA ′ and FIG. 29B is a cross-sectional view taken along line BB ′ following FIG. 29 schematically illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 31 is a cross-sectional view taken along a line AA ′ and a cross-sectional view taken along a line BB ′ following FIG. 30 schematically showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 32A is a cross-sectional view taken along line AA ′ and FIG. 32B is a cross-sectional view taken along line BB ′ following FIG. 31 schematically illustrating the method for manufacturing the semiconductor device according to the first embodiment;

[Embodiment 1]
A semiconductor device according to Embodiment 1 will be described with reference to the drawings. Here, a case where the semiconductor device is a DRAM (Dynamic Random Access Memory) will be described as an example.

  FIG. 1 is a cross-sectional view taken along a line A-A ′ in FIG. 2 and a cross-sectional view taken along a line BB ′ in FIG. 2 schematically showing the configuration of a memory cell portion of the semiconductor device according to the first embodiment. is there. FIG. 2 is a partial plan view corresponding to FIG. 1 schematically showing the configuration of the memory cell portion of the semiconductor device according to the first embodiment. In FIG. 2, the capacitor (48 in FIG. 1) located on the capacitor contact pad 42 and the upper metal wiring (51 in FIG. 1) located on the capacitor are omitted in order to clarify the arrangement of the components. ing. 1A has a cross section parallel to the Y direction, FIG. 1B is described as the X direction in this description although it is strictly deviated from the X direction. In the DRAM 100 of this embodiment, the silicon substrate 1 is used as a base semiconductor substrate. Furthermore, not only a single semiconductor substrate but also a state in which a semiconductor device is manufactured on the semiconductor substrate and a state in which the semiconductor device is formed on the semiconductor substrate are collectively referred to as a wafer.

  Since the DRAM 100 is provided with a planar type MOS (Metal Oxide Semiconductor) transistor (hereinafter referred to as a MOS transistor) on the silicon substrate 1, the configuration of the MOS transistor will be described first.

  The MOS transistor is provided in an active region 1A surrounded by STI (Shallow Trench Isolation) 9 which is an element isolation region of the silicon substrate 1. The STI 9 is obtained by laminating an insulating film 6 and an insulating film 7 in a groove formed in the silicon substrate 1. The MOS transistor includes a gate insulating film 16 covering an inner wall of a groove provided in the active region 1A, an intervening layer 17 covering an upper surface portion and a part of side surfaces of the gate insulating film 16, and an intervening layer 17 The conductive film 18 and the conductive film 18A that become the buried word line 23 and the buried wiring 22 provided inside, the impurity diffusion layer 26 that becomes the source region and the drain region provided in the low-concentration impurity diffusion layer 11, and the impurity diffusion The layer 37 is included. The low-concentration impurity diffusion layer 11 is provided above the active region 1A excluding the region where the gate insulating film 16 is provided, and has an impurity of a conductivity type opposite to the conductive impurity contained in the silicon substrate 1 in a large amount. It is a layer formed by diffusion. The upper surfaces of the conductive films 18 and 18A are covered with the liner film 20 and the buried insulating film 21. The active region 1A shown in FIG. 1B represents two MOS transistors having embedded word lines 23 for convenience of explanation, but in the cell array portion in an actual DRAM, several thousand to several hundred thousand are shown. A number of MOS transistors are arranged. The embedded wiring 22 shown in FIG. 1B has the same structure as the embedded word line 23, but does not function as a word line but has a function of electrically separating MOS transistors. In the embedded wiring 22, the parasitic transistor is turned off by maintaining the voltage at a predetermined value, so that adjacent MOS transistors on the same active region 1 </ b> A can be electrically isolated.

  Next, the configuration above the MOS transistor will be described.

  A plurality of memory cells having the MOS transistor and the capacitor 48 are provided in the cell array portion of the DRAM 100. The capacitor 48 is a cylinder type capacitor, and includes a lower electrode 45, a capacitive insulating film 46, and an upper electrode 47. The lower electrode 45 has a cylindrical shape in which the bottom surface of the cylindrical portion is closed, and has an inner wall and an outer wall. The upper electrode 47 is embedded on the inner wall side through a capacitive insulating film 46. The impurity diffusion layer 26 is connected to a conductive film 27 provided on the impurity diffusion layer 26. Here, the conductive film 27 and the conductive film 28 provided on the conductive film 27 constitute a bit line 30. The upper surface of the bit line 30 is covered with a mask film 29, and the side surfaces of the bit line 30 and the mask film 29 are covered with a sidewall insulating film 31. The mask film 29 and the sidewall insulating film 31 are silicon oxide films. The impurity diffusion layer 37 of the MOS transistor is electrically connected to the lower electrode 45 through a capacitor contact plug 41 and a capacitor contact pad 42 provided on the impurity diffusion layer 37. Here, the capacitor contact plug 41 has a laminated structure in which an intervening layer 39 is inserted between the conductive film 38 and the conductive film 40, and the side surface portion is covered with the sidewall insulating film 36. Further, since the capacitor contact pad 42 is provided in order to secure an alignment margin between the capacitor 48 and the capacitor contact plug 41, it is not necessary to cover the entire upper surface of the capacitor contact plug 41. It suffices if it is located above and connected to at least a part thereof.

  The bit line 30, the mask film 29, and the capacitor contact plug 41 are embedded with the first interlayer insulating film 24 and the second interlayer insulating film 32. Further, the capacitor contact pad 42 is covered with a stopper film 43 for protecting the second interlayer insulating film 32. A third interlayer insulating film 44 is provided on the stopper film 43. In the third interlayer insulating film 44 and the stopper film 43, a cylinder hole 44A communicating with the capacitor contact pad 42 is formed. Since the cylinder hole 44 </ b> A is covered with the lower electrode 45, the outer wall of the lower electrode 45 is in contact with the third interlayer insulating film 44 and the stopper film 43. The upper surface of the third interlayer insulating film 44 is covered with a capacitive insulating film 46. The exposed surface (upper surface or side wall surface) of the capacitor insulating film 46 is covered with the upper electrode 47. The capacitor insulating film 46 and the upper electrode 47 are common to the predetermined capacitors 48 adjacent to each other.

  The upper electrode 47 is covered with a fourth interlayer insulating film 49. The fourth interlayer insulating film 49 is provided with a contact plug 50 that communicates with the upper electrode 47. Furthermore, an upper metal wiring 51 is provided on the fourth interlayer insulating film 49. The upper electrode 47 of the capacitor 48 is connected to the upper metal wiring 51 through the contact plug 50. The fourth interlayer insulating film 49 including the upper metal film 51 is covered with a protective film 52.

  As described above, the MOS transistor in this embodiment has the embedded word line 23, and has a configuration that is more effective in reducing the occupied area in the cell array portion than the planar MOS transistor.

  Next, a method for manufacturing the semiconductor device (DRAM 100) according to the first embodiment will be described with reference to the drawings. 3 to 32 are cross-sectional views or partial plan views schematically showing the method for manufacturing the semiconductor device according to the first embodiment. 3, 5 to 8, 10 to 12, 14 to 16, 18 to 19, 21, 23 to 26, and 28 to 32, (a) is a diagram. 1 is a cross-section corresponding to the section between A-A ', and (b) shows a section corresponding to the section between BB' in FIG. As in FIG. 1, (a) is a cross section parallel to the Y direction, and (b) is also described as a cross section parallel to the X direction. 4, 9, 13, 17, 20, 22, and 27 are partial plan views of the region corresponding to FIG. 2, and FIG. 3 and FIG. 8, FIG. 12, FIG. 16, FIG. 19, FIG. 21, FIG.

On a P-type silicon substrate 1, a sacrificial film 2 which is a silicon oxide film (SiO ₂ ) by a thermal oxidation method and a mask film 3 which is a silicon nitride film (Si ₃ N ₄ ) by a thermal CVD (Chemical Vapor Deposition) method Are sequentially deposited, and then the mask film 3, the sacrificial film 2 and the silicon substrate 1 are patterned by using a photolithography method and a dry etching method, whereby an element isolation trench 4 (trench) for partitioning the active region 1A is formed. ) Is formed on the silicon substrate 1 (step A1; see FIGS. 3 and 4).

  Here, the element isolation trench 4 is formed as a line pattern extending in the X direction. The region that becomes the active region 1 </ b> A is covered with the mask film 3.

  Next, an insulating film 6 that is a silicon oxide film is formed on the surfaces of the silicon substrate 1 and the mask film 3 by a thermal oxidation method, and then the insulating film 7 that is a silicon nitride film is formed into an element isolation trench by a thermal CVD method. Then, the insulating film 7 is left only in the element isolation trench 4 by performing an etch-back process (step A2; see FIG. 5).

  Next, a buried film 8 which is a silicon oxide film is deposited by plasma CVD so as to fill the inside of the element isolation trench 4, and then the mask film 3 formed in step A1 (see FIG. 3) is exposed. CMP (Chemical Mechanical Polishing) is performed until the surface of the buried film 8 is flattened (step A3; see FIG. 6).

  Next, the mask film (3 in FIG. 6) and the sacrificial film (2 in FIG. 6) are removed by wet etching, and the buried film 8 on the surface of the element isolation trench 4 is roughly positioned and positioned on the surface of the silicon substrate 1. The surface of the silicon substrate 1 is exposed so as to be equivalent, and then a sacrificial film 10 which is a silicon oxide film is formed on the upper surfaces of the silicon substrate 1 and the buried film 8 by thermal oxidation, and then a low concentration N N-type low-concentration impurity diffusion layers 11 are formed by implanting type impurities (phosphorus or the like) into the silicon substrate 1 by ion implantation (step A4; see FIG. 7).

  Here, by removing the mask film (3 in FIG. 6) and the sacrificial film (2 in FIG. 6), a linear element isolation region using the STI 9 is formed. Further, the low concentration impurity diffusion layer 11 functions as a source / drain (S / D) region of the MOS transistor.

  Next, a lower mask film 12 that is a silicon nitride film is formed on the sacrificial film 10 by plasma CVD, and then a carbon film (amorphous carbon film) is formed on the lower mask film 12 by plasma CVD. The upper layer mask film 13 is deposited, and then the upper layer mask film 13, the lower layer mask film 12, and a part of the sacrificial film 10 are formed by photolithography and dry etching so as to form a gate electrode trench (trench) pattern. Remove (step A5; see FIGS. 8 and 9).

  Next, the silicon substrate 1 is etched by dry etching using the upper mask film (13 in FIG. 8) and the lower mask film 12 as a mask to form a gate electrode trench (trench) 15 (step A6; see FIG. 10). ).

  Here, the gate electrode trench 15 is formed as a line-shaped pattern extending in the Y direction intersecting the active region 1A. On the side surface portion of the gate electrode trench 15 in contact with the STI 9, the thin-film silicon substrate 1 remains in a sidewall shape and functions as the channel region 14 of the MOS transistor. Further, the upper layer mask film (13 in FIG. 8) disappears on the silicon substrate 1 excluding the inside of the gate electrode trench 15, and at least a part of the lower layer mask film 12 remains.

  Next, a gate insulating film 16 is formed at least on the inner wall of the trench 15 for the gate electrode (the entire substrate surface in FIG. 11), and then the intervening layer 17 made of titanium nitride (TiN) and tungsten (W) are formed by CVD. A conductive film 18 is sequentially deposited (step A7; see FIG. 11).

  Here, as the gate insulating film 16, a silicon oxide film formed by a thermal oxidation method or the like can be used.

  Next, the upper part of the conductive film 18 that is no longer necessary is removed by dry etching so that the conductive film 18 remains at a thickness of about 100 nm at the bottom of the gate electrode trench 15, and then interposed by dry etching. The unnecessary intervening layer 17 is removed so that the layer 17 remains at the same height as the upper surface of the conductive film 18 at the bottom of the gate electrode trench 15 (step A8; see FIGS. 12 and 13).

  Here, in the dry etching for removing the upper portion of the conductive film 18, the intervening layer 17 is not removed but remains on the inner wall of the gate electrode trench 15 and the upper portion of the lower mask film 12. Also, by dry etching to remove the intervening layer 17, the buried word line 23 and the buried wiring 22 composed of the intervening layer 17 and the conductive film 18 having the same upper surface height are formed at the bottom of the gate electrode trench 15. Can be formed.

  Next, a liner film 20 that is a silicon nitride film is formed by thermal CVD so as to cover the upper surface of the remaining conductive film 18 and the inner wall of the gate electrode trench 15, and then the liner film 20 is covered. A buried insulating film 21 is deposited (step A9; see FIG. 14).

Here, as the buried insulating film 21, a silicon oxide film formed by a plasma CVD method, an SOD film (Spin On Dielectrics: coating insulating film) that is a coating film, or a laminated film thereof can be used. When the SOD film is used, annealing is performed in a high-temperature water vapor (H ₂ O) atmosphere to modify the film into a solid film.

  Next, the embedded insulating film 21 is removed by CMP until the upper surface of the liner film 20 is exposed, and then the surface of the embedded insulating film 21 is approximately the same as the surface of the silicon substrate 1 by etch back. The sacrificial film (10 in FIG. 14), the lower layer mask film (12 in FIG. 14), the gate insulating film 16, the buried insulating film 21, and a part of the liner film 20 are removed (step A10). ; See FIG. As a result, the upper surfaces of the buried word line 23 and the buried wiring 22 are insulated.

  Next, a first interlayer insulating film 24, which is a silicon oxide film formed by plasma CVD, is formed so as to cover the upper surface of the silicon substrate 1, and then the first interlayer insulating film is formed using photolithography and dry etching. A bit contact opening 25 is formed by removing a part of 24, and then an N-type impurity diffusion layer 26 is formed by ion implantation of an N-type impurity (such as arsenic) near the surface of the silicon substrate 1. (Step A11; see FIGS. 16 and 17).

  Here, the bit contact opening 25 is formed as a line-shaped opening pattern extending in the Y direction in the same manner as the embedded word line 23 and the embedded wiring 22. At the intersection of the bit contact opening 25 and the active region 1A, the surface of the silicon substrate 1 is exposed, and an N-type impurity diffusion layer 26 is formed at that portion. The formed N-type impurity diffusion layer 26 functions as one of the source / drain regions of the transistor, and the upper surface thereof is exposed at the bottom surface of the bit contact opening 25.

  Next, a conductive film 27 which is a polysilicon film containing an N-type impurity (phosphorus or the like) by thermal CVD so as to cover the impurity diffusion layer 26 and the first interlayer insulating film 24, and tungsten by sputtering. A conductive film 28 and a mask film 29 which is a silicon oxide film formed by plasma CVD are sequentially deposited (step A12; see FIG. 18).

  Next, the laminated conductive film 27 and conductive film 28 and mask film 29 are patterned in a line shape so that the width Y1 is about 18 nm, and a bit line 30 composed of the conductive film 27 and the conductive film 28 is formed. Thereafter, a silicon oxide film is formed by an ALD (Atomic Layer Deposition) method with a thickness Y3 of 16 nm so as to cover the side surface of the bit line 30, and then the silicon oxide film is etched back, whereby the bit line 30 A side wall insulating film 31 having a thickness Y3 of about 16 nm is formed on the side surface (step A13; see FIGS. 19 and 20).

  Hereinafter, the bit line 30 including the mask film 29 may be referred to. The bit line 30 is formed as a pattern extending in the X direction intersecting the embedded word line 23, and the space width Y2 of the adjacent bit line 30 is 54 nm. In FIG. 20, the bit line 30 is shown in a straight line shape orthogonal to the embedded word line 23, but may be arranged in a partially curved shape. The impurity diffusion layer 26 of the silicon substrate 1 exposed in the bit contact opening 25 is connected to the conductive film 27 under the bit line 30.

In step A13, in the ALD method, (step B1) supply of source gas to the semiconductor substrate maintained at a predetermined temperature, (step B2) adsorption of source gas on the semiconductor substrate, (step B3) One cycle comprising steps of exhausting surplus source gas by vacuum purge, (step B4) supplying oxidizing gas, (step B5) oxidizing source gas by oxidizing gas, and (step B6) discharging surplus oxidizing gas by vacuum purge This process is repeated a plurality of times to form a film. Here, as an example of ALD process conditions in one cycle, trisdimethylaminosilane [TDMAS (Trisdimethyl Amino Silane): SiH [N (CH ₃ )] ₃ ] having a temperature of 550 ° C. and a pressure of 400 Pa as a source gas is shown. After supplying at a flow rate of 140 sccm (Standard Cubic Centimeter per Minute), ozone (O ₃ ) having a temperature of 550 ° C. is supplied as an oxidizing gas.

Etchback conditions for forming the sidewall insulating film 31 are tetrafluoromethane (reactive ion etching (RIE)), a high frequency power of 400 W, a pressure of 60 mTorr, and a temperature of 60 ° C. CF ₄ ) and trifluoromethane (CHF ₃ ) were used as process gases, and the respective flow rates were set to 150 sccm. At this time, the space width Y4 of the adjacent bit line 30 is narrower than Y2 and is 22 nm. The relationship between the space width Y4, the space width Y2, and the thickness Y3 of the sidewall insulating film 31 is “Y4 = Y2−Y3 × 2”. In the prior art, since a portion corresponding to the sidewall insulating film 31 is formed of a silicon nitride film having a relative dielectric constant larger than that of the silicon oxide film, the parasitic capacitance due to the adjacent bit line 30 increases, and the capacitor The ratio (C _s / C _b ) between the capacitance C _s and the parasitic capacitance C _b of the bit line becomes small, and there is a problem that the sense margin of the capacitor is lowered.

  The bit line 30 also serves as the gate electrode of the planar MOS transistor in the peripheral circuit portion, and the sidewall insulating film 31 covering the side surface of the bit line 30 is connected to the side wall of the gate electrode in the peripheral circuit portion. It has become.

  Next, a multilayer film 33 is formed so as to cover the bit line 30 (step A14; see FIGS. 21 and 22).

  Here, each of the multilayer films 33 is a polymer film, and is a lower layer film 33A that is an antireflection film (BARC: Bottom Anti Reflective Coating), an intermediate film 33B that is silicon-containing BARC, and an upper layer film that is a photoresist. 33C. The lower layer film 33A is applied so as to fill the space portion of the adjacent bit line 30, and the intermediate film 33B and the upper layer film 33C are sequentially formed so as to cover the flattened lower layer film 33A and the upper surface of the bit line 30. Laminated. The upper layer film 33C is patterned using a photolithography method, and the upper layer film 33C is left at the position where the capacitive contact plug is formed. The upper layer film 33C is patterned so as to extend in the Y direction. At this time, the intermediate film 33B and the lower layer film 33A remain without being patterned.

  Next, by using a dry etching method, the intermediate film 33B and the lower layer film 33A are patterned using the upper layer film (33C in FIGS. 21 and 22) as a mask (step A15; see FIG. 23).

Here, the dry etching conditions in step A15 are RIE, in which high frequency power is 800 W, pressure is 15 mTorr, temperature is 20 ° C., carbon monoxide (CO) and oxygen (O ₂ ) are process gases, The flow rate was set to 400 sccm (CO) and 140 sccm (O ₂ ). Since this dry etching is performed under the condition of selectively removing the intermediate film 33B and the lower layer film 33A, which are polymer films, the intermediate film 33B and the lower layer film 33A that are not covered with the upper layer film 33C are removed. The mask film 29 in contact with the bottom of 33B and the first interlayer insulating film 24 in contact with the bottom of the lower film 33A are both silicon oxide films, and the etching rate is 1 / of that of the intermediate film 33B and the lower film 33A. Since it is 400, it remains almost unetched and exposed. The upper layer film 33C disappears by patterning the intermediate film 33B and the lower layer film 33A.

  Next, a second interlayer insulating film 32 which is a silicon oxide film by an ALD method is formed on the substrate (wafer) so as to completely fill the remaining intermediate film 33B and lower layer film 33A (step A16; see FIG. 24). ).

Here, in step A16, an example of ALD process conditions in one cycle is shown. Monoaminosilane (SiH ₃ NH ₂ ) at a temperature of 25 ° C. and a pressure of 400 Pa is used as a source gas in a state where the high-frequency power is 100 W. After supplying at a flow rate of 250 sccm to 750 sccm, oxygen (O ₂ ) at a high frequency power of 100 W, a temperature of 25 ° C., and a pressure of 140 Pa is supplied as an oxidizing gas with a high frequency power of 100 W.

  Next, the second interlayer insulating film 32 is etched back so as to expose the upper surface of the lower layer film 33A (step A17; see FIG. 25). At this time, the intermediate film (33B in FIG. 24) containing silicon can be removed simultaneously with the second interlayer insulating film 32, which is a silicon oxide film, whereas the lower layer film 33A is removed by etch back. Therefore, the upper surface of the lower layer film 33A can be easily exposed.

  Next, the lower layer film (33A in FIG. 25) whose upper surface is exposed is selectively removed by an ashing method until the first interlayer insulating film 24 appears, and then the silicon substrate 1 is formed using a dry etching method. Until it appears, the exposed first interlayer insulating film 24 is removed to form a capacitor contact opening 35 (step A18; see FIGS. 26 and 27).

  Here, when the lower layer film (33A in FIG. 25) is removed, the second interlayer insulating film 32, the mask film 29, and the sidewall insulating film 31 remain without being removed by the ashing method. 33A) becomes a cavity, and a capacitor contact opening 35 having a side surface surrounded by the second interlayer insulating film 32 and the sidewall insulating film 31 on the first interlayer insulating film 24 is formed. Further, here, the capacitor contact opening 35 is formed by the SAC (Self Alignment Contact) method using the sidewall insulating film 31 and the second interlayer insulating film 32 as the sidewalls, and the first interlayer is formed at the bottom of the capacitor contact opening 35. The insulating film 24 is exposed.

  Further, when the first interlayer insulating film 24 is removed, the capacitor contact opening 35 becomes deeper, and the side surface portion of the capacitor contact opening 35 is formed by the second interlayer insulating film 32, the first interlayer insulating film 24, and the sidewall insulating film 31. Thus, the upper surface of the silicon substrate 1 is exposed at a portion where the capacitance contact opening 35 and the active region 1A intersect at the bottom surface.

  Next, a silicon nitride film is formed by thermal CVD so as to cover the inner wall of the capacitor contact opening (35 in FIG. 26), and then etched back to form a sidewall insulating film 36. An N-type impurity diffusion layer 37 is formed in the vicinity of the surface of the silicon substrate 1 by ion-implanting an N-type impurity (phosphorus or the like) into the silicon substrate 1, and then inside the capacitance contact opening (35 in FIG. 26). Then, a polysilicon film containing phosphorus is deposited by thermal CVD, and then etch back is performed to leave the conductive film 38, which is a polysilicon film, at the bottom of the capacitor contact opening (35 in FIG. 26). An intervening layer 39 which is a cobalt silicide (CoSi) film is formed on the surface of the conductive film 38 by sputtering, and then the inside of the capacitor contact opening (35 in FIG. 26) is filled. As described above, the conductive film 40 made of tungsten is deposited by the CVD method, and then the intervening layer 39 and the conductive film 40 are removed by the CMP method until the surface of the second interlayer insulating film 32 is exposed. The intervening layer 39 and the conductive film 40 are left only inside 35) of FIG. 26 (step A19; see FIG. 28).

  Here, the N-type impurity diffusion layer 37 functions as a source / drain region of the transistor. In addition, inside the capacitor contact opening (35 in FIG. 26), a capacitor contact plug 41 composed of the conductive film 38, the intervening layer 39, and the conductive film 40 is formed.

  Next, a laminated film in which tungsten nitride (WN) and tungsten (W) are sequentially deposited is formed on the upper surface of the substrate (wafer) by sputtering, and then the laminated film is patterned by using a photolithography method and a dry etching method. Thus, the capacitor contact pad 42 is formed (step A20; see FIG. 29). Here, the capacitor contact pad 42 is connected to the capacitor contact plug 41.

  Next, a stopper film 43, which is a silicon nitride film by thermal CVD, is formed so as to cover the upper surface of the capacitor contact pad 42. Thereafter, a third silicon oxide film by plasma CVD is formed on the upper surface of the stopper film 43. An interlayer insulating film 44 is formed (step A21; see FIG. 30).

  Next, a cylinder hole 44A penetrating the third interlayer insulating film 44 and the stopper film 43 is formed so as to expose at least a part of the upper surface of the capacitive contact pad 42 by using a photolithography method and a dry etching method, Thereafter, a conductive film to be the capacitor lower electrode 45 is formed of titanium nitride by CVD so as to cover the inner wall of the cylinder hole 44A, and then the conductive film on the upper surface of the third interlayer insulating film 44 is removed. A capacitor lower electrode 45 is formed in the cylinder hole 44A (step A22; see FIG. 31). Here, the bottom of the lower electrode 45 is connected to the capacitor contact pad 42.

Next, a capacitor insulating film 46 is formed by an ALD method so as to cover the upper surface of the substrate (wafer) including the surface of the lower electrode 45, and then an upper electrode 47 of the capacitor is formed by titanium nitride by a CVD method (step A23). See FIG. 32). Here, as the capacitor insulating film 46, zirconium oxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), or a stacked film thereof can be used.

  Finally, a fourth interlayer insulating film 49 is formed with a silicon oxide film by plasma CVD so as to cover the upper electrode 47, and then contacted with the fourth interlayer insulating film 49 by using a photolithography method and a dry etching method. A contact hole (not shown) for the plug 50 is formed, and then the contact hole is filled with tungsten by a CVD method. Then, excess tungsten on the fourth interlayer insulating film 49 is removed by CMP, A contact plug 50 is formed, and then an upper metal wiring 51 made of aluminum (Al) or copper (Cu) is formed on the upper surface of the fourth interlayer insulating film 49 by using a photolithography method and a dry etching method. A protective film 52 is formed on the surface of the fourth interlayer insulating film 49 including the upper metal wiring 51 (step A24; FIG. , See Figure 2). Thereby, the memory cell of the DRAM 100 is completed. Here, the upper metal wiring 51 is electrically connected to the upper electrode 47 through the contact plug 50.

As described above, the space portion between the adjacent bit lines 30 in this embodiment is covered with the sidewall insulating film 31 and the second interlayer insulating film 32 which are silicon oxide films. At this time, when the relative permittivity ε _sio of the silicon oxide film is 3.9 and the vacuum permittivity is ε ₀ , the parasitic capacitance C _b1 in the unit area of the adjacent bit line 30 is calculated, and C _b1 = (relative permittivity ε _sio ) × (vacuum dielectric constant ε ₀ ) / (space width Y 2), so C _b1 is 0.072 · ε ₀ .

On the other hand, in the space between the bit lines (portion corresponding to 30 in FIG. 1) in the prior art, the sidewall insulating film (portion corresponding to 31 in FIG. 1) is a silicon nitride film, and the second interlayer insulation The film (portion corresponding to 32 in FIG. 1) is a silicon oxide film. At this time, the relative permittivity ε _sio of the silicon oxide film is 3.9, the relative permittivity ε _sin of the silicon nitride film is 7.0, the vacuum permittivity is ε ₀ , and the adjacent bit lines (corresponding to 30 in FIG. 1). When calculating the parasitic capacitance C _b2 in the unit area of 1 / C _b2 = 1 / (relative permittivity ε _sin × vacuum permittivity ε ₀ / thickness Y3 × 2 of the sidewall insulating film 31) + 1 / ( Since the relative dielectric constant ε _sio × vacuum dielectric constant ε ₀ / space width Y4), C _b1 is 0.098 · ε ₀ . Therefore, in the present embodiment, the parasitic capacitance of the bit line 30 can be reduced by 26% compared to the prior art. The amount of reduction of the parasitic capacitance varies depending on the thickness Y3 of the sidewall insulating film 31 and the space width Y4 of the bit line 30, but in any case, in this embodiment, the sidewall insulating film 31 has a relative dielectric constant. Therefore, the parasitic capacitance can be reduced as compared with the prior art.

  An insulating film (mask film 29, sidewall insulating film 31) made of a silicon oxide film is formed on the upper and side walls of the bit line 30, and then covered with a lower layer film 33A made of BARC. The lower layer film 33A is left, and then covered with the second interlayer insulating film 32. Thereafter, the upper surface of the lower layer film 33A is exposed, and then the lower layer film 33A is removed to form the capacitor contact opening 35. There is no disclosure in Patent Document 1 about embedding the capacitor contact plug 41 in the capacitor contact opening 35.

  According to the first embodiment, the insulating film (mask film 29, sidewall insulating film 31) formed on the upper surface and side wall of the bit line 30 is formed of an insulating film such as a silicon oxide film having a dielectric constant smaller than that of the silicon nitride film. By using it, the parasitic capacitance can be made smaller than in the prior art.

  In the semiconductor device manufacturing method according to the first aspect, the insulating film preferably has a dielectric constant smaller than that of the silicon nitride film.

  In the method of manufacturing a semiconductor device according to the first aspect, the step of forming the plurality of conductive wirings includes a step of depositing a polysilicon film and a step of depositing a silicon oxide film on the polysilicon film. It is preferable to include.

  In the method of manufacturing a semiconductor device according to the first aspect, the step of forming the plurality of conductive wirings includes a step of depositing a tungsten film and a step of depositing a silicon oxide film on the tungsten film. Is preferred.

  In the method of manufacturing a semiconductor device according to the first aspect, it is preferable that the step of forming the plurality of conductive wirings includes a step of depositing a polysilicon film, a tungsten film, and a silicon oxide film in this order.

  In the method for manufacturing a semiconductor device according to the first aspect, in the step of covering with the polymer film, it is preferable to cover with a multilayer film including a polymer film containing silicon.

  In the method of manufacturing a semiconductor device according to the first aspect, it is preferable that in the step of forming the interlayer insulating film, a silicon oxide film is formed by an ALD method.

  In the method of manufacturing a semiconductor device according to the first aspect, it is preferable that the step of filling the conductive layer includes a step of depositing a polysilicon film doped with phosphorus.

  In the method of manufacturing a semiconductor device according to the first aspect, it is preferable that the step of embedding the conductive layer includes a step of depositing tungsten.

  In the method of manufacturing a semiconductor device according to the first aspect, in the step of embedding the conductive layer, a step of depositing a polysilicon film doped with phosphorus, a step of forming cobalt silicide on the polysilicon film, Forming tungsten on the cobalt silicide.

  In the semiconductor device manufacturing method according to the second aspect, the insulating film preferably has a dielectric constant smaller than that of the silicon nitride film.

  In the method of manufacturing a semiconductor device according to the third aspect, it is preferable that a polysilicon film is deposited in the step of depositing the conductive film.

  In the method of manufacturing a semiconductor device according to the third aspect, it is preferable that the metal film is deposited in the step of depositing the conductive film.

  In the method of manufacturing a semiconductor device according to the third aspect, it is preferable that a tungsten film is deposited on a polysilicon film in the step of depositing the conductive film.

  In the method of manufacturing a semiconductor device according to the third aspect, it is preferable that the silicon oxide film is deposited by an ALD method in the step of depositing the second silicon oxide film.

  In the method of manufacturing a semiconductor device according to the third aspect, it is preferable that the polymer film is etched back in the step of forming the opening.

  In the method of manufacturing a semiconductor device according to the third aspect, it is preferable that a diffusion layer is formed on the semiconductor substrate before the step of depositing the conductive film and the first oxide film.

  In the method of manufacturing a semiconductor device according to the third aspect, it is preferable that a diffusion layer is formed on the semiconductor substrate before the step of embedding the conductive layer.

  In the semiconductor device manufacturing method according to the third aspect, it is preferable that a sidewall of a silicon nitride film is formed on a sidewall of the opening before the step of filling the conductive layer.

  Note that, in the present application, where reference numerals are attached to the drawings, these are only for the purpose of helping understanding, and are not intended to be limited to the illustrated embodiments.

  Further, within the scope of the entire disclosure (including claims and drawings) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are included within the scope of the claims of the present invention. Is possible. That is, the present invention naturally includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 1A Active region 2 Sacrificial film 3 Mask film 4 Element isolation groove (trench)
6 Insulating film 7 Insulating film 8 Buried film 9 STI
DESCRIPTION OF SYMBOLS 10 Sacrificial film 11 Low concentration impurity diffusion layer 12 Lower layer mask film 13 Upper layer mask film 14 Channel region 15 Gate electrode trench (trench)
16 Gate insulating film 17 Intervening film 18, 18A Conductive film 20 Liner film 21 Embedded insulating film 22 Embedded wiring 23 Embedded word line 24 First interlayer insulating film (interlayer silicon oxide film)
25 Bit contact opening (opening)
26 Impurity diffusion layer (diffusion layer)
27 Conductive film (polysilicon film)
28 Conductive film (tungsten film, metal film)
29 Mask film (silicon oxide film, first silicon oxide film)
30 bit line (conductive wiring)
31 Side wall insulating film (second oxide film, side wall, silicon oxide film)
32 Second interlayer insulating film (silicon oxide film, third oxide film)
33 Multilayer film (polymer film)
33A Lower layer film 33B Intermediate film 33C Upper layer film 35 Capacitor contact opening (opening)
36 Side wall insulation film (side wall)
37 Impurity diffusion layer 38 Conductive film (polysilicon film)
39 Intervening film (cobalt silicide)
40 Conductive film (tungsten)
41 Capacitance contact plug (conductive layer)
42 Capacitor contact pad 43 Stopper film 44 Third interlayer insulating film 44A Cylinder hole 45 Lower electrode 46 Capacitor insulating film 47 Upper electrode 48 Capacitor 49 Fourth interlayer insulating film 50 Contact plug 51 Upper metal wiring 52 Protective film 100 DRAM

Claims (22)

Forming a plurality of conductive wirings whose side surfaces and upper surface are covered with an insulating film on a semiconductor substrate so as to extend in a first direction;
A step of covering a space between the plurality of conductive wirings on the semiconductor substrate with a polymer film;
Patterning the polymer film in a second direction intersecting the first direction and leaving it on the semiconductor substrate;
Forming an interlayer insulating film on the semiconductor substrate including the polymer film and the plurality of conductive wirings;
Removing the interlayer insulating film until the upper surface of the polymer film appears;
Removing the polymer film whose upper surface appears;
Embedding a conductive layer in the portion where the polymer film has been removed;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film has a dielectric constant smaller than that of the silicon nitride film.   2. The semiconductor device according to claim 1, wherein the step of forming the plurality of conductive wirings includes a step of depositing a polysilicon film and a step of depositing a silicon oxide film on the polysilicon film. Production method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the plurality of conductive wirings includes a step of depositing a tungsten film and a step of depositing a silicon oxide film on the tungsten film. .   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the plurality of conductive wirings includes a step of depositing a polysilicon film, a tungsten film, and a silicon oxide film in this order.   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of covering with a polymer film, the film is covered with a multilayer film including a polymer film containing silicon.   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the interlayer insulating film, a silicon oxide film is formed by an ALD method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of embedding the conductive layer includes a step of depositing a polysilicon film doped with phosphorus.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of embedding the conductive layer includes a step of depositing tungsten.   The step of embedding the conductive layer includes a step of depositing a polysilicon film doped with phosphorus, a step of forming cobalt silicide on the polysilicon film, and a step of forming tungsten on the cobalt silicide. The method of manufacturing a semiconductor device according to claim 1. Forming a first interlayer insulating film having an opening on a semiconductor substrate;
Forming a plurality of conductive wirings whose side surfaces and upper surface are covered with an insulating film in the opening on the semiconductor substrate so as to extend in a first direction;
Covering the space between the plurality of conductive wirings on the first interlayer insulating film with a polymer film;
Patterning the polymer film in a second direction intersecting the first direction and leaving it on the semiconductor substrate;
Forming a second interlayer insulating film on the semiconductor substrate including the polymer film and the plurality of conductive wirings;
Removing the second interlayer insulating film until the upper surface of the polymer film appears;
Removing the polymer film whose upper surface appears until the upper surface of the first interlayer insulating film appears;
Removing the first interlayer insulating film whose upper surface appears until the upper surface of the semiconductor substrate appears;
Embedding a conductive layer in a portion where the polymer film and the first interlayer insulating film are removed;
A method for manufacturing a semiconductor device, comprising:   12. The method of manufacturing a semiconductor device according to claim 11, wherein the insulating film has a dielectric constant smaller than that of the silicon nitride film. Depositing a conductive film and a first silicon oxide film in this order on a semiconductor substrate;
Forming a plurality of bit lines by patterning the conductive film and the first silicon oxide film to extend in a first direction;
Depositing a second silicon oxide film on the semiconductor substrate including the plurality of bit lines;
Forming a sidewall by leaving the second silicon oxide film on the sidewalls of the plurality of bit lines by etch back;
Applying a polymer film between the plurality of bit lines on the semiconductor substrate;
Patterning the polymer film in a second direction intersecting the first direction and leaving it on the semiconductor substrate; and exposing the semiconductor substrate;
Forming a third silicon oxide film on the semiconductor substrate including the remaining polymer film and the plurality of bit line wirings;
Removing the third silicon oxide film until an upper surface of the polymer film appears;
Removing the polymer film to form an opening communicating with the semiconductor substrate;
Burying a conductive layer in the opening on the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising:   14. The method of manufacturing a semiconductor device according to claim 13, wherein in the step of depositing the conductive film, a polysilicon film is deposited.   14. The method of manufacturing a semiconductor device according to claim 13, wherein in the step of depositing the conductive film, a metal film is deposited.   14. The method of manufacturing a semiconductor device according to claim 13, wherein in the step of depositing the conductive film, a tungsten film is deposited on the polysilicon film.   14. The method of manufacturing a semiconductor device according to claim 13, wherein in the step of depositing the second silicon oxide film, a silicon oxide film is deposited by an ALD method.   14. The method of manufacturing a semiconductor device according to claim 13, wherein in the step of forming the opening, the polymer film is etched back.   14. The method of manufacturing a semiconductor device according to claim 13, wherein a diffusion layer is formed on the semiconductor substrate before the step of depositing the conductive film and the first oxide film.   14. The method of manufacturing a semiconductor device according to claim 13, wherein a diffusion layer is formed on the semiconductor substrate before the step of embedding the conductive layer.   14. The method of manufacturing a semiconductor device according to claim 13, wherein a side wall of the silicon nitride film is formed on a side wall of the opening before the step of embedding the conductive layer. Forming an interlayer silicon oxide film having an opening on a semiconductor substrate;
Depositing a conductive film and a first silicon oxide film in this order in the opening on the semiconductor substrate;
Forming a plurality of bit lines by patterning the conductive film and the first silicon oxide film to extend in a first direction;
Depositing a second silicon oxide film on the semiconductor substrate including the plurality of bit lines;
Forming a sidewall by leaving the second silicon oxide film on the sidewalls of the plurality of bit lines by etch back;
Applying a polymer film between the plurality of bit lines on the interlayer silicon oxide film;
Patterning the polymer film in a second direction intersecting the first direction and leaving it on the interlayer silicon oxide film, and exposing the interlayer silicon oxide film;
Forming a third silicon oxide film on the interlayer silicon oxide film including the remaining polymer film and the plurality of bit line wirings;
Removing the third silicon oxide film until an upper surface of the polymer film appears;
Removing the polymer film and the interlayer silicon oxide film exposed on the upper surface to form another opening that leads to the semiconductor substrate;
Burying a conductive layer in the other opening on the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising:

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