CN107369649B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN107369649B CN107369649B CN201610308959.0A CN201610308959A CN107369649B CN 107369649 B CN107369649 B CN 107369649B CN 201610308959 A CN201610308959 A CN 201610308959A CN 107369649 B CN107369649 B CN 107369649B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
Abstract
The invention provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors. The method comprises the following steps: providing a first substrate, forming a radio frequency front-end device comprising a transistor and a first interconnection structure on one side of a first surface of the first substrate, and forming a second interconnection structure positioned outside the transistor; providing a second substrate, and bonding the second substrate with one side of the first substrate, on which the radio frequency front-end device is formed, through a bonding process; thinning the first substrate from a side of a second surface of the first substrate opposite to the first surface to a first substrate thickness; forming a back dielectric layer on the second surface of the first substrate thinned to the thickness of the first substrate; the first substrate thickness is above 0.01 times the minimum feature size of the transistor and below 10 times the maximum feature size of the transistor. According to the manufacturing method, the bulk silicon substrate is thinned, so that the radio frequency performance of the CMOS device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
With the improvement of CMOS performance and the trend of integration of wireless communication chips, Radio Frequency (RF) CMOS process is not only a popular subject of research in the academic world, but also has attracted attention in the industry. The RF CMOS process has the greatest advantage of high integration of RF, baseband and memory devices, while reducing device cost.
RF CMOS processes can generally be divided into two broad categories: bulk silicon CMOS processes and silicon-on-insulator (SOI) CMOS processes. The bulk silicon CMOS process has a lower cost than the SOI CMOS process, however, in the conventional bulk silicon CMOS process, the radio frequency characteristics of the device are greatly reduced due to the influence of the substrate.
Therefore, in order to solve the above technical problems, it is necessary to provide a new semiconductor device and a method for manufacturing the same.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to overcome the problems existing at present, an aspect of the present invention provides a method for manufacturing a semiconductor device, the method comprising:
providing a first substrate, forming a radio frequency front-end device comprising a plurality of transistors and a first interconnection structure on one side of a first surface of the first substrate, and forming a second interconnection structure positioned outside the transistors;
providing a second substrate, and bonding the second substrate and one side of the first substrate, on which the radio frequency front-end device is formed, through a bonding process;
thinning the first substrate from a side of a second surface of the first substrate opposite to the first surface to a first substrate thickness;
forming a back dielectric layer on the second surface of the first substrate thinned to the thickness of the first substrate;
wherein the first substrate thickness is greater than or equal to 0.01 times the transistor minimum feature size and less than or equal to 10 times the transistor maximum feature size.
Further, shallow trench isolation structures are formed in the first substrate on one side of the first surface of the first substrate and on two sides of the transistor.
Further, the thinning treatment is stopped on the shallow trench isolation structure.
Further, after the back dielectric layer is formed, the method further comprises the following steps:
forming a through hole structure electrically connected with a bottom metal layer of the second interconnection structure on one side of the second surface of the first substrate;
forming a pad on a portion of the second surface of the first substrate, the pad being electrically connected to the via structure.
Further, after forming the pad, the method further includes the steps of:
and forming a passivation layer covering the second surface of the first substrate and exposing the routing area of the bonding pad.
Further, the first substrate is a bulk silicon substrate.
Further, the thinning treatment method uses one or more of a back grinding process, a chemical mechanical polishing process or a wet etching process.
Further, the first interconnection structure comprises a bottom metal layer, a top metal layer and an intermediate metal layer positioned between the bottom metal layer and the top metal layer, and a metal-insulation layer-metal capacitor is formed on part of the intermediate metal layer.
Further, a bonding layer is formed on a surface of the second substrate bonded to the first substrate before the bonding process is performed.
The invention also provides a semiconductor device manufactured by the method.
In summary, according to the manufacturing method of the invention, the bulk silicon substrate is thinned, so that the radio frequency performance of the CMOS device is improved. The semiconductor device of the present invention has the same advantages as described above because of the above manufacturing method.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIGS. 1A-1E are cross-sectional views of structures formed at steps associated with a method of fabricating a semiconductor device, in accordance with an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method of manufacturing a semiconductor device according to another embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In order to solve the problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 2, the method comprising:
step S201: providing a first substrate, forming a radio frequency front-end device comprising a plurality of transistors and a first interconnection structure on one side of a first surface of the first substrate, and forming a second interconnection structure positioned outside the transistors;
step S202: providing a second substrate, and bonding the second substrate and one side of the first substrate, on which the radio frequency front-end device is formed, through a bonding process;
step S203: thinning the first substrate from a side of a second surface of the first substrate opposite to the first surface to a first substrate thickness;
step S204: forming a back dielectric layer on the second surface of the first substrate thinned to the thickness of the first substrate;
wherein the first substrate thickness is greater than or equal to 0.01 times the transistor minimum feature size and less than or equal to 10 times the transistor maximum feature size.
In summary, according to the manufacturing method of the invention, the substrate is thinned, so that the radio frequency performance and the device yield of the CMOS device are improved. The semiconductor device of the present invention has the same advantages as described above because of the above manufacturing method.
Example one
Next, detailed steps of an exemplary method of a method of manufacturing a semiconductor device proposed by an embodiment of the present invention are described with reference to fig. 1A to 1E and fig. 2. Fig. 1A to 1E are cross-sectional views of structures formed in the relevant steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention; fig. 2 is a schematic flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
The method for manufacturing the semiconductor device of the embodiment specifically includes the following steps:
first, as shown in fig. 1A, a first substrate 100 is provided, and a radio frequency front end device including a transistor 102 and a first interconnect structure 103, and a second interconnect structure 105 located outside the transistor 102 are formed on a first surface side of the first substrate 100.
In particular, the first substrate 100 is a bulk silicon substrate, which may be at least one of the materials mentioned below: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, and also includes multilayer structures and the like composed of these semiconductors.
Shallow trench isolation structures 101 are formed in the first substrate 100 on one side of the first surface of the first substrate 100 and on two sides of the transistor 102.
The steps of forming the shallow trench isolation structure and defining the active region are well known to those skilled in the art and will not be described in detail herein, and any suitable method may be used to form the shallow trench isolation structure and define the active region.
Optionally, the material filled in the shallow trench isolation structure 101 may be one or more of silicon oxide, silicon nitride, or silicon oxynitride.
As an example, a radio frequency device is also formed on the first surface of the first substrate 100. In this embodiment, the transistor 102 is used to form various circuits, the rf device is used to form rf components or modules, and the first interconnect structure 103 is used to connect the transistor 102, the rf device, and other components in the rf front-end device. The transistor 102 may be a normal transistor, a high-k metal gate transistor, a fin transistor, or other suitable transistors. The first interconnect structure 103 may include a metal layer (e.g., a copper layer or an aluminum layer), a via, and the like. The radio frequency device may include an inductor (inductor) or the like.
The second interconnect structure 105 corresponds to a region where a pad is to be formed, wherein the second interconnect structure 105 includes a plurality of metal layers (e.g., copper layers or aluminum layers) and vias between adjacent metal layers, and wherein the bottom metal layer 1051 of the second interconnect structure 105 is located above the first surface of the first substrate 100.
Optionally, the first interconnect structure 103 and the second interconnect structure 105 include a bottom metal layer, a top metal layer, and an intermediate metal layer located between the bottom metal layer and the top metal layer, and different metal materials may be used for the respective metal layers, for example, the material of the bottom metal layer and the material of the top metal layer may be copper, and the material of the intermediate metal layer may be aluminum.
In addition to the transistor 102, the rf front-end device and the first interconnect structure 103, the rf front-end device may include various other possible components, such as resistors, capacitors, MEMS devices, etc., which are not limited herein.
Optionally, passive devices are disposed on the first surface of the first substrate, which may include metal-insulator-metal capacitors (MIMs) 104, spiral inductors, and the like.
The first interconnect structure 103 includes a bottom metal layer, a top metal layer, and an intermediate metal layer between the bottom metal layer and the top metal layer, and the metal-insulator-metal capacitor 104 is formed on a portion of the intermediate metal layer, as shown in fig. 1A.
The specific structure and the forming method of each component in the rf front-end device may be selected by those skilled in the art according to actual needs by referring to the prior art, and are not described herein again.
Illustratively, the second interconnect structure 105 and the first interconnect structure 103 may be formed simultaneously, and the forming method may be selected from conventional manufacturing methods, such as forming a dielectric layer, then patterning the dielectric layer to form an opening and filling the opening with a conductive material, sequentially forming various metal layers and a via to form the interconnect structure, and further depositing a dielectric layer to cover the top metal layer and planarize the dielectric layer after forming the top metal layer, as shown in fig. 1A.
The top metal layer is made of a metal material Cu, the deposition method of the metal material Cu can be one of low-pressure chemical vapor deposition (LPCVD), Laser Ablation Deposition (LAD) and Selective Epitaxial Growth (SEG) formed by a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, an Atomic Layer Deposition (ALD) method and the like, the Physical Vapor Deposition (PVD) method is preferred in the invention, and an electrochemical plating method and the like can also be used.
Further, a bonding layer 106 may be selectively formed on the first surface of the first substrate, wherein the bonding layer 106 is selected from an oxide, such as SiO2Etc., are not limited to the examples.
Next, as shown in fig. 1B, a second substrate 200 is provided, and a bonding layer 201 is formed on a surface of the second substrate 200 bonded to the first substrate 100.
In this embodiment, the second substrate 200 is a carrier wafer (carrier wafer) for carrying and protecting rf front-end devices in the subsequent process of thinning the first substrate 100 and other subsequent processes. The second substrate 200 may be any semiconductor substrate such as silicon, a ceramic substrate such as alumina, a quartz or glass substrate, or the like.
The bonding layer 201 may be any suitable film layer material used in a bonding process, for example, the material of the bonding layer 201 may be silicon oxide, silicon oxynitride, or the like, and may be formed by any method known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like.
The bonding layer 201 may also be a stack of multiple film layers.
Next, as shown in fig. 1C, the second substrate 200 is bonded to the side of the first substrate 100 on which the rf front-end device is formed through a bonding process.
Illustratively, the bonding layer 106 and the bonding layer 201 are directly contacted with each other, and one side of the second substrate 200 is bonded with one side (i.e., the first surface side) of the first substrate 100 on which the rf front-end device is formed, as shown in fig. 1C. The bonding process may be performed by any method known to those skilled in the art, such as an oxide fusion bonding process, and the like.
Next, as shown in fig. 1D, the first substrate 200 is thinned from the second surface side of the first substrate 100 opposite to the first surface to the first substrate thickness.
The thickness of the first substrate 100 remaining after the thinning process can be reasonably selected according to the actual needs of the device. According to the technical requirements of a radio frequency front end system and the radio frequency transistor, the first substrate thickness should be more than 0.01 times of the minimum characteristic size of the transistor and less than 10 times of the maximum characteristic size of the transistor; for example, if the channel length of the included rf switch CMOS transistor is 250 nm, which is the minimum feature size, the first substrate thickness should be above 2.5 nm, and if the channel length of the included rf high voltage or power CMOS transistor is 2.0 microns, which is the maximum feature size, the first substrate thickness should be below 20 microns.
Feature size refers to the smallest dimension in a semiconductor device. In a CMOS process, the feature size is typically represented by the width of the "gate structure", i.e., the channel length of the MOS device.
The plurality of transistors formed on the semiconductor substrate in the present embodiment include different types of transistors, such as an rf switch CMOS transistor and an rf high voltage or power CMOS transistor, and the plurality of transistors have different feature sizes, that is, different channel lengths, so that the minimum feature size refers to a minimum channel length among the plurality of transistors, and the maximum feature size refers to a maximum channel length among the plurality of transistors.
Illustratively, the first substrate 100 is a bulk silicon substrate in which shallow trench isolation structures 101 are disposed, and the thinning process stops above the shallow trench isolation structures 101 located within the bulk silicon substrate.
The thinning process may be one or more of a back grinding process, a Chemical Mechanical Polishing (CMP) process, or a wet etching process, or may be other suitable processes.
Wherein, the back grinding process has a faster grinding rate, so that the substrate can be thinned quickly, and the thinning of the first substrate 200 can be realized by combining a CMP and/or a wet etching process in order to obtain a smooth surface.
When the first substrate is a bulk silicon substrate, the RF performance of the device can be improved by thinning the bulk silicon substrate.
Next, as shown in fig. 1E, a back dielectric layer 107 is formed on the second surface of the first substrate 100 thinned to the thickness of the first substrate, a via structure 108 electrically connected to the bottom metal layer 1051 of the second interconnect structure 105 is formed on the second surface of the first substrate 100, a pad 109 is formed on a portion of the second surface of the first substrate, and the pad 109 is electrically connected to the via structure 107.
The material of the back dielectric layer 107 may include, but is not limited to, silicon oxide or silicon nitride, such as SiO2Fluorocarbon (CF), silicon oxide doped with carbon (SiOC), silicon nitride (SiN), or silicon carbonitride (SiCN). Alternatively, a film in which a SiCN thin film is formed on fluorocarbon (CF) or the like may be used. The fluorocarbon compound contains fluorine (F) and carbon (C) as main components. As the fluorocarbon, a fluorocarbon having an amorphous (non-crystalline) structure may be used.
The backside dielectric layer 107 may be formed by any deposition process known to those skilled in the art, such as a Chemical Vapor Deposition (CVD) process, a physical vapor deposition (pvd) process, and the like, wherein the CVD process may be selected from a thermal CVD (thermal CVD) process or a High Density Plasma (HDP) process.
The deposition thickness may be selected as appropriate according to the size of a semiconductor device to be formed, and is not particularly limited herein.
Illustratively, the method of forming the via structure 108 includes the steps of: first, a back dielectric layer 107, a shallow trench isolation structure 101, and a part of the dielectric layer on the front surface of the shallow trench isolation structure are sequentially etched from the second surface of the first substrate 100 until a part of the bottom metal layer 1051 of the second interconnect structure 105 is exposed, so as to form a via opening.
The back dielectric layer 107, the shallow trench isolation structure 101 and a part of the dielectric layer on the front surface of the shallow trench isolation structure may be etched by dry etching or wet etching. The dry etching can employ an anisotropic etching method based on a carbon fluoride gas. The wet etch can use a hydrofluoric acid solution, such as a Buffered Oxide Etchant (BOE) or a buffered hydrofluoric acid (BHF), to stop on the bottom metal layer 1051 of the second interconnect structure 105.
The via structure opening is then filled to form a via structure, wherein the via structure 108 comprises, in order from the inside to the outside, a conductive layer, a barrier layer, and a liner layer.
The conductive layer may be any suitable material having conductivity, including but not limited to a metal material, and the metal material may include one or more of metals such as Cu, Al, or W.
The pad 109 is used to input a signal or power to the inside of the semiconductor device through the second interconnect structure 105 and the first interconnect structure 103. The material of the bonding pad 109 may be aluminum, copper, or other suitable conductive material. The film can be formed by physical vapor deposition, chemical vapor deposition and the like.
Subsequently, the method further comprises the steps of: a passivation layer 110 is formed covering the second surface of the first substrate 100 but exposing the wire bonding area of the pad 109.
In one example, a passivation layer 110 is formed covering the second surface of the first substrate 100 but exposing the wire bonding area of the bonding pad 105.
The passivation layer 110 serves to protect the first substrate 100 and the pad 109. The material of the passivation layer 110 may be silicon oxide, silicon nitride, or other suitable materials. The passivation layer 110 may be deposited by chemical vapor deposition or the like.
Thus, the description of the key steps of the method of manufacturing the semiconductor device of the present embodiment is completed. For the complete device manufacturing method, other preceding steps, intermediate steps or subsequent steps may also be required, which are not described in detail herein.
In summary, according to the manufacturing method of the present invention, the bulk silicon substrate is thinned, so that the radio frequency performance of the CMOS device is improved, and the production cost of the device can be reduced.
Example two
The embodiment of the invention provides a semiconductor device which is prepared by adopting the manufacturing method in the first embodiment. The semiconductor device may be an integrated circuit or an integrated circuit intermediate product including a Radio Frequency (RF) device.
Next, a structure of a semiconductor device proposed by an embodiment of the present invention is described with reference to fig. 1E. Fig. 1E is a cross-sectional view of a structure of a semiconductor device according to an embodiment of the present invention.
As shown in fig. 1E, the semiconductor device of the present embodiment includes:
a first substrate 100, a radio frequency front end device including a transistor 102 and a first interconnection structure 103 and a second interconnection structure 105 located outside the transistor 102 are formed on a first surface side of the first substrate 100, a via structure 108 is formed on a second surface side of the first substrate 100 opposite to the first surface after thinning, the via structure 108 is electrically connected with a bottom metal layer 1051 of the second interconnection structure 105, a pad 109 is formed on a part of the second surface of the first substrate 100, the pad 109 is electrically connected with the via structure 108, and a second substrate 200 is disposed to be bonded to a side of the first substrate 100 on which the radio frequency front end device is formed.
In particular, the first substrate 100 is a bulk silicon substrate, which may be at least one of the materials mentioned below: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, and also includes multilayer structures and the like composed of these semiconductors.
Wherein the thinned first substrate 100 has a first substrate thickness, and the first substrate thickness should be greater than or equal to 0.01 times the minimum feature size of the transistor and less than or equal to 10 times the maximum feature size of the transistor according to the rf front-end system and the specifications of the rf transistor; for example, if the channel length of the included rf switch CMOS transistor is 250 nm, which is the minimum feature size, the first substrate thickness should be above 2.5 nm, and if the channel length of the included rf high voltage or power CMOS transistor is 2.0 microns, which is the maximum feature size, the first substrate thickness should be below 20 microns.
Shallow trench isolation structures 101 are formed in the first substrate 100 on one side of the first surface of the first substrate 100 and on two sides of the transistor 102.
The steps of forming the shallow trench isolation structure and defining the active region are well known technical means for those skilled in the art and will not be described in detail herein, and any suitable method may be used to form the shallow trench isolation structure and define the active region.
Optionally, the material filled in the shallow trench isolation structure 101 may be one or more of silicon oxide, silicon nitride, or silicon oxynitride.
As an example, a radio frequency device is also formed on the first surface of the first substrate 100. In this embodiment, the transistor 102 is used to form various circuits, the rf device is used to form rf components or modules, and the first interconnect structure 103 is used to connect the transistor 102, the rf device, and other components in the rf front-end device. The transistor 102 may be a normal transistor, a high-k metal gate transistor, a fin transistor, or other suitable transistors. The first interconnect structure 103 may include a metal layer (e.g., a copper layer or an aluminum layer), a via, and the like. The radio frequency device may include an inductor (inductor) or the like.
The second interconnect structure 105 corresponds to a region where a pad is to be formed, wherein the second interconnect structure 105 includes a plurality of metal layers (e.g., copper layers or aluminum layers) and vias between adjacent metal layers, and wherein the bottom metal layer 1051 of the second interconnect structure 105 is located above the first surface of the first substrate 100.
Optionally, the first interconnect structure 103 and the second interconnect structure 105 include a bottom metal layer, a top metal layer, and an intermediate metal layer located between the bottom metal layer and the top metal layer, and different metal materials may be used for the respective metal layers, for example, the material of the bottom metal layer and the material of the top metal layer may be copper, and the material of the intermediate metal layer may be aluminum.
In addition to the transistor 102, the rf front-end device and the first interconnect structure 103, the rf front-end device may include various other possible components, such as resistors, capacitors, MEMS devices, etc., which are not limited herein.
Optionally, the passive devices are disposed on the first surface of the first substrate, and may include a metal-insulator-metal capacitor (MIM)104, a spiral inductor, or the like.
Wherein the first interconnect structure 103 includes a bottom metal layer, a top metal layer, and an intermediate metal layer between the bottom metal layer and the top metal layer, and the metal-insulator-metal capacitor 104 is formed on a portion of the intermediate metal layer, as shown in fig. 1E.
The specific structure and the forming method of each component in the rf front-end device may be selected by those skilled in the art according to actual needs by referring to the prior art, and are not described herein again.
The second interconnect structure 105 and the first interconnect structure 103 may be formed at the same time, and the forming method may be a conventional manufacturing method, and both the second interconnect structure 105 and the first interconnect structure 103 are disposed in a dielectric layer.
Further, a second substrate 200 is provided to be bonded to the side of the first substrate 100 where the rf front-end device is formed, wherein a bonding layer 201 is provided on a surface where the second substrate 200 is bonded to the first substrate, and a bonding layer 106 is optionally further formed on the first surface of the first substrate, and the bonding layer 201 and the bonding layer 106 are directly in contact bonding, thereby achieving bonding of the first substrate 100 and the second substrate 200.
Wherein the bonding layer 106 is made of oxide, such as SiO2Etc. are not limited to the examples。
The second substrate 200 may be any semiconductor substrate such as silicon, a ceramic substrate such as alumina, a quartz or glass substrate, or the like.
The bonding layer 201 may be any suitable film layer material used in a bonding process, for example, the material of the bonding layer 201 may be silicon oxide, silicon oxynitride, or the like, and the bonding layer 201 may also be a stack of multiple film layers.
Further, the back surface of the shallow trench isolation structure 101 is exposed at the second surface of the thinned first substrate 100.
Illustratively, a backside dielectric layer 107 is formed on the second surface of the first substrate 100 thinned to the thickness of the first substrate, a via structure 108 is formed on the side of the second surface of the first substrate 100 opposite to the first surface after thinning, the via structure 108 is electrically connected to the bottom metal layer 1051 of the second interconnect structure 105, a pad 109 is formed on a portion of the second surface of the first substrate 100, the pad 109 is electrically connected to the via structure 108, and a second substrate 200 is bonded to the side of the first substrate 100 on which the rf front-end device is formed.
Wherein, the material of the back dielectric layer 107 may include, but is not limited to, silicon oxide or silicon nitride, such as SiO2Fluorocarbon (CF), silicon oxide doped with carbon (SiOC), silicon nitride (SiN), or silicon carbonitride (SiCN). Alternatively, a film in which a SiCN thin film is formed on fluorocarbon (CF) or the like may be used. The fluorocarbon compound contains fluorine (F) and carbon (C) as main components. As the fluorocarbon, a fluorocarbon having an amorphous (non-crystalline) structure may be used.
The via structure 108 includes a conductive layer, a barrier layer, and a liner layer from inside to outside.
The conductive layer may be any suitable material having conductivity, including but not limited to a metal material, and the metal material may include one or more of metals such as Cu, Al, or W.
Illustratively, the via structure 108 is electrically connected from the second surface of the first substrate, sequentially through the backside dielectric layer 107, the shallow trench isolation structure 101, the dielectric layer on the front side of the shallow trench isolation structure 101, and to directly contact the bottom metal layer 1051 of the second interconnect structure 105.
The pad 109 is used to input a signal or power to the inside of the semiconductor device through the second interconnect structure 105 and the first interconnect structure 103. The material of the bonding pad 109 may be aluminum, copper, or other suitable conductive material. Illustratively, a passivation layer 110 is disposed covering the second surface of the first substrate 100 but exposing the wire bonding area of the pad 109.
The passivation layer 110 serves to protect the first substrate 100 and the pad 109. The material of the passivation layer 110 may be silicon oxide, silicon nitride, or other suitable materials. The passivation layer 110 may be deposited by chemical vapor deposition or the like.
The semiconductor device of the present invention has the same advantages as those described above since it is obtained by the manufacturing method described in the first embodiment.
The semiconductor device of this embodiment may be a radio frequency front end module or other circuits or modules. The radio frequency performance of the semiconductor device is improved, so that the requirements on the device performance under more application environments can be met.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (9)
1. A method of manufacturing a semiconductor device, the method comprising:
providing a first substrate, forming a radio frequency front-end device comprising a plurality of transistors and a first interconnection structure on one side of a first surface of the first substrate, and forming a second interconnection structure positioned outside the transistors; shallow trench isolation structures are formed in the first substrate on one side of the first surface of the first substrate and on two sides of the transistor;
providing a second substrate, and bonding the second substrate and one side of the first substrate, on which the radio frequency front-end device is formed, through a bonding process;
thinning the first substrate from a side of a second surface of the first substrate opposite to the first surface to a first substrate thickness;
forming a back dielectric layer on the second surface of the first substrate thinned to the thickness of the first substrate;
wherein the first substrate thickness is greater than or equal to 0.01 times the transistor minimum feature size and less than or equal to 10 times the transistor maximum feature size; the minimum feature size refers to a minimum channel length among the plurality of transistors, and the maximum feature size refers to a maximum channel length among the plurality of transistors.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the thinning process is stopped on the shallow trench isolation structure.
3. The manufacturing method of the semiconductor device according to claim 1 or 2, further comprising, after forming the back side dielectric layer, the steps of:
forming a through hole structure electrically connected with a bottom metal layer of the second interconnection structure on one side of the second surface of the first substrate;
forming a pad on a portion of the second surface of the first substrate, the pad being electrically connected to the via structure.
4. A method for manufacturing a semiconductor device according to claim 3, further comprising, after forming the pad, the steps of:
and forming a passivation layer covering the second surface of the first substrate and exposing the routing area of the bonding pad.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the first substrate is a bulk silicon substrate.
6. The method for manufacturing a semiconductor device according to claim 1, wherein the thinning process uses one or more of a back grinding process, a chemical mechanical polishing process, or a wet etching process.
7. The method of manufacturing of claim 1, wherein the first interconnect structure comprises a bottom metal layer, a top metal layer, and an intermediate metal layer between the bottom metal layer and the top metal layer, a metal-insulator-metal capacitor being formed on a portion of the intermediate metal layer.
8. The manufacturing method according to claim 1, wherein a bonding layer is formed on a surface of the second substrate bonded to the first substrate before the bonding process is performed.
9. A semiconductor device, characterized in that it is obtained by being manufactured with a method according to one of claims 1 to 8.
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