US20180366540A1

US20180366540A1 - Semiconductor devices comprising vias and capacitors

Info

Publication number: US20180366540A1
Application number: US16/110,615
Authority: US
Inventors: Tieh-Chiang Wu; Shing-Yih Shih
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2015-11-16
Filing date: 2018-08-23
Publication date: 2018-12-20
Also published as: CN106711083A; TW201719808A; CN106711083B; TWI590381B; US20170141185A1; CN110718505A; US10121849B2

Abstract

A semiconductor structure and a method of fabricating thereof are provided. The method includes the following steps. A substrate with an upper surface and a lower surface is received. A first recess extending from the upper surface to the lower surface is formed and the first recess has a first depth. A second recess extending from the upper surface to the lower surface is formed and the second recess has a second depth less than the first depth. A first conducting layer is formed in the first recess and the second recess. A first insulating layer is formed over the first conducting layer. A second conducting layer is formed over the first insulating layer and isolated from the first conducting layer with the first insulating layer. The substrate is thinned from the lower surface to expose the second conducting layer in the first recess.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No. 14/941,665, filed Nov. 16, 2015, pending, the disclosure of which is hereby incorporated herein in its entirety by this reference.

TECHNICAL FIELD

Embodiments disclosed herein relate to semiconductor devices and to semiconductor device fabrication. More particularly, embodiments of the disclosure relate to semiconductor devices comprising via structures and capacitor structures.

BACKGROUND

In order to continue to improve functionality and performance of integrated circuits, the semiconductor industry has recently been developing technology to enable the vertical integration of semiconductor devices, generally known as three-dimensional (3D) stacking technology. Typically, through-silicon-vias (TSVs) are becoming a viable approach for improving chip performance and on-chip decoupling capacitors (decaps) serving as charge reservoirs and are used to support instantaneous current surges, suppress power fluctuations and prevent noise-related circuit degradation in integrated circuits.
Conventional on-chip decoupling capacitors may be planar-type or trench-type. Because trench-type capacitors have a capacitance density advantage over planar-type capacitors, the trench-type capacitors are usually used in semiconductor devices. Therefore, the demands to forming TSVs and trench-type capacitors simultaneously have increased. However, traditional fabricating methods are expensive because of complex and costly processes. For example, sacrificial layers are usually used in fabrication steps.
Accordingly, an improved semiconductor structure that includes a capacitor structure and a via structure, and a fabricating method of the semiconductor structure are required.

BRIEF SUMMARY

The instant disclosure provides a method of fabricating a semiconductor structure, and the method includes the following steps. A substrate with an upper surface and a lower surface is received. A first recess extending from the upper surface to the lower surface is formed and the first recess has a first depth. A second recess extending from the upper surface to the lower surface is formed and the second recess has a second depth less than the first depth. A first conducting layer is formed in the first recess and the second recess. A first insulating layer is formed over the first conducting layer. A second conducting layer is formed over the first insulating layer and isolated from the first conducting layer with the first insulating layer. The substrate is thinned from the lower surface to expose the second conducting layer in the first recess.
In various embodiments of the instant disclosure, forming the first recess and the second recess are by laser drilling, dry etching or wet etching.
In various embodiments of the instant disclosure, the dry etching includes reactive ion etching (RIE).
In various embodiments of the instant disclosure, forming the first recess and forming the second recess include forming a photoresist layer over the upper surface, wherein the photoresist layer has a first opening and a second opening smaller than the first opening. Next, the substrate is etched through the first opening to form the first recess and through the second opening to form the second recess.
In various embodiments of the instant disclosure, the first conducting layer in the second recess is exposed after thinning the substrate from the lower surface.
In various embodiments of the instant disclosure, thinning the substrate from the lower surface stops before exposing the first conducting layer in the second recess.
In various embodiments of the instant disclosure, thinning the substrate from the lower surface is by backside grinding, chemical-mechanical polishing or blanket etching process.
In various embodiments of the instant disclosure, a first dimension of the first recess is larger than a second dimension of the second recess.
In various embodiments of the instant disclosure, forming the first conducting layer and the second conducting layer are by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) or plasma-enhanced chemical vapor deposition (PECVD).
In various embodiments of the instant disclosure, the method further includes forming a second insulating layer in the first recess and the second recess before forming the first conducting layer in the first recess and the second recess.
In various embodiments of the instant disclosure, forming the first insulating layer and the second insulating layer are by CVD, ALD, PVD or PECVD.
The instant disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a via structure through the substrate. The substrate has an upper surface and a lower surface. The via structure includes a first inner conductor, a first outmost conductor, and a first inner insulator. The first outmost conductor surrounds the first inner conductor and is coaxial with the first inner conductor. The first inner insulator is between the first inner conductor and the first outmost conductor and separates the first inner conductor and the second outmost conductor.
In various embodiments of the instant disclosure, the semiconductor structure further includes a capacitor structure in the substrate. The capacitor structure includes a second inner conductor, a second outmost conductor, and a second inner insulator. The second outmost conductor surrounds the second inner conductor and is coaxial with the second inner conductor. The second inner insulator is between the second inner conductor and the second outmost conductor, wherein the second outmost conductor is isolated from the second inner conductor with the second inner insulator.
In various embodiments of the instant disclosure, the substrate has a thickness and the first inner insulator has a height equal to the thickness.
In various embodiments of the instant disclosure, a first dimension of the via structure is larger than a second dimension of the capacitor structure.
In various embodiments of the instant disclosure, the semiconductor structure further includes an upper metal layer over the upper surface. The upper metal layer is in contact with the second inner conductor and the second outmost conductor.
In various embodiments of the instant disclosure, the semiconductor structure further includes a first outmost insulator separating the first outmost conductor from the substrate and a second outmost insulator separating the second outmost conductor from the substrate.
In various embodiments of the instant disclosure, the capacitor structure penetrates through the substrate.
In various embodiments of the instant disclosure, the semiconductor structure further includes an upper metal layer over the upper surface and a lower metal layer under the lower surface. The upper metal layer is in contact with the second inner conductor and the lower metal layer is in contact with the second outmost conductor.
In various embodiments of the instant disclosure, the semiconductor structure further includes a first outmost insulator separating the first outmost conductor from the substrate and a second outmost insulator separating the second outmost conductor from the substrate.
These and other features, aspects, and advantages of the present invention will become better understood with reference to the following description and appended claims.
It is to be understood that both the foregoing general description and the following detailed description are by way of example, and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:

FIGS. 1A-1J are cross-sectional views of a semiconductor structure at various stages of fabrication, in accordance with various embodiments.

FIGS. 2A and 2B are cross-sectional views of a semiconductor structure at various stages of fabrication, in accordance with various embodiments.

DETAILED DESCRIPTION

Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
The following embodiments are disclosed with accompanying diagrams for detailed description. For illustration clarity, many details of practice are explained in the following descriptions. However, it should be understood that these details of practice do not intend to limit the present invention. That is, these details of practice are not necessary in parts of embodiments of the present invention. Furthermore, for simplifying the drawings, some of the conventional structures and elements are shown with schematic illustrations.
It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
As aforementioned problems, traditional methods of fabricating TSVs and trench-type capacitors simultaneously is complex and costly. Accordingly, the instant disclosure provides a semiconductor structure that includes a capacitor structure and a via structure, and a fabricating method of the semiconductor structure. The fabricating method of the instant disclosure skips the process of using sacrificial layers and the capacitor structure and the via structure can be formed with the same etching processes such that the fabricating method has a simpler process flow and a lower process cost.
FIGS. 1A-1J are cross-sectional views of a semiconductor structure at various stages of fabrication, in accordance with various embodiments. As shown in FIG. 1A, a substrate 110 with an upper surface 112 and a lower surface 114 is received. A first recess 122 extending from the upper surface 112 to the lower surface 114 is formed and the first recess 112 has a first depth d1. A second recess 124 extending from the upper surface 112 to the lower surface 114 is formed and the second recess 124 has a second depth d2 less than the first depth d1.
In various embodiments, the substrate 110 is a silicon wafer or die, which may include passive components such as resistors, capacitors, inductors, and active components, such as N-channel field effect transistors (NFETs), P-channel field effect transistors (PFETs), metal-oxide-semiconductor field effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, high-voltage transistors, and/or high-frequency transistors, other suitable components, and/or combinations thereof. The silicon wafer may include a material of Si, SiGe, SiGeC or SiC, a layered semiconductor such as Si/SiGe or a silicon-on-insulator (SOI). It is further understood that additional features may be added in the substrate 110.
In various embodiments, the first recess 122 and the second recess 124 are formed by laser drilling, dry etching or wet etching. For example, the dry etching includes reactive ion etching (RIE) such as cryogenic deep reactive ion etching or Bosch deep reactive ion etching.
In one embodiment, the first recess 122 and the second recess 124 are formed by the following steps. A photoresist layer (not shown) is formed over the upper surface 112 of the substrate 110, which has a first opening and a second opening smaller than the first opening. Subsequently, the substrate 110 is etched through the first opening to form the first recess 122 and through the second opening to form the second recess 124. Because the first opening is larger than the second opening, a first dimension D1 of the first recess 122 is larger than a second dimension D2 of the second recess 124, as shown in FIG. 1A. For example, the first recess 122 and the second recess 124 are etched out of the substrate 110 by a dry etching such as RIE. Therefore, the depth of the first recess 122 and the second recess 124 can be controlled by RIE lag because the first opening is larger than the second opening.
In various embodiments, a pad layer (not shown) is optionally formed between the photoresist layer and the upper surface 112 of the substrate 110. The pad layer may be made of any suitable materials such as SiO₂, or Si₃N₄.
As shown in FIG. 1B, a second insulating layer 132 is formed in the first recess 122 and the second recess 124. Subsequently, a first conducting layer 142 is formed over the second insulating layer 132 in the first recess 122 and the second recess 124. Therefore, the second insulating layer 132 separates the first conducting layer 142 from the substrate 110 to avoid current leakage and reduce parasitic capacitance. In various embodiments, the second insulating layer 132 may be omitted. In various embodiments, the second insulating layer 132 is formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) or plasma-enhanced chemical vapor deposition (PECVD) and is made of silicon dioxide or silicon nitride. In various embodiments, the first conducting layer 142 is formed by CVD, ALD, PVD or PECVD and is made of any suitable material such as tungsten, aluminum, copper, polysilicon or an alloy.
As shown in FIG. 1C, a portion of the second insulating layer 132 and a portion of the first conducting layer 142 are removed by polishing such as chemical-mechanical polishing (CMP) to form a first outmost insulator 132 a and a first outmost conductor 142 a in the first recess 122 and to form a second outmost insulator 132 b and a second outmost conductor 142 b in the second recess 124.
As shown in FIG. 1D, a first insulating layer 134 is formed over the first outmost insulator 132 a, the first outmost conductor 142 a, the second outmost insulator 132 b, the second outmost conductor 142 b and the substrate 110. The first insulating layer 134 is then polished to form a first inner insulator 134 a in the first recess 122 and a second inner insulator 134 b in the second recess 124 as shown in FIG. 1E. Subsequently, a second conducting layer (not shown) is formed over the first inner insulator 134 a and second inner insulator 134 b and the second conducting layer is then polished to form a first inner conductor 144 a in the first recess 122 and a second inner conductor 144 b in the second recess 124. Therefore, the first inner conductor 144 a is isolated from the first outmost conductor 142 a with the first inner insulator 134 a and the second inner conductor 144 b is isolated from the second outmost conductor 142 b with the second inner insulator 134 b.
More specifically, the first outmost insulator 132 a surrounds the first outmost conductor 142 a, which surrounds the first inner insulator 134 a. Further, the first inner insulator 134 a surrounds the first inner conductor 144 a. Accordingly, the first inner conductor 144 a, the first inner insulator 134 a, the first outmost conductor 142 a and the first outmost insulator 132 a are coaxial. Similarly, the second outmost insulator 132 b surrounds the second outmost conductor 142 b, which surrounds the second inner insulator 134 b. Further, the second inner insulator 134 b surrounds the second inner conductor 144 b. Accordingly, the second inner conductor 144 b, the second inner insulator 134 b, the second outmost conductor 142 b and the second outmost insulator 132 b are coaxial as well.
In various embodiments, the first insulating layer 134 is formed by CVD, ALD, PVD or PECVD and is made of silicon dioxide or silicon nitride. In various embodiments, the second conducting layer is formed by CVD, ALD, PVD or PECVD and is made of any suitable material such as tungsten, aluminum, copper, polysilicon or an alloy.
As shown in FIG. 1F, an upper insulating layer 150 is formed over the upper surface 112 of the substrate 110. Subsequently, the upper insulating layer 150 is patterned to form some openings and the openings are then filled with an upper metal layer 152 as shown in FIG. 1G. It is worth noting that the upper metal layer 152 is in contact with the first outmost insulator 132 a, the first outmost conductor 142 a, the first inner insulator 134 a, the first inner conductor 144 a and the second inner conductor 144 b.
As shown in FIG. 1H, the substrate 110 is thinned from the lower surface 114 to expose a lower surface 116 of the substrate 110, the first inner conductor 144 a, the first inner insulator 134 a, the first outmost conductor 142 a, the first outmost insulator 132 a, the second outmost conductor 142 b and the second outmost insulator 132 b to form a via structure 146 a and a capacitor structure 146 b. Specifically, the via structure 146 a includes the first inner conductor 144 a, the first inner insulator 134 a, the first outmost conductor 142 a and the first outmost insulator 132 a and has the first dimension D1. The capacitor structure 146 b includes the second inner conductor 144 b, the second inner insulator 134 b, the second outmost conductor 142 b and the second outmost insulator 132 b and has the second dimension D2 smaller than the first dimension D1. Both the via structure 146 a and the capacitor structure 146 b extend through the substrate 110. It is worth noting that the first inner insulator 134 a separates the first outmost conductor 142 a and the first inner conductor 144 a and has a height equal to a thickness T1 of the substrate 110, as shown in FIG. 1H. Further, the first inner insulator 134 a is coplanar with the upper surface 112 and the lower surface 116 of the substrate 110. In the capacitor structure 146 b, the second inner conductor 144 b is isolated from the second outmost conductor 142 b.
In other words, the substrate 110 is thinned from the lower surface 114 to expose the first inner conductor 144 a and the second outmost conductor 142 b, namely, the substrate 110 is thinned from the lower surface 114 to expose the second conducting layer in the first recess 122 and the first conducting layer 142 in the second recess 124.
In various embodiments, the substrate 110 is thinned from the lower surface 114 by backside grinding, chemical-mechanical polishing or blanket etching process.
As shown in FIG. 1I, a lower insulating layer 160 is formed under the lower surface 116 of the substrate 110. Subsequently, the lower insulating layer 160 is patterned to form some openings and the openings are then filled with a lower metal layer 162 to form a semiconductor structure 100 as shown in FIG. 1J. It is worth noting that the lower metal layer 162 is in contact with the first outmost insulator 132 a, the first outmost conductor 142 a, the first inner insulator 134 a, the first inner conductor 144 a, the second outmost insulator 132 b and the second outmost conductor 142 b. Therefore, the upper metal layer 152 can electrically connect with the lower metal layer 162 through the via structure 146 a, which allows current to flow through the substrate 110.
FIGS. 2A and 2B are cross-sectional views of a semiconductor structure 200 at various stages of fabrication, in accordance with various embodiments. As shown in FIG. 2A, a substrate 210 with an upper surface 212 and a lower surface 214 is received. A first outmost insulator 232 a surrounds a first outmost conductor 242 a, which surrounds a first inner insulator 234 a. Further, the first inner insulator 234 a surrounds a first inner conductor 244 a. Accordingly, the first inner conductor 244 a, the first inner insulator 234 a, the first outmost conductor 242 a and the first outmost insulator 232 a are coaxial. Similarly, a second outmost insulator 232 b surrounds a second outmost conductor 242 b, which surrounds a second inner insulator 234 b. Further, the second inner insulator 234 b surrounds a second inner conductor 244 b. Accordingly, the second inner conductor 244 b, the second inner insulator 234 b, the second outmost conductor 242 b and the second outmost insulator 232 b are coaxial as well. The fabrication process of above configuration shown in FIG. 2A is the same as shown in FIGS. 1A-1E.
Further, after an upper insulating layer 250 is formed over the upper surface 212 of the substrate 210, the upper insulating layer 250 is patterned to form some openings and the openings are then filled with an upper metal layer 252 as shown in FIG. 2A. It is worth noting that the upper metal layer 252 is in contact with the first outmost insulator 232 a, the first outmost conductor 242 a, the first inner insulator 234 a, the first inner conductor 244 a, the second inner conductor 244 b and the second outmost conductor 242 b, which is isolated from the second inner conductor 244 b with the second inner insulator 234 b.
As shown in FIG. 2B, the substrate 210 is thinned from the lower surface 214 to expose a lower surface 216 of the substrate 210, the first inner conductor 244 a, the first inner insulator 234 a, the first outmost conductor 242 a and the first outmost insulator 232 a to form a via structure 246 a and a capacitor structure 246 b. In other words, thinning the substrate 210 from the lower surface 214 stops before exposing the second inner conductor 244 b. More specifically, the via structure 246 a includes the first inner conductor 244 a, the first inner insulator 234 a, the first outmost conductor 242 a and the first outmost insulator 232 a and has the first dimension D1. Only the via structure 246 a penetrates through the substrate 210. It is worth noting that the first inner insulator 234 a separates the first outmost conductor 242 a and the first inner conductor 244 a and has a height equal to a thickness T2 of the substrate 210 as shown in FIG. 2B. Further, the first inner insulator 234 a is coplanar with the upper surface 212 and the lower surface 216 of the substrate 210.
Further, the capacitor structure 246 b includes the second inner conductor 244 b, the second inner insulator 234 b, the second outmost conductor 242 b and the second outmost insulator 232 b and has the second dimension D2 smaller than the first dimension D1. In the capacitor structure 246 b, the second inner conductor 244 b is isolated from the second outmost conductor 242 b.
Furthermore, a lower insulating layer (not shown) may be formed under the lower surface 216 and then patterned to form some openings. The openings are continuously filled with a lower metal layer (not shown). Therefore, the upper metal layer 252 can electrically connect with the lower metal layer through the via structure 246 a which allows current to flow through the substrate 210.
Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structures of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the appended claims.

Claims

1. A semiconductor device, comprising:

a via structure extending through a material, the via structure comprising:

a first inner conductor;

a first outmost conductor surrounding the first inner conductor and coaxial with the first inner conductor; and

a first inner insulator between the first inner conductor and the first outmost conductor, the first inner insulator.

2. The semiconductor device of claim 1, further comprising a capacitor structure in the material, the capacitor structure comprising:

a second inner conductor;

a second outmost conductor surrounding the second inner conductor and coaxial with the second inner conductor; and

a second inner insulator between the second inner conductor and the second outmost conductor, wherein the second outmost conductor is isolated from the second inner conductor by the second inner insulator.

3. The semiconductor device of claim 2, wherein the material has a thickness and the first inner insulator has a height equal to the thickness.

4. The semiconductor device of claim 2, wherein a first dimension of the via structure is larger than a second dimension of the capacitor structure.

5. The semiconductor device of claim 2, further comprising an upper metal material over an upper surface of the material, the upper metal material in contact with the second inner conductor and the second outmost conductor.

6. The semiconductor device of claim 2, further comprising a first outmost insulator separating the first outmost conductor from the material and a second outmost insulator separating the second outmost conductor from the material.

7. The semiconductor device of claim 2, wherein the capacitor structure penetrates through the material.

8. The semiconductor device of claim 7, further comprising an upper metal material over the upper surface of the material and a lower metal material under the lower surface of the material, the upper metal material in contact with the second inner conductor and the lower metal material in contact with the second outmost conductor.

9. The semiconductor device of claim 7, further comprising a first outmost insulator separating the first outmost conductor from the material and a second outmost insulator separating the second outmost conductor from the material.

10. A semiconductor device, comprising:

a via structure comprising a first inner conductive material, a first inner insulative material coaxial to the first inner conductive material, and a first outer conductive material coaxial to the first inner insulative material; and

a capacitor structure comprising a second inner conductive material, a second inner insulative material coaxial to the second inner conductive material, and a second outer conductive material coaxial to the second inner conductive material.

11. The semiconductor device of claim 10, further comprising a metal material adjacent the via structure and the capacitor structure, the metal material contacting the first inner conductive material, the first outer conductive material, the first inner insulative material, and the second outer conductive material.

12. The semiconductor device of claim 11, further comprising a second outer insulative material coaxial to the second outer conductive material, the second outer insulative material and the second outer conductive material contacting the metal material and the second inner conductive material isolated from the metal material.

13. The semiconductor device of claim 10, further comprising another metal material adjacent the via structure and the capacitor structure, the another metal material contacting the first inner conductive material and the second inner conductive material.

14. The semiconductor device of claim 13, wherein the first inner conductive material, the first outer conductive material, and the second inner conductive material contact the another metal material.

15. The semiconductor device of claim 13, wherein the another metal material contacts the second inner conductive material without contacting the second outer conductive material.

16. The semiconductor device of claim 13, wherein discrete portions of the another metal material contact the second inner conductive material and the second outer conductive material.

17. A semiconductor device, comprising:

a via structure and a capacitor structure adjacent to the via structure;

an upper metal material electrically connected to a first inner conductive material of the via structure, to a first outer conductive material of the via structure, and to a second inner conductive material of the capacitor structure; and

a lower metal material electrically connected to the first inner conductive material of the via structure, to the first outer conductive material of the via structure, and to a second outer conductive material of the capacitor structure.

18. The semiconductor device of claim 17, wherein the second inner conductive material of the capacitor structure is isolated from the lower metal material.

19. The semiconductor device of claim 17, wherein the first inner conductive material of the via structure and the second inner conductive material of the capacitor structure comprise the same material.

20. The semiconductor device of claim 17, wherein the first outer conductive material of the via structure and the second outer conductive material of the capacitor structure comprise the same material.

21. The semiconductor device of claim 17, wherein a width of the via structure is larger than a width of the capacitor structure.

22. The semiconductor device of claim 17, wherein a bottom surface of the first inner conductive material is substantially coplanar with a bottom surface of the first outer conductive material.

23. The semiconductor device of claim 17, wherein a bottom surface of the second inner conductive material is not substantially coplanar with a bottom surface of the second outer conductive material.

24. The semiconductor device of claim 17, wherein a bottom surface of the first inner conductive material is not substantially coplanar with a bottom surface of the second inner conductive material.