CN103346148B - A kind of Vertical-type capacitor structure and preparation method thereof - Google Patents
A kind of Vertical-type capacitor structure and preparation method thereof Download PDFInfo
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- CN103346148B CN103346148B CN201310280532.0A CN201310280532A CN103346148B CN 103346148 B CN103346148 B CN 103346148B CN 201310280532 A CN201310280532 A CN 201310280532A CN 103346148 B CN103346148 B CN 103346148B
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Abstract
The present invention relates to a kind of Vertical-type capacitor structure and preparation method thereof, belong to microelectronics passive device technical field.Its structure specifically comprises: the zanjon structure in wafer substrate, the insulating barrier being deposited on zanjon madial wall successively and conductive layer and the dielectric layer be filled between conductive layer.Insulating barrier, conductive layer, dielectric layer and zanjon are contour.Adopt the principle based on expanded capacitor area on vertical substrates direction, utilize the battery lead plate area of vertical direction, adopt sputtering, the techniques such as plating make metal electrode board, and pole plate adopts the low-resistivity materials such as metal.In conjunction with silicon through hole technology, realize the vertical type electric capacity of large depth-to-width ratio; In conjunction with substrate back thinning technique, this upright capacitance structure runs through substrate, can be used as the hf channel between multilayer chiop; Greatly can save chip area, improve integrated circuit integrated level.
Description
Technical field
The present invention relates to a kind of Vertical-type capacitor structure and preparation method thereof, belong to microelectronics passive device technical field.
Background technology
Electric capacity is the passive device with stored charge function, has the electric functions such as decoupling, switching noise suppression, bypass filtering, ac/dc conversion and signal isolation.No matter all there is important function in discrete device circuit or in integrated circuit.The excursion of capacitance is usually between picofarad (pF) to microfarad (μ F) magnitude.
In the integrated circuit development course of more than 40 year, the characteristic size of transistor follows Moore's Law and constantly reduces, and realizes integrate circuit function and performance improves constantly.But the size of electric capacity, is limited to dielectric material, cannot effectively reduce, at present much larger than the size of transistor.In integrated circuits, especially analogue layout, the area of single picofarad magnitude electric capacity is up to ~ 1000 μm
2, considerably increase the gross area of chip, thus, significantly increase the manufacturing cost of chip.Although have the electric capacity saving area, such as high-k electric capacity, the electric capacity of this structure often has very high loss and very poor voltage coefficient, is difficult to the demand meeting high performance analog circuits.On the other hand, capacitance is difficult to reach microfarad magnitude, and researcher has to adopt other method to go to make up this defect.Visible, in the development in future, still need the electric capacity of design high density, high-performance, low cost to meet the need of market.
CMOS integrated circuit technology now adopts thin film technique to manufacture electric capacity.In order to obtain higher capacitance density, the general film adopting high dielectric constant, as BaTiO
3and PbZr
xti
1-xo
3deng as dielectric.Because the puncture voltage of electric capacity and the dielectric constant of dielectric are inversely proportional to, therefore, the electric capacity adopting this scheme to obtain has lower puncture voltage; Meanwhile, because dielectric material has higher temperature control, therefore, the electric capacity adopting the program to obtain also has higher temperature control.While increasing capacitance density, how to ensure that the electric property of device is a hot issue of research.
Vertical type electric capacity is a kind of feasible method realizing high density capacitor.By using high density zanjon structure, effectively can increase capacity area, thus improve capacitance density, in conjunction with wafer thinning technique, can be used for the hf channel connecting upper and lower chip in three-dimensional integration technology.Existing groove capacitor structure can not be called vertical type electric capacity completely, although expand capacity area in vertical substrates method, but its power-on and power-off pole plate is still similar to flush system electric capacity, and battery lead plate packing material mostly is polysilicon, resistance is comparatively large, can not charge to flute surfaces fully.On the other hand, existing zanjon capacitance structure is used for memory, is not yet applied to the hf channel in three dimensional integrated circuits between multilayer chiop.
Summary of the invention
The object of the invention is the capacitance density for improving integrated circuit and integrated level, proposing a kind of Vertical-type capacitor structure and preparation method thereof.
Vertical type electric capacity of the present invention is based on the thought of expanded capacitor area on vertical substrates direction, be different from existing channel capacitor battery lead plate material and preparation method thereof, utilize the battery lead plate area of vertical direction, adopt sputtering, the techniques such as plating make metal electrode board, and pole plate adopts the low-resistivity materials such as metal.In conjunction with silicon through hole technology, realize the vertical type electric capacity of large depth-to-width ratio; In conjunction with substrate back thinning technique, this upright capacitance structure runs through substrate, can be used as the hf channel between multilayer chiop.
A kind of vertical type electric capacity, concrete structure comprises: the zanjon structure in wafer substrate, the insulating barrier being deposited on zanjon madial wall successively and conductive layer and the dielectric layer be filled between conductive layer.Insulating barrier, conductive layer, dielectric layer and zanjon are contour.
Described vertical type electric capacity is vertically embedded in wafer substrate, from top to bottom through wafer substrate.
Described zanjon structure is annular.Described annular comprises back-shaped ring, circular rings and polygon ring.
Described zanjon structure can also be two parallel rectangular strips, or the polygon bar that two parallel.
Described wafer substrate material is the one in Silicon Wafer, glass wafer, sapphire wafer, GaAs, organic wafer.
The material of described insulating barrier is the one in silicon dioxide, aluminium oxide, silicon oxynitride, silicon nitride, high molecular polymer.
Described conductive is the one in copper, aluminium, iron, nickel, titanium, tungsten, platinum, gold, silver, titanium, palladium, tantalum, polysilicon, titanium silicide, tungsten silicide, molybdenum silicide, platinum silicide and cobalt silicide.
Described dielectric layer material is the one of silicon nitride, silicon dioxide, tantalum oxide, titanium oxide, zinc oxide, lead zirconate titanate, barium strontium, high molecular polymer.
Described high molecular polymer is the one in benzocyclobutene, polyimides, polyethylene, dimethyl silicone polymer, polymethyl methacrylate, epoxy resin.
Height and the interior side-wall surface thereof of the size of capacitance and the dielectric material of dielectric layer and thickness thereof, zanjon are long-pending relevant, highly higher, and interior side-wall surface is amassed larger, and capacitance is larger.The thickness of dielectric medium is less, and dielectric constant is larger, and capacitance is larger.
A manufacture method for the back-shaped capacitance structure of vertical type, comprises the steps:
Step 1, adopts deep reaction ion etching technology, wafer substrate makes the zanjon structure perpendicular to substrate floor;
Step 2, at zanjon structure madial wall and wafer substrate upper surface deposition insulating layer;
Step 3, on the insulating layer deposit conductive layer;
Step 4, filled dielectric material in the zanjon that conductive layer is formed, forms dielectric layer;
Step 5, removes dielectric layer and the conductive layer of wafer substrate upper surface;
Step 6, carries out reduction processing at wafer substrate lower surface, until expose conductive layer.
The manufacture method of another kind of vertical type bar shaped capacitance structure, comprises the steps:
Step 1, wafer substrate makes two bar shaped zanjon structures side by side;
Step 2, at described bar shaped zanjon structure madial wall and wafer substrate upper surface deposition insulating layer;
Step 3, fills up electric conducting material in the zanjon between insulating barrier, forms two strips of conductive layers;
Step 4, by etch tool, removes the wafer substrate between described two strips of conductive layers and insulating barrier, forms upright, contour with a conductive layer zanjon structure;
Step 5, filled dielectric material in the zanjon structure that step 4 is formed, forms dielectric layer;
Step 6, carries out reduction processing at wafer substrate back, until expose conductive layer.
Beneficial effect
The present invention replaces the capacitor arrangement in traditional integrated circuit technique, vertical type electric capacity is changed into by flush system electric capacity, the capacitance density that easy realization is large, and on the basis not changing original CMOS technology, electric capacity domain can be removed during design circuit, only reserve corresponding capacitive interface, by the wafer of bonding containing upright capacitance structure, reach the object connecting electric capacity, by three-dimensional integration technology, electric capacity is made in above or below integrated circuit, make capacitance structure independent, greatly can save chip area, perpendicular interconnection technical compatibility in its manufacture craft and three dimensional integrated circuits, same layer can be produced on through-silicon via structure, can greatly improve integrated circuit integrated level.
Accompanying drawing explanation
Fig. 1 is the back-shaped capacitance structure schematic three dimensional views of vertical type that the embodiment of the present invention 1 provides.In figure, S1 is wafer substrate, and S2 is back-shaped zanjon structure, and 101 is insulating barrier, and 102 is conductive layer, and 103 is dielectric layer;
Fig. 2 is the schematic diagram forming back-shaped zanjon structure in wafer substrate that the embodiment of the present invention 1 provides; Wherein (a) is generalized section, and (b) is schematic top plan view;
Fig. 3 is the formation insulating barrier that the embodiment of the present invention 1 provides, the schematic diagram of conductive layer and dielectric layer;
Fig. 4 is the schematic diagram after the removal wafer substrate surface dielectric layer that provides of the embodiment of the present invention 1 and conductive layer, and wherein (a) is generalized section, and (b) is schematic top plan view;
Fig. 5 be the embodiment of the present invention 1 provide carry out wafer substrate back thinning after schematic diagram;
Fig. 6 is the schematic diagram of two bar shaped zanjon structures that the embodiment of the present invention 2 provides, and in figure, S21 is wafer substrate, and S22 is two parallel striped zanjon structures;
Fig. 7 is the schematic diagram of the conductive layer of deposition insulating layer in zanjon structure that the embodiment of the present invention 2 provides; In figure, 201 is upper surface insulating barrier, and 202 is conductive layer;
Fig. 8 is the schematic diagram forming zanjon between two conductive layers that the embodiment of the present invention 2 provides; In figure, S23 is the zanjon structure between two conductive layers.
Fig. 9 is the schematic diagram after the filling dielectric layer that provides of the embodiment of the present invention 2; In figure, 203 is dielectric layer;
Figure 10 be the embodiment of the present invention 2 provide to wafer substrate carry out back thinning after schematic diagram;
Figure 11 is the interdigital parallel-connection structure schematic diagram of vertical type bar shaped electric capacity that the embodiment of the present invention 3 provides, and wherein S31 is wafer substrate, and S32 is interdigitated electrodes, and 301 is insulating barrier, and 302 is conductive layer, and 303 is dielectric layer.
Embodiment
The present invention discloses a kind of Vertical-type capacitor structure, and as shown in Figure 1, vertical type electric capacity comprises: wafer substrate, back-shaped zanjon structure, at the insulating barrier of back-shaped side wall of deep channel and conductive layer and the dielectric layer between conductive layer.Compared with flush system electric capacity conventional in current integrated circuit, the advantage of vertical type electric capacity disclosed in this invention is that to occupy chip area little, and has high capacitance density.Below in conjunction with specific embodiment and accompanying drawing, the present invention is further described in detail, disclose two kinds of specific embodiments.
Specific embodiment 1: back-shaped capacitance structure of vertical type and preparation method thereof.
As shown in Figure 2, adopt deep reaction ion etching technology on wafer substrate S1, etch back-shaped zanjon S2.The width of described zanjon is 5-10 micron; Zanjon length does not strictly limit, and can be 5-200 micron; The zanjon degree of depth is less than the thickness of wafer substrate, can be 60-500 micron; The shape of zanjon is the one in back-shaped, circular rings or polygon ring.
As shown in Figure 3, using plasma strengthens chemical vapor deposition at zanjon madial wall deposition insulating layer 101 silicon dioxide; Utilize the young crystal layer of sputtering technology cement copper, and increase the thickness formation conductive layer 102 of layers of copper by plating, as inside and outside battery lead plate.The thickness of the young crystal layer of copper does not strictly limit, and can be 50nm-300nm; The thickness of conductive layer, can be 1 μm-5 μm.Finally adopt spray, spin coating, plasma enhanced CVD or vacuum suction technology fill one in silicon nitride, silicon dioxide, tantalum oxide, titanium oxide, zinc oxide, lead zirconate titanate, barium strontium in zanjon, form dielectric layer 103.
As shown in Figure 4, adopt chemical Mechanical Polishing Technique to remove dielectric layer 103 and the conductive layer 102 of wafer substrate S1 surface deposition successively, retain the insulating barrier 101 on wafer substrate S1 surface.
As shown in Figure 5, rough lapping technology is first adopted to remove most of backing substrate, until backing substrate is close to bottom zanjon; Then adopt chemical Mechanical Polishing Technique to carry out planarizing process to backing substrate, until expose zanjon, and the conductive layer ground off bottom zanjon connects, and forms independently inside and outside battery lead plate.
Specific embodiment 2: vertical type bar shaped capacitance structure and preparation method thereof.
As shown in Figure 6, the present embodiment adopts manufacture method identical in embodiment 1, makes two bar shaped zanjon structure S22 side by side.Under existing technique, the making scope of zanjon length is 5-200 micron; In the present embodiment, the width of zanjon is 3-5 micron; The zanjon degree of depth is less than the thickness of wafer substrate S21, can be 60-500 micron; Spacing between two zanjons is 2-5 micron; The shape of zanjon is rectangle or serpentine polygon.
As shown in Figure 7, the present embodiment adopts manufacture method identical in embodiment 1, deposition insulating layer 201, and in zanjon S21 deposit conductive layer 202, until fill up zanjon.
As shown in Figure 8, adopt deep reaction ion etching technology to etch the silicon between conductive layer 202, form bar shaped zanjon structure S23.
As shown in Figure 9, using plasma enhancing chemical vapor deposition or vacuum suction technology fill the one in silicon nitride, silicon dioxide, tantalum oxide, titanium oxide, zinc oxide, lead zirconate titanate, barium strontium in zanjon S23, form dielectric layer 203.
As shown in Figure 10, the present embodiment adopts manufacture method identical in embodiment 1, and thinned wafer substrate back, until expose conductive layer 202.
Specific embodiment 3: the interdigital parallel-connection structure of vertical type bar shaped electric capacity.
As shown in figure 11, the present embodiment adopts the manufacture method in embodiment 2, and same wafer substrate makes three vertical type bar shaped electric capacity, wherein 301 is insulating barrier, and 302 is conductive layer, and 303 is dielectric layer, then utilize surperficial interconnection process to form interdigital electrode S32, form shunt capacitance structure.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. a manufacture method for the back-shaped capacitance structure of vertical type, comprises the steps:
Step 1, adopts deep reaction ion etching technology, wafer substrate makes the zanjon structure perpendicular to substrate floor;
Step 2, at zanjon structure madial wall and wafer substrate upper surface deposition insulating layer;
Step 3, on the insulating layer deposit conductive layer;
Step 4, filled dielectric material in the zanjon that conductive layer is formed, forms dielectric layer;
Step 5, removes dielectric layer and the conductive layer of wafer substrate upper surface;
Step 6, carries out reduction processing at wafer substrate lower surface, until expose conductive layer.
2. the manufacture method of the back-shaped capacitance structure of a kind of vertical type according to claim 1, is characterized in that, described zanjon shape, can also be circular rings or polygon ring.
3. a manufacture method for vertical type bar shaped capacitance structure, comprises the steps:
Step 1, wafer substrate makes two bar shaped zanjon structures side by side;
Step 2, at described bar shaped zanjon structure madial wall and wafer substrate upper surface deposition insulating layer;
Step 3, fills up electric conducting material in the zanjon between insulating barrier, forms two strips of conductive layers;
Step 4, by etch tool, removes the wafer substrate between described two strips of conductive layers and insulating barrier, forms upright, contour with a conductive layer zanjon structure;
Step 5, filled dielectric material in the zanjon structure that step 4 is formed, forms dielectric layer;
Step 6, carries out reduction processing at wafer substrate back, until expose conductive layer.
4. the manufacture method of a kind of vertical type bar shaped capacitance structure according to claim 3, it is characterized in that, described bar shaped comprises rectangle or polygon.
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| US10121849B2 (en) | 2015-11-16 | 2018-11-06 | Micron Technology, Inc. | Methods of fabricating a semiconductor structure |
| US10068184B1 (en) * | 2017-10-27 | 2018-09-04 | International Business Machines Corporation | Vertical superconducting capacitors for transmon qubits |
| CN108074739B (en) * | 2017-12-28 | 2023-07-07 | 山东芯诺电子科技股份有限公司 | Vertical patch capacitor and manufacturing process thereof |
| CN108766899A (en) * | 2018-05-30 | 2018-11-06 | 上海华力集成电路制造有限公司 | The manufacturing method and its structure of integrated circuit |
| WO2020029177A1 (en) * | 2018-08-09 | 2020-02-13 | 深圳市为通博科技有限责任公司 | Capacitor and manufacturing method for same |
| US11329125B2 (en) * | 2018-09-21 | 2022-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit including trench capacitor |
| CN109461737B (en) * | 2018-11-12 | 2020-09-29 | 长江存储科技有限责任公司 | Semiconductor device and manufacturing method thereof |
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| CN101114616A (en) * | 2006-07-27 | 2008-01-30 | 联华电子股份有限公司 | Capacitor contact structure and technique for dynamic random access memory |
| CN101789390A (en) * | 2009-01-23 | 2010-07-28 | 财团法人工业技术研究院 | Manufacturing method of silicon through hole and silicon through hole structure |
| CN102386240A (en) * | 2010-09-01 | 2012-03-21 | 台湾积体电路制造股份有限公司 | Cylindrical embedded capacitors |
| CN102568817A (en) * | 2012-03-01 | 2012-07-11 | 中北大学 | MEMS (Micro Electro Mechanical System) capacitor based on three-dimensional silicon micro structure and manufacturing method thereof |
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| CN101114616A (en) * | 2006-07-27 | 2008-01-30 | 联华电子股份有限公司 | Capacitor contact structure and technique for dynamic random access memory |
| CN101789390A (en) * | 2009-01-23 | 2010-07-28 | 财团法人工业技术研究院 | Manufacturing method of silicon through hole and silicon through hole structure |
| CN102386240A (en) * | 2010-09-01 | 2012-03-21 | 台湾积体电路制造股份有限公司 | Cylindrical embedded capacitors |
| CN102568817A (en) * | 2012-03-01 | 2012-07-11 | 中北大学 | MEMS (Micro Electro Mechanical System) capacitor based on three-dimensional silicon micro structure and manufacturing method thereof |
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