CN102592968B - Method for producing multilayer metal-silicon nitride-metal capacitor - Google Patents
Method for producing multilayer metal-silicon nitride-metal capacitor Download PDFInfo
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Abstract
The invention provides a method for producing a multilayer metal-silicon nitride-metal capacitor, which includes the following steps: 1) using a plasma enhanced chemical vapor deposition (PECVD) method to deposit a silicon nitride thin film with a high k value on a silicon chip substrate; 2) removing silicon nitride in a non-metal-oxide-metal area through photoetching and etching; 3) depositing a dielectric layer with a low k value; 4) removing redundant silicon nitride through chemical mechanical polishing, and forming a mixing layer of low-k-value dielectric and silicon nitride; 5) completing photoetching and etching to form a metallic channel in the low-k-value dielectric and the silicon nitride; 6) forming metal fillers of a lead and a metal-oxide-metal (MOM) capacitor after deposition and chemical mechanical polishing of a metal layer are completed; and 7) repeating Step 1) to Step 6) to form multilayer MOM capacitor. The method for producing the multilayer metal-silicon nitride-metal capacitor can effectively improve the capacitance of the interlayer capacitor, can also effectively improve various electric characteristics of the MOM capacitor such as breakdown voltage, leakage current and the like, can effectively improve electric uniformity among various apparatuses, and is very practical.
Description
Technical field
The present invention relates to the manufacture method of a kind of electric capacity in semiconductor integrated circuit manufacture, particularly a kind of manufacture method of Multilayer MOM capacitor.
Background technology
Along with the trend CMOS (Complementary Metal Oxide Semiconductor) of standard (CMOS) technology being applied in simulation and radio frequency CMOS (Complementary Metal Oxide Semiconductor) (RFCMOS) integrated circuit fields, increasing passive component arises at the historic moment.Capacitor is the important composition unit in integrated circuit, is widely used in memory, microwave, and radio frequency, smart card, in the chips such as high pressure and filtering.The capacitor constructions widely adopting in chip is the metal-insulator-metal type (MIM) that is parallel to silicon chip substrate.Wherein metal be manufacture craft easily with metal interconnected technique copper, the aluminium etc. of compatibility mutually, insulator is the dielectric substance of the high-k such as silicon nitride, silica (k).The performance of improving high-k dielectric material is one of main method improving capacitor performance.
Owing to utilizing the assembly of CMOS (Complementary Metal Oxide Semiconductor) fabrication techniques there is good usefulness and easily make, so metal-insulating barrier-metal (Metal-Insulator-Metal, MIM) electric capacity is widely used in the design of semiconductor element.Because this kind of metal capacitor has lower resistance value (resistance) and less parasitic capacitance (parasitic capacitance), and the problem that does not have depletion layer induced voltage (induced voltage) to be offset, therefore the current primary structures of MIM structure as metal capacitor that adopt more, the emphasis direction of research at present especially of the MIM capacitor especially with low-resistance copper electrode.
Chinese patent CN101577227A has introduced a kind of method of improving aluminium-silicon nitride-tantalum compound capacitor performance.Plasma enhanced chemical vapor deposition method (PECVD, Plasma Enhanced Chemical Vapor Deposition) is because of the low thin film deposition being widely used in metal interconnected technique of its depositing temperature.The interior residual a large amount of si-h bond (Si-H) of silicon nitride film that utilizes PECVD method to make, make to exist in it more electric charge, this causes the uniformity of this silicon nitride film aspect electrical thickness poor, and the MIM capacitor of utilizing this silicon nitride film to make also can be corresponding poor aspect each electrical characteristics such as puncture voltage, leakage current.Process this silicon nitride film by oxygen-containing gas, can effectively reduce residual si-h bond in silicon nitride film, thereby effectively improved the performance of capacitor.
Metal-insulating barrier-metal (Metal-Insulator-Metal, MIM) capacitor is to increase one of capacitor arrangement of capacitance, it is the most simply constructed is that the metallic plate of horizontal direction parallel is built up to several layers, be interval between each metal level with dielectric layer, two metallic plates that connect via dielectric layer become the two poles of the earth of capacitor.By simple the formation of metallic plate vertical stacking, compared with the situation of two conductive surfaces is only provided, can provide larger unit-area capacitance value.Although but formation is simple, the MIM electric capacity that forms multilayer usually needs a lot of extra processing steps, and has increased the burden in many manufacturing costs.
Metal-oxide-metal (Metal-Oxide-Metal, MOM) capacitor be can increase capacitance another capacitor arrangement, it comprises the tabular thing of conductivity conventionally, its two poles of the earth that are capacitor for dielectric medium be split to form.The benefit of MOM capacitor is that it can complete by existing technique.For example, the dual-damascene technics that is used for the metallization process of copper interconnects is filled out the interlayer hole (via) of copper and the stacked structure of groove in can be used to form, wherein oxide dielectric medium is separated fills out interlayer hole and the groove of copper in two or more, forms a capacitor.Compared to traditional capacitor, MOM capacitor can provide larger unit-area capacitance value effectively.
Along with the minimizing of size, and the demand of performance to large electric capacity, how under limited area, obtaining highdensity electric capacity becomes a problem having a great attraction.Along with the continuous progress of semiconductor integrated circuit manufacturing technology, performance is also accompanied by device miniaturization, microminiaturized process when constantly lifting.More and more advanced processing procedure, requires in as far as possible little region, to realize device as much as possible, obtains high as far as possible performance.A kind of method that realizes larger electric capacity in less chip area perpendicular to the metal-oxide-metal (MOM) of silicon chip substrate.Oxide wherein is not only confined to silica, comprises in actual applications the dielectric substance of the high-ks such as silicon nitride (k).The compatibility of MOM capacitor fabrication technique and metal interconnected technique is relatively good, and outer company of capacitor two-stage can synchronously realize with metal interconnected technique.
Than MIM capacitor, MOM can improve the electric capacity in unit are.The performance of improving high-k dielectric material also can further improve the performance of MOM capacitor.Thereby meet the requirement of constantly microminiaturized chip to high performance capacitors.
Chinese patent CN200810186404 provides a kind of metal-oxide-metal capacitor construction.This capacitance structure comprises: a dielectric layer, one first net-shaped metal layer and one second net-shaped metal layer.First and second net-shaped metal layer is embedded in dielectric layer, and the second net-shaped metal layer stacked in parallel is in the first net-shaped metal layer top.Each net-shaped metal layer has the multiple openings that are arranged in an array.Net intersection point in the first net-shaped metal layer is the opening in corresponding the second net-shaped metal layer respectively, and net intersection point in the second net-shaped metal layer corresponds respectively to the opening in the first net-shaped metal layer.Metal-oxide-metal capacitor construction of the present invention, can effectively improve processing procedure character gradient and the linearity, and further promotes the usefulness of integrated circuit.
Chinese patent CN200610094199 provides a kind of capacitor arrangement and manufacture method thereof of integrated circuit, comprises: one first plate object layer, the first plate object that comprises a series of mutual intersections (interdigitated); One first dielectric layer, is covered on this first plate object layer; One first extended layer, on this first dielectric layer, comprises a series of cross one another the first extension boards, and each this first extension board is disposed at respectively each this first plate object top; A series of the first conductting layer, is connected on each this first extension board; And one second plate object layer, comprising a series of cross one another the second plate objects, each this second plate object is connected on each this first conductting layer; The polarity of the first extension board, the first conductting layer and the second plate object being wherein connected and the polarity inequality of corresponding the first plate object.The present invention can be effectively in conjunction with MOM capacitor and MIM capacitor, and also can improve the impact that alignment error causes.
Chinese patent CN200610071511 relates to a kind of capacitance structure, and it comprises a substrate, a first metal layer, an etch stop layer, an articulamentum, one second metal level and an insulating barrier.The first metal layer is disposed in substrate.Etch stop layer is disposed in substrate, and wherein etch stop layer has an opening, and this opening exposes part the first metal layer.Articulamentum is disposed at the surface of opening and partially-etched stop layer.The second metal level is disposed on articulamentum.Insulating barrier is disposed between the second metal level and articulamentum.
In order effectively to improve the electric capacity of layer inner capacitor, improve each electrical characteristics such as puncture voltage, leakage current of metal-silicon nitride-metal (MOM) capacitor, and electricity uniformity between each device.The invention provides a kind of manufacture method of Multilayer MOM capacitor, this method is particularly suitable for being manufactured with the device of individual layer MOM capacitor.
Summary of the invention
In view of the above problems, the object of the present invention is to provide a kind of manufacture method of Multilayer MOM capacitor, the present invention, by improving dielectric k value of layer inner capacitor, improves the electric capacity of layer inner capacitor effectively, is very suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.
The invention provides a kind of manufacture method of metal-silicon nitride-metal capacitor, its step is as follows:
1) in silicon chip substrate, first utilize plasma enhanced chemical vapor deposition method (PECVD) to deposit high k value silicon nitride film;
2) remove the silicon nitride in non-MOM region by photoetching and etching;
3) deposit low k value dielectric layer;
4) cmp is removed unnecessary silicon nitride, forms the mixed layer of low k value medium and silicon nitride;
5) complete photoetching and be etched in low k value medium and silicon nitride and form metallic channel;
6) form the metal filled of wire and MOM capacitor after completing metal level deposition and metal level cmp;
7) repeating step (1), to step (6), forms multilayer MOM capacitor.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further:
In described step (1), silicon nitride deposition adopts two step endless form of deposited silicon nitride-oxygen-containing gas processing to complete.
The oxygen-containing gas using in silicon nitride deposition in described step (1) is one or several in nitric oxide, nitrous oxide, carbon monoxide and carbon dioxide.
In described step (1), in silicon nitride deposition, each silicon nitride deposit thickness is 1 nanometer to 10 nanometer.
In the middle silicon nitride deposition of described step (1), the gas flow of oxygen-containing gas processing is between 2000 to 6000sccm.
In the middle silicon nitride deposition of described step (1), the treatment temperature of oxygen-containing gas processing is between 300 to 600 degrees Celsius.
The present invention proposes a kind of manufacture method of Multilayer MOM capacitor, by improving dielectric k value of layer inner capacitor, effectively improves the electric capacity of layer inner capacitor.By improving the performance of high k value silicon nitride, effectively improve each electrical characteristics such as puncture voltage, leakage current of metal-silicon nitride-metal (MOM) capacitor, and electricity uniformity between each device.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of specification, and for above and other object of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Brief description of the drawings
With reference to appended accompanying drawing, to describe more fully embodiments of the invention.But appended accompanying drawing only, for explanation and elaboration, does not form limitation of the scope of the invention.
Fig. 1 illustrates the generalized section of silicon nitride film layer.
Fig. 2 has illustrated photoetching and etching and has removed the generalized section of the silicon nitride film of non-MOM capacitor regions.
Fig. 3 has illustrated the generalized section of low k value medium and silicon nitride mixed layer after the unnecessary low k value medium of deposition low k value medium and cmp removal.
Fig. 4 has illustrated the generalized section of photoetching and etching formation metallic channel.
Fig. 5 has illustrated the generalized section of wire metal and MOM capacitor after metal level deposition and metal level cmp.
Fig. 6 illustrates the generalized section of multilayer MOM capacitor.
Label declaration: 1. low k value medium, 2. silicon nitride, 3. fills metal.
Embodiment
Technological means and effect of taking for reaching predetermined goal of the invention for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to the manufacture method of a kind of Multilayer MOM capacitor proposing according to the present invention, be described in detail as follows.
Different embodiments of the invention will details are as follows, to implement different technical characterictic of the present invention, will be understood that, the unit of the specific embodiment of the following stated and configuration are in order to simplify the present invention, and it is not only for example limits the scope of the invention.
Embodiment mono-
First in silicon chip substrate, first utilize plasma enhanced chemical vapor deposition method (PECVD) to deposit high k value silicon nitride film, wherein silicon nitride deposition adopts two step endless form of deposited silicon nitride-oxygen-containing gas processing to complete, the oxygen-containing gas using is nitric oxide, the gas flow of oxygen-containing gas processing is 3000sccm, treatment temperature is 400 degrees Celsius, each silicon nitride deposit thickness is 2 nanometers, adopt two step circulations of deposited silicon nitride-oxygen-containing gas processing to reach final required silicon nitride thickness, Fig. 1 illustrates the generalized section of silicon nitride film layer.Then remove the silicon nitride in non-MOM region by photoetching and etching, Fig. 2 has illustrated photoetching and etching and has removed the generalized section of the silicon nitride film of non-MOM capacitor regions.Deposit low k value dielectric layer, and remove unnecessary low k value dielectric layer with cmp, form the mixed layer of low k value medium and silicon nitride.Fig. 3 has illustrated the generalized section of low k value medium and silicon nitride mixed layer after the unnecessary low k value medium of deposition low k value medium and cmp removal.Complete photoetching and be etched in low k value medium forming metallic channel, Fig. 4 has illustrated the generalized section of photoetching and etching formation metallic channel.After completing metal level deposition and metal level cmp, form the metal filled of wire and MOM capacitor, Fig. 5 illustrated that metal level deposits and metal level cmp after the generalized section of wire metal and MOM capacitor.Repeating step (1), to step (6), forms multilayer MOM capacitor, and Fig. 6 illustrates the generalized section of multilayer MOM capacitor.
Implement two
First in silicon chip substrate, first utilize plasma enhanced chemical vapor deposition method (PECVD) to deposit high k value silicon nitride film, wherein silicon nitride deposition adopts two step endless form of deposited silicon nitride-oxygen-containing gas processing to complete, the oxygen-containing gas using is nitrous oxide, the gas flow of oxygen-containing gas processing is 4000sccm, treatment temperature is 500 degrees Celsius, each silicon nitride deposit thickness is 4 nanometers, adopt two step circulations of deposited silicon nitride-oxygen-containing gas processing to reach final required silicon nitride thickness, Fig. 1 illustrates the generalized section of silicon nitride film layer.Then remove the silicon nitride in non-MOM region by photoetching and etching, Fig. 2 has illustrated photoetching and etching and has removed the generalized section of the silicon nitride film of non-MOM capacitor regions.Deposit low k value dielectric layer, and remove unnecessary low k value dielectric layer with cmp, taking high k value medium as grinding stop-layer, form the mixed layer of low k value medium and silicon nitride.Deposit again low k value medium to desired thickness.Fig. 3 has illustrated the generalized section of low k value medium and silicon nitride mixed layer after the unnecessary low k value medium of deposition low k value medium and cmp removal.Complete photoetching and be etched in low k value medium forming metallic channel, Fig. 4 has illustrated the generalized section of photoetching and etching formation metallic channel.After completing metal level deposition and metal level cmp, form the metal filled of wire and MOM capacitor, Fig. 5 illustrated that metal level deposits and metal level cmp after the generalized section of wire metal and MOM capacitor.Repeating step (1), to step (6), forms multilayer MOM capacitor, and Fig. 6 illustrates the generalized section of multilayer MOM capacitor.
Implement three
First in silicon chip substrate, first utilize plasma enhanced chemical vapor deposition method (PECVD) to deposit high k value silicon nitride film, wherein silicon nitride deposition adopts two step endless form of deposited silicon nitride-oxygen-containing gas processing to complete, the oxygen-containing gas using is carbon monoxide, the gas flow of oxygen-containing gas processing is 5000sccm, treatment temperature is 300 degrees Celsius, each silicon nitride deposit thickness is 5 nanometers, adopt two step circulations of deposited silicon nitride-oxygen-containing gas processing to reach final required silicon nitride thickness, Fig. 1 illustrates the generalized section of silicon nitride film layer.Then remove the silicon nitride in non-MOM region by photoetching and etching, Fig. 2 has illustrated photoetching and etching and has removed the generalized section of the silicon nitride film of non-MOM capacitor regions.Deposit low k value dielectric layer, and remove unnecessary low k value dielectric layer with cmp, form the mixed layer of low k value medium and silicon nitride.Fig. 3 has illustrated the generalized section of low k value medium and silicon nitride mixed layer after the unnecessary low k value medium of deposition low k value medium and cmp removal.Complete photoetching and be etched in low k value medium forming metallic channel, Fig. 4 has illustrated the generalized section of photoetching and etching formation metallic channel.After completing metal level deposition and metal level cmp, form the metal filled of wire and MOM capacitor, Fig. 5 illustrated that metal level deposits and metal level cmp after the generalized section of wire metal and MOM capacitor.Repeating step (1), to step (6), forms multilayer MOM capacitor, and Fig. 6 illustrates the generalized section of multilayer MOM capacitor.
Implement four
First in silicon chip substrate, first utilize plasma enhanced chemical vapor deposition method (PECVD) to deposit high k value silicon nitride film, wherein silicon nitride deposition adopts two step endless form of deposited silicon nitride-oxygen-containing gas processing to complete, the oxygen-containing gas using is carbon dioxide, the gas flow of oxygen-containing gas processing is 6000sccm, treatment temperature is 600 degrees Celsius, each silicon nitride deposit thickness is 10 nanometers, adopt two step circulations of deposited silicon nitride-oxygen-containing gas processing to reach final required silicon nitride thickness, Fig. 1 illustrates the generalized section of silicon nitride film layer.Then remove the silicon nitride in non-MOM region by photoetching and etching, Fig. 2 has illustrated photoetching and etching and has removed the generalized section of the silicon nitride film of non-MOM capacitor regions.Deposit low k value dielectric layer, and remove unnecessary low k value dielectric layer with cmp, taking high k value medium as grinding stop-layer, form the mixed layer of low k value medium and silicon nitride.Deposit again low k value medium to desired thickness.Fig. 3 has illustrated the generalized section of low k value medium and silicon nitride mixed layer after the unnecessary low k value medium of deposition low k value medium and cmp removal.Complete photoetching and be etched in low k value medium forming metallic channel, Fig. 4 has illustrated the generalized section of photoetching and etching formation metallic channel.After completing metal level deposition and metal level cmp, form the metal filled of wire and MOM capacitor, Fig. 5 illustrated that metal level deposits and metal level cmp after the generalized section of wire metal and MOM capacitor.Repeating step (1), to step (6), forms multilayer MOM capacitor, and Fig. 6 illustrates the generalized section of multilayer MOM capacitor.
By explanation and accompanying drawing, provide the exemplary embodiments of the ad hoc structure of embodiment.Although foregoing invention has proposed existing preferred embodiment, but these contents are not as limitation.For a person skilled in the art, read after above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Within the scope of claims, scope and the content of any and all equivalences, all should think and still belong to the intent and scope of the invention.
Claims (6)
1. a manufacture method for Multilayer MOM capacitor device, is characterized in that: it has following steps:
1) in silicon chip substrate, first utilize plasma enhanced chemical vapor deposition method to deposit high k value silicon nitride film;
2) remove the silicon nitride in non-MOM region by photoetching and etching;
3) deposit low k value dielectric layer;
4) cmp is removed unnecessary low k value dielectric layer, forms metal layer conductive line and passes that low k dielectric layer is connected with silicon nitride and the mixed layer of low k dielectric layer and silicon nitride;
5) complete photoetching and be etched in low k value medium and silicon nitride and form metallic channel;
6) form the metal filled of wire and MOM capacitor after completing metal level deposition and metal level cmp;
7) repeating step 1) to step 6), form multilayer MOM capacitor.
2. the manufacture method of a kind of Multilayer MOM capacitor device as claimed in claim 1, is characterized in that: described step 1) in silicon nitride deposition adopt two step endless form of deposited silicon nitride-oxygen-containing gas processing to complete.
3. the manufacture method of a kind of Multilayer MOM capacitor device as claimed in claim 1, is characterized in that: described step 1) in the oxygen-containing gas that uses in silicon nitride deposition be one or several in nitric oxide, nitrous oxide, carbon monoxide and carbon dioxide.
4. the manufacture method of a kind of Multilayer MOM capacitor device as claimed in claim 1, is characterized in that: described step 1) in silicon nitride deposition each silicon nitride deposit thickness be 1 nanometer to 10 nanometer.
5. the manufacture method of a kind of Multilayer MOM capacitor device as claimed in claim 1, is characterized in that: described step 1) in the gas flow of oxygen-containing gas processing in silicon nitride deposition between 2000 to 6000sccm.
6. the manufacture method of a kind of Multilayer MOM capacitor device as claimed in claim 1, is characterized in that: described step 1) in the treatment temperature of oxygen-containing gas processing in silicon nitride deposition between 300 to 600 degrees Celsius.
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| CN107644810B (en) * | 2016-07-20 | 2024-05-31 | 全球能源互联网研究院 | Front electrode processing method of crimping IGBT/FRD chip |
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|---|---|---|---|---|
| TW479353B (en) * | 2001-01-17 | 2002-03-11 | Taiwan Semiconductor Mfg | Manufacturing method of MIM capacitor |
| US6458650B1 (en) * | 2001-07-20 | 2002-10-01 | Taiwan Semiconductor Manufacturing Company | CU second electrode process with in situ ashing and oxidation process |
| US6559004B1 (en) * | 2001-12-11 | 2003-05-06 | United Microelectronics Corp. | Method for forming three dimensional semiconductor structure and three dimensional capacitor |
| CN101577227A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Forming methods of silicon nitride film and MIM capacitor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW479353B (en) * | 2001-01-17 | 2002-03-11 | Taiwan Semiconductor Mfg | Manufacturing method of MIM capacitor |
| US6458650B1 (en) * | 2001-07-20 | 2002-10-01 | Taiwan Semiconductor Manufacturing Company | CU second electrode process with in situ ashing and oxidation process |
| US6559004B1 (en) * | 2001-12-11 | 2003-05-06 | United Microelectronics Corp. | Method for forming three dimensional semiconductor structure and three dimensional capacitor |
| CN101577227A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Forming methods of silicon nitride film and MIM capacitor |
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