TW479353B - Manufacturing method of MIM capacitor - Google Patents
Manufacturing method of MIM capacitor Download PDFInfo
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- TW479353B TW479353B TW090101074A TW90101074A TW479353B TW 479353 B TW479353 B TW 479353B TW 090101074 A TW090101074 A TW 090101074A TW 90101074 A TW90101074 A TW 90101074A TW 479353 B TW479353 B TW 479353B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 114
- 229910052751 metal Inorganic materials 0.000 claims abstract description 61
- 239000002184 metal Substances 0.000 claims abstract description 61
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 57
- 238000000034 method Methods 0.000 claims abstract description 44
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 238000000151 deposition Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 18
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000010937 tungsten Substances 0.000 claims abstract description 18
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 18
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000009413 insulation Methods 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims abstract description 7
- 238000007517 polishing process Methods 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 44
- 239000000463 material Substances 0.000 claims description 24
- 239000010409 thin film Substances 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 238000005137 deposition process Methods 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- -1 ruthenium-gold-tungsten Chemical compound 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims 2
- 239000004020 conductor Substances 0.000 claims 2
- 229910052702 rhenium Inorganic materials 0.000 claims 2
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 claims 2
- 229910052779 Neodymium Inorganic materials 0.000 claims 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims 1
- 238000005520 cutting process Methods 0.000 claims 1
- 229910052750 molybdenum Inorganic materials 0.000 claims 1
- 239000011733 molybdenum Substances 0.000 claims 1
- MUMZUERVLWJKNR-UHFFFAOYSA-N oxoplatinum Chemical compound [Pt]=O MUMZUERVLWJKNR-UHFFFAOYSA-N 0.000 claims 1
- 229910003446 platinum oxide Inorganic materials 0.000 claims 1
- 229910052726 zirconium Inorganic materials 0.000 claims 1
- 229910052707 ruthenium Inorganic materials 0.000 abstract description 6
- 239000012212 insulator Substances 0.000 abstract description 2
- 230000008569 process Effects 0.000 description 13
- 238000003860 storage Methods 0.000 description 9
- 239000013078 crystal Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- XEKOWRVHYACXOJ-UHFFFAOYSA-N Ethyl acetate Chemical compound CCOC(C)=O XEKOWRVHYACXOJ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000005342 ion exchange Methods 0.000 description 3
- 238000006263 metalation reaction Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- WVBBLATZSOLERT-UHFFFAOYSA-N gold tungsten Chemical compound [W].[Au] WVBBLATZSOLERT-UHFFFAOYSA-N 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 241000579895 Chlorostilbon Species 0.000 description 1
- 241001052209 Cylinder Species 0.000 description 1
- 108010001498 Galectin 1 Proteins 0.000 description 1
- 102100021736 Galectin-1 Human genes 0.000 description 1
- 241001674048 Phthiraptera Species 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229910052876 emerald Inorganic materials 0.000 description 1
- 239000010976 emerald Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- JUWSSMXCCAMYGX-UHFFFAOYSA-N gold platinum Chemical compound [Pt].[Au] JUWSSMXCCAMYGX-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- CFQCIHVMOFOCGH-UHFFFAOYSA-N platinum ruthenium Chemical compound [Ru].[Pt] CFQCIHVMOFOCGH-UHFFFAOYSA-N 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
479353 五、發明說明(1) 發明領域: 本發明與一種金屬/絕緣層/金屬(ΜIΜ)電容器的製作 方法有關,特別是一種使用無電鍍製程(electroiess), 沉積鉑金屬來構成電容器其接觸插塞(Pt plug)之相關製 發明背景: 一般而言,動態隨機存取記憶體(DRAM)往往包含了數 以萬計以陣列方式排列的記憶單元(ceU),且對每一個記 憶單元而言,通常是由電容器與電晶體所構成,以便儲存 *位元(b i t)之§fl號。其中,電晶體的第一汲/源極可與電 谷f 一端連接,而電容之另一端則與參考電位連接。至於 電,體之第二汲/源極與閘極則分別與位元線(bit Hne)、 =字語線(word line)連接,以便進行相關的操作功能。 製造DRAM記憶單元時,往往也包含了電晶體與電容 =’並藉著電谷裔與電晶體間的電性接觸,將 成儲存在電容器中。 貝 古〜然而,隨著超大型積體電路(ULSI)的發展,為了符人 度積體電路的設計趨勢,動態隨機存取記憶單元之又 曰’,、降至次微米以下。而且隨著DRAM元件密度不斷的上 用來製作電谷裔其儲存電極的區域面積亦相對的縮479353 V. Description of the invention (1) Field of the invention: The present invention relates to a method for manufacturing a metal / insulating layer / metal (MIM) capacitor, in particular a method for depositing platinum metal to form a capacitor with a contact plug using electrolesss (electroiess). Background of the related invention of Pt plug: Generally speaking, dynamic random access memory (DRAM) often contains tens of thousands of memory cells (ceU) arranged in an array, and for each memory cell , Usually composed of a capacitor and a transistor, in order to store the §fl number of bits. The first drain / source of the transistor can be connected to one end of the valley f, and the other end of the capacitor is connected to the reference potential. As for electricity, the second drain / source and gate of the body are respectively connected to the bit line and the word line in order to perform related operation functions. When manufacturing a DRAM memory cell, a transistor and a capacitor are often included, and are stored in a capacitor through electrical contact between the transistor and the transistor. Begu ~ However, with the development of ultra-large integrated circuits (ULSI), in order to meet the design trend of human integrated circuits, the dynamic random access memory unit is reduced to sub-micron. And as the density of DRAM elements continues to increase, the area of the storage electrodes used to make the electric valleys is also relatively reduced.
五、發明說明(2) 寸也p夕:來,由於DRAM元件不斷的縮小,促使其電容尺 動皞u少’故其儲存載子之性能也相對降低。是以對 =心機存取記憶體(DRAM)中的記憶單元(mem〇ry ce⑴ 隹^牲2 ^的^ λ問題是如何在元件&寸趨向縮小且積 I ^ Γ提兩之情形下’提昇電容的儲存能力,並增加電 谷的可靠度。 六Μ ^此,業界設計出各式各樣的堆疊結構,以便增加電 谷為的儲存能力。這些堆疊結構包括了指狀電容器 皇冠型電容器(Cr〇Wn)、分散式電容器(spread)與 f ί f器(cyl inder)等…用來嘗試在高密度的dram元 ’藉著各式各樣密集的堆疊方式來增加電容值。铁 而,受制於目前微影製程的解析度與最小線寬之限制了對 256^或是“的⑽-元件來說,上述的堆疊結構所能提供的 電谷儲存能力,依舊難以達到所需的目標。 八“於此同時,亦有人提出利用高介電值薄膜作為電容器 ^電層,來製作具有金屬/絕緣層/金屬(MIM)結構之電容 裔,以便藉著其較佳的導電性與電荷儲存能力,來取代 統金屬/絕緣層/矽層(M丨s )結構之電容器。其中,藉著採 用,渡金屬氧化物來作為電容器介電層,確實可達到增木加 電容器介電係數的目的。例如使用諸如。々或BaTi〇3等言ϋ 介電係數材料,來製作金屬/絕緣層/金屬電容器,可符: 未來DRAM技術中對電容器的需求。並且,由於金屬/絕緣σ 479353V. Description of the invention (2) Inch size: In the future, due to the continuous shrinkage of DRAM components, the capacitance of the DRAM is reduced, so the performance of the stored carriers is also relatively reduced. The question is how to match the memory unit (memory ce〇 牲 ^ 2 2 ^ ^ λ in the memory access memory (DRAM) in the case where the component & inch tends to shrink and the product I ^ Γ is two). Improve the storage capacity of capacitors and increase the reliability of power valleys. Six M ^ Therefore, the industry has designed a variety of stacked structures to increase the storage capacity of power valleys. These stacked structures include finger capacitors crown type capacitors (CrOWn), distributed capacitors (spread), f ί f (cyl inder), etc ... used to try to increase the capacitance value in various high-density dram elements through various dense stacking methods. Limited by the resolution and minimum line width of the current lithography process, it is still difficult to achieve the required target storage capacity of the valley provided by the above-mentioned stacked structure for 256 ^ or "“ "devices. . At the same time, it was also proposed to use a high dielectric film as the capacitor's electrical layer to make a capacitor with a metal / insulating layer / metal (MIM) structure in order to take advantage of its better conductivity and charge. Storage capacity to replace Tongjin Capacitors of the / insulation layer / silicon layer (M 丨 s) structure. Among them, by using metal oxides as the capacitor dielectric layer, the purpose of increasing the dielectric constant of the capacitor can be achieved. For example, using such as. 々 or BaTi〇3, etc. 介 Dielectric constant materials to make metal / insulating layers / metal capacitors can meet the demand for capacitors in future DRAM technology. And because of metal / insulation σ 479353
$ 金屬電容器其接面不易發生反應,且可提供較高儲 ”谷值’是以可充分的運用於未來的dram製程中。 以目 具有極高 的研究與 專結構中 具有相當 確的定義 不易控制 往會導致 易與矽原 低整體製 ,鉑金屬材料由於 流,是以受到廣泛 存電極或接觸插塞 料的使用上,依舊 製程來說,很難精 製程中的絕對維度 ,是以在使用上往 屬材料時,其極容 的材料特性,並降 前的BST電容器製作技術來說 的抗氧化能力與較低的漏洩電 利用,而大量的應用於電容儲 。然而’在目前有關麵金屬材 多的困難。例如以目前的钱刻 圖案於翻金屬上,而導致相關 。另外,由於鉑金屬極為昂貴 成本上昇。並且,在使用鉑金 子發生反應,而改變彼此接面 程的良率。 存雷^外’隨著元件維度尺寸不斷的縮小,在製作電容儲 古,而!接觸Ϊ塞時’所面臨接觸孔的縱橫比往往變得更 :成填充變得更加銀矩,並容易在接觸= 對目前典型的嫣插塞製程來說良:二=特性。特別是 的接面效果,&進行鶴金屬沉产”屬與石夕底材」 /氮化銥組成的阻障層於接觸^ /’絲會先形成由鈦一 來,其間的縱橫比將變T更觸大孔= 程變得更加困難。並且,儘管上:使屬材料的填充製 積去來製作而使其具有較均句的覆蓋特性。但對於$ Metal capacitors are not easy to react at their interfaces, and can provide a high storage "valley", which can be fully used in the future dram process. It is not easy to have a very high definition in the research and specialized structure. Controlling will lead to a low-integrity system made of silicon. Due to the flow of platinum metal materials, it is widely used in electrode or contact plug materials. For the manufacturing process, it is difficult to refine the absolute dimension of the process. When using the previous materials, its extremely capacitive material characteristics, and the oxidation resistance and lower leakage electricity utilization of the previous BST capacitor manufacturing technology are reduced, and a large number of them are used in capacitor storage. However, in the current relevant aspects There are many difficulties in metal materials. For example, the current money engraving pattern is used to turn metal, which is related. In addition, platinum metal is extremely expensive, and the cost increases. Moreover, the use of platinum gold reacts and changes the yield of the interface. Cun Lei ^ Wai 'As the dimensions of the components continue to shrink, in the production of capacitor storage, and the aspect ratio of the contact hole facing when contacting congestion often becomes : The filling becomes more silvery, and it is easy to contact = good for the current typical Yan plug process: two = characteristics. Especially the interface effect, & carrying out crane metal sinking "belongs to Shi Xidi The barrier layer composed of "Material" / Iridium Nitride will be formed by titanium when contacted with the wire, and the aspect ratio between them will become more T and the hole becomes more difficult. In addition, the above: the filling material of the base material is made to make it to have a more uniform coverage characteristic. But for
479353479353
鈦金屬層的製作來說’其僅能使用物理氣相沉積法來製 作’是以其階梯覆蓋能力極差,且容易導致空洞的產生 發明目的及概述: 本發明之目的為提供一種使用鉑金屬製作金屬/絕 層/金屬(MIM)電容器之方法。 ^ 本發明之又一目的為提供一種使用釕金屬薄膜作為 t層,以沉積鉑金屬於接觸孔中作為鉑金屬插塞之方法 本發明提供一種積體電路電容之製作方法,方法勺·八 了下列步驟。首先,形成鎢金屬層於半導體底材上\^ ^ ,釕金屬薄膜於鎢金屬層上。接著,蝕 ,儿 :屬層以定義接觸塾於半導體底材上。心金= 私層於半導體底材、釕金屬薄膜與鎢金屬層上。並I θ 積氮化石夕薄膜於層間介電層上。隨後,可敍心f且,沉 與芦pq人 j蚀刻鼠化石夕薄胺 s間介電層,以形成接觸孔於釕金屬薄膜表面上。馭 然後,可進行無電鍍沉積程序以形Λ 人 =之中。其中,上述曝露的釕金屬薄以接 =金屬可藉著離子交換程序,而由釕金屬薄‘ /儿積,並逐漸的填滿接觸孔。 、表面向 479353 五、發明說明(5) 二…棋與 金屬插塞表面上。皇製以。於 :的側壁上,並沉積艇金屬了;;=:間隙壁於皇冠型J 土、虱化矽薄膜與鉑 、而乳化矽層、氮 極使用。 插塞表面丨,以作為電容广 在塗佈光阻層於鉑金 研磨程序直至抵達氧化石夕声:=之後’可進行化學機械 部份鉑金屬薄膜。如;=面,以移除部份光阻層盥 介電㈣金丄:=面光:〜 為電容頂部電極使用。 、死於王过型開口中,並作 發明詳細說明: .方法本所二種製作金屬/絕緣層/金屬電容器之 =電鑛沉積程序,而在接觸.孔中沉積心 姓刻所遭遇的困難。有關本發明之詳細方法如下所‘進仃 請參照第一圖,首先提供一半導體底材1〇來沉積所需For the production of titanium metal layer, 'it can only be produced by physical vapor deposition method', it is because its step coverage ability is very poor, and it is easy to cause voids. The purpose and summary of the invention is to provide a method using platinum metal. Method for making metal / insulation / metal (MIM) capacitors. ^ Another object of the present invention is to provide a method for using a ruthenium metal film as the t layer to deposit platinum metal in a contact hole as a platinum metal plug. The present invention provides a method for manufacturing an integrated circuit capacitor. The method is as follows: step. First, a tungsten metal layer is formed on a semiconductor substrate, and a ruthenium metal thin film is formed on the tungsten metal layer. Next, an etching layer is defined to define contact on the semiconductor substrate. Heart gold = private layer on semiconductor substrate, ruthenium metal film and tungsten metal layer. An I θ nitride nitride film is deposited on the interlayer dielectric layer. Subsequently, it can be described that Shen and Lu pq Ren j etched the interstitial layer of the rat fossil thin amine thin s to form contact holes on the surface of the ruthenium metal thin film. Then, an electroless deposition process can be performed in the shape of Λ = =. Among them, the above-mentioned exposed ruthenium metal thin film can be filled by the ruthenium metal thin film by ion exchange process, and gradually fill the contact hole. The surface is 479353 V. Description of the invention (5) Two ... Chess and metal plug on the surface. The imperial system. On: the side wall, and the boat metal is deposited;; =: The partition wall is used in the crown type J soil, lice silicon film and platinum, and the emulsified silicon layer and nitrogen electrode are used. The surface of the plug is used as a capacitor. The photoresist layer is coated with platinum. The grinding process is performed until it reaches the oxidized stone: = After ’, a chemical mechanical part of the platinum metal film can be performed. Such as; = surface to remove part of the photoresist layer. Dielectric: Gold: = surface light: ~ Used for the top electrode of the capacitor. He died in the Wang Guo-type opening, and explained it in detail: Method Two difficulties in the process of making metal / insulation layer / metal capacitor = electric ore deposition process, and depositing the surname in the hole. . The detailed method of the present invention is as follows. ′ Please refer to the first figure. First, a semiconductor substrate 10 is provided for deposition.
ΙΗϋΙ 麵 第8頁 479353 五、發明說明(6) ‘ 的膜層。其中,此半導體底材10可使用具<100〉晶向之單 .· 晶矽來加以構成。一般而言,其它種類之半導體材料,諸 如砷化鎵(gal 1 ium arsenide)、鍺(germanium)或是位於 絕緣層上之石夕底材(siHcon 〇n Insulator,SOI)亦可應 用作為此處的半導體底材l〇使用。另外,由於半導體底材 1 0表面的特性對本發明而言,並不會造成特別的影晌,是 以其晶向亦可選擇<110>或<111>。 接著’可形成鎢金屬層12於半導體底材10上。在較佳 只施例中’可利用化學氣相沉積法或是物理氣相沉積法來 沉積此處的鎢金屬層12。並且,對於DRAM元件中的電容器·’ 製作來說,可在沉積鎢金屬層丨2之前,先定義出製造元件 的主動區域’再藉著定義導電層圖案與進行離子佈植程 序’而製作出作為字語線(word lines)使用的複數個閘極 結構’以及位於這些閘極結構間的源/汲極區域。由於此 部份元件或相關製作步驟,並非本發明所要陳述之重點, 是以此處不加以詳述。在形成鎢金屬層丨2後,接著可沉積 釕金屬薄膜1 4於此鎢金屬層1 2上。 - 然後,如第二圖所示,藉著餘刻釕金屬薄膜1 4與鎢金_ 屬層12,可定義出如圖中所示之接觸墊16於半導體底材1〇 上。接著’沉積層間介電層(ILD) 1 8於半導體底材1 〇、釕 金屬薄膜14與鎢金屬層12上,以覆蓋住整個接觸墊16。一 般來說,此處的層間介電層18是由BPSG材料與TE〇s氧化物^ΙΗϋΙ 面 Page 8 479353 V. Description of the invention (6) ‘film. Among them, the semiconductor substrate 10 can be composed of a single crystal of a device < 100 > Generally speaking, other types of semiconductor materials, such as gal 1 ium arsenide, germanium, or siHcon On Insulator (SOI) on the insulation layer can also be used here. The semiconductor substrate 10 is used. In addition, since the characteristics of the surface of the semiconductor substrate 10 do not cause special effects to the present invention, the crystal orientation can also be selected as < 110 > or < 111 >. Next, a tungsten metal layer 12 may be formed on the semiconductor substrate 10. In the preferred embodiment, the tungsten metal layer 12 can be deposited by chemical vapor deposition or physical vapor deposition. In addition, for capacitors in DRAM devices, “the active area of the device can be defined before the tungsten metal layer 2 is deposited, and then it can be produced by defining the conductive layer pattern and performing the ion implantation process”. A plurality of gate structures used as word lines' and a source / drain region located between the gate structures. Because this part of the component or related manufacturing steps is not the focus of the present invention, it will not be described in detail here. After the tungsten metal layer 2 is formed, a ruthenium metal film 14 can be deposited on the tungsten metal layer 12. -Then, as shown in the second figure, the contact pad 16 shown in the figure can be defined on the semiconductor substrate 10 by using the remaining ruthenium metal film 14 and the tungsten gold metal layer 12. Next, an interlayer dielectric layer (ILD) 18 is deposited on the semiconductor substrate 10, the ruthenium metal film 14 and the tungsten metal layer 12 to cover the entire contact pad 16. Generally, the interlayer dielectric layer 18 here is made of BPSG material and TE0s oxide ^
479353 五、發明說明(7) --- 材料的複合層所構成。在較佳實施例中,可先使用常壓化 學氣相沉積法(APCVD)或是電漿增強化學氣相沉積法 (PECVD),在溫度約3〇〇至6〇〇。〇、且壓力約1至托耳 (T〇rr)的環境中形成厚度約BPSG材料層。然後,再使用正 石夕酸乙醋(1£03)在溫度6〇〇至8〇〇。(:間,且壓力約〇1至 10忱!^的環境中,以化學氣相沈積法製作TE〇s氧化材料層 在袅作層間介電層」j後,接著沉積氮化矽薄膜2〇於芦 間介電層18表面上。-般來說,此氮化石夕薄膜2〇可以使^ 低壓化學氣相沈積法(LPCVD),電漿增強化學 (PECVD)在溫度大約4〇〇至8〇〇。(:的環境中形成。積$ 間介電層18,而形成接觸孔22於釕 Λ中’可先塗佈光阻材料於氮化石夕薄膜 定ίίΓ再藉著進行微影曝光、顯影、清洗等程序,而 案於光阻材料中。接著,可使用此光阻材料 罩冪’依次對下方的氮切薄賴與層間 18進仃蝕刻程序,以定義出上述的接觸孔22。 曰 請參照第三圖,接著進行無電鍍(electr〇iess)沉 耘序以形成鉑金屬插塞24於接觸孔22中。其中,“、 於接觸孔22底部曝露的釕金屬薄朗來作為種子;精者位 seeding layer),以便藉著離子交換程序,而曰 原子沉積於釕金屬薄膜14表面上,且逐漸的向上堆積金而屬填 479353 五、發明說明(8) 滿整個接觸孔22。值得注意的,由於此處的無電鍍沉積程 ·-序’是利用了材料間的離子交換特性來進行沉積。是以, 在沉積程序進行時,鉑原子是由接觸孔22的底部向上生長 (only bottom growth),而不會由接觸孔22的側壁進行沉 積。如此一來,沉積的鉑原子將以逐層堆疊的方式,依序 沉積於接觸孔22底部,而完全避免了空洞(voids)可能產 生的機會。 冬一般而言,可在鉑金屬插塞24的上表面抵達氮化矽薄 膜20,,停止無電鍍沉積程序。再沉積一氧化矽層26於氮 =矽薄膜20與鉑金屬插塞24上表面,以作為後續定義電容 ,儲存電極的絕緣層使用。在較佳實施例中,可使用化學 氣相沈積法(CVD),以四乙基矽酸鹽门肋幻在 = 壓力約o.um町間來製作所需的氧:二°至 w傻,參照第四圖,蝕刻氧化矽層2 6直 薄膜2〇與翻金屬插塞24表面為止,;479353 V. Description of the invention (7) --- The composite layer of materials. In a preferred embodiment, atmospheric pressure chemical vapor deposition (APCVD) or plasma enhanced chemical vapor deposition (PECVD) can be used first at a temperature of about 300 to 600. 〇, and a pressure of about 1 to Torr (Torr) in an environment to form a layer of a thickness of BPSG material. Then, ethyl acetate was used again (1 £ 03) at a temperature of 600 to 800. (: Occasionally, under a pressure of about 0.1 to 10 μm!), A TE0s oxide material layer is formed by chemical vapor deposition method, and then an interlayer dielectric layer is formed, and then a silicon nitride film is deposited. On the surface of the dielectric layer 18, in general.-Generally, this nitride film 20 can be used for low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical (PECVD) at a temperature of about 400 to 80. 〇. (: Formed in the environment. The interlayer dielectric layer 18 is formed, and the contact hole 22 is formed in ruthenium Λ. 'A photoresist material can be coated on the nitride film first, and then lithographic exposure and development are performed. , Cleaning and other procedures, and the case is in the photoresistive material. Then, the photoresistive material can be used to sequentially etch the nitrogen below and interlayer 18 to define the contact hole 22. Please refer to the third figure, and then perform an electroless plating (electr0iess) sinking sequence to form a platinum metal plug 24 in the contact hole 22. Among them, ", the ruthenium metal thin exposed at the bottom of the contact hole 22 as a seed; (Seeding layer) so that atoms are deposited on ruthenium by ion exchange On the surface of the thin film 14, gold is gradually piled up to fill 479353. V. Description of the invention (8) The entire contact hole 22 is filled. It is worth noting that because of the electroless deposition process here, the sequence is used between materials. Ion-exchange characteristics are used for deposition. Therefore, during the deposition process, platinum atoms are grown only from the bottom of the contact hole 22, but not from the sidewall of the contact hole 22. In this way, the deposition The platinum atoms will be sequentially deposited on the bottom of the contact hole 22 in a layer-by-layer manner, completely avoiding the chance of voids. In general, nitrogen can be reached on the upper surface of the platinum metal plug 24. The silicon film 20 is stopped, and the electroless deposition process is stopped. Then, a silicon oxide layer 26 is deposited on the upper surface of the nitrogen = silicon film 20 and the platinum metal plug 24, which is used as a subsequent definition of the capacitor and the insulating layer of the storage electrode. In the embodiment, a chemical vapor deposition (CVD) method can be used to produce the required oxygen with a tetraethyl silicate portal rib at a pressure of about o.um: 2 ° to w, refer to the fourth Figure, etching silicon oxide layer 2 6 2〇 film 24 and a metal plug surface turned up,;
半導體底材Η上。其中,可先.塗佈光阻以:= ^面,再藉著進行微影製程定義出皇二 :。然後,使用此光阻層作為姓刻罩冪,;;圖= :蝕刻,而定義出皇冠型開口於其中。在: 底部表面上。亦即,沉積氣化儀二的二The semiconductor substrate is stacked. Among them, you can first apply the photoresist to: = ^ surface, and then define the Emperor II by lithography process. Then, use this photoresist layer as the last mask power;; Figure =: Etching, and define the crown-shaped opening in it. On: On the bottom surface. That is, two of the two deposition gasifiers
479353 五、發明說明(9) 石夕薄膜20與鉑金屬插塞24的表面上 接著, 刻術(RIE) 並定義氮化 位於氮化矽 部份氮化矽 積鉑金屬薄 薄膜20與鉑 電極之製程 層3 6於鉑金 如第五圖所示,對氮化矽層3 0進行反應離子蝕 以移除位於開口圖案底部的部份氮化矽層, f間隙壁32於氧化矽層26的側壁上。亦即,將 薄膜20、鉑金屬插塞24與氧化矽層26上表面的 層移除,而製作出氮化矽間隙壁32。然後,沉 膜34於氧化矽層26、氮化矽間隙壁32、氮化矽 金屬插塞24表面上,以提供後續定義電容底部 使用。在沉積鉑金屬薄膜34後,接著塗佈光阻 屬薄膜34上,且填充於皇冠型開口 28之中。 隨後 研磨程序 光阻層3 6 的側壁與 器底部電 可沉積電 上。在較 成。然後 填充於皇 底材1 0進行化學機械 面為止,以移除部份 ’可在皇冠型開口 28 薄膜34所構成的電容 殘餘的光阻材料後, 與氧化矽層26表面 層38可由BST材料構 介電層38表面上,且 器頂部電極使用。 ,如第 ,直至 與部份 底部表 極。在 容介電 佳實施 ,可沉 冠型開 六圖所 抵達氧 翻金屬 面,定 移除皇 層38於 例中, 積鉑金 口 28中 示,對 化石夕層 薄膜34 義出由 冠型開 鉑金屬 上述電 屬層40 ,而作 半導體 26上表 。如此 翻金屬 口 28中 薄膜34 容介電 於電容 為電容 使用本發明的方法’來製作鉑金屬電容器具有相當多 的優點。首先’藉著製作鶴金屬接觸墊,可以縮短後^接 479353 積填充金屬 要強調的, 金屬薄膜來 勤金屬插塞 性,而進行 表面向上堆 為蓋層使用 可產生種子 一來,在所 洞,而可有 五、發明說明(10) 觸孔的縱橫比,而 (process wi ndow) 屬層的上方,並沉 layer),是以在後 釕金屬薄膜的離子 使鉑原子沿著釕金 金屬插塞。亦即, 續的鉑金屬插塞製: 原子的附著與沉積 中’將不會產生任 的特性。 時的製程誤差允許值 由於本發明中在鎢金 作為蓋層(cap 時,可藉著鉑原子與 ,電鍍沉積製程,並 逢’而構成所需的鉑 的釕金屬薄瞑,在後' 層的功能,而便於鉑 製作的的鉑金屬插塞 效的維持其連線導電 另外,藉 的防止作為電 應。並且,由 義電容器的底 之困難,而可 本發明中是使 困此相較於傳 程,本發明的 沉積較厚翻金 巧用氮切側壁與氮切薄膜,可以有效 谷益底部電極之鉑金屬層’與矽原子發生反 於在本發明中是使用化學機械研磨程序來定 部電極,是以可有效解決直接蝕刻鉑金屬層 精確的控制所需的絕對維度。更者,由於在 用較薄的翻金屬層來構成電容器底部電極, 統技術中對較厚的鉑金屬層進行蝕刻之製 方法顯然除了可解決蝕刻問題外,尚可避免 屬所造成的成本耗費。 本發明雖以一較佳實例闡明如上,然其並非用以限定 本發明精神與發明實體,僅止於此一實施例爾。對熟悉此 479353479353 V. Description of the invention (9) Next, the surface of the Shixi film 20 and the platinum metal plug 24 is etched (RIE) and defined to be nitrided in the silicon nitride part. The silicon nitride deposited platinum thin film 20 and the platinum electrode The process layer 36 in platinum is shown in the fifth figure, and the silicon nitride layer 30 is reactively etched to remove a part of the silicon nitride layer at the bottom of the opening pattern. The f spacer 32 is on the silicon oxide layer 26. On the sidewall. That is, the layers on the upper surface of the thin film 20, the platinum metal plug 24, and the silicon oxide layer 26 are removed to form a silicon nitride spacer 32. Then, a sinker film 34 is formed on the surface of the silicon oxide layer 26, the silicon nitride spacer 32, and the silicon nitride metal plug 24, so as to provide the use of the capacitor bottom defined later. After the platinum metal thin film 34 is deposited, the photoresist thin film 34 is then coated and filled in the crown-shaped opening 28. Subsequent grinding procedures The sidewalls of the photoresist layer 36 and the bottom of the device are electrically deposited. In comparison. Then it is filled in the emerald substrate 10 for the chemical mechanical surface to remove a portion of the photoresist material that can be left in the capacitor formed by the crown-shaped opening 28 and the film 34, and the silicon oxide layer 26 and the surface layer 38 can be made of BST material. The dielectric layer 38 is on the surface, and the top electrode is used. , As above, until the bottom of the and part. In the implementation of Rongdijia, the sinkable crown-type opening six pictures reached the oxygen metal surface, and the imperial layer 38 will be removed. In the example, the platinum deposit port 28 is shown, and the fossil evening layer film 34 is defined by the crown-type opening. The above-mentioned electrical metal layer 40 of platinum is used as the semiconductor 26 as described above. In this way, the thin film 34 in the metal port 28, the capacitance, the capacitance, and the capacitance are capacitors. Using the method of the present invention to make a platinum metal capacitor has many advantages. First of all, by making crane metal contact pads, it is possible to shorten the thickness of 479353. Filled metal should be emphasized, the metal thin film is used for metal plugging, and the surface is piled up as a cover layer to produce seeds. However, there can be five, description of the invention (10) the aspect ratio of the contact hole, and (process window) is above the layer, and the layer is layered). The ions of the ruthenium metal film are used to make the platinum atoms along the ruthenium metal. Plug. That is, the continuous platinum metal plug system: atomic adhesion and deposition will not produce any characteristics. The allowable value of the process error at this time is because in the present invention, tungsten gold is used as the cap layer (cap, the platinum atom and the electroplating process can be used to form the required platinum ruthenium metal thin layer, and the latter layer The function of the platinum metal plug, which is convenient for platinum, maintains the electrical conductivity of the connection. In addition, it is prevented as an electrical response. In addition, the difficulty of the capacitor is difficult, but it can be compared in the present invention. In the transfer process, the present invention deposits thicker gold through the use of nitrogen-cut sidewalls and nitrogen-cut films, which can effectively prevent the platinum metal layer of the bottom electrode and silicon atoms from occurring, as opposed to using a chemical mechanical polishing process in the present invention The fixed electrode is an absolute dimension that can effectively solve the precise control of direct etching of the platinum metal layer. Furthermore, because the thinner metal layer is used to form the bottom electrode of the capacitor, the thicker platinum metal is used in the conventional technology. Obviously, in addition to solving the problem of etching, the method for etching the layers can also avoid the cost. The present invention is illustrated above with a preferred example, but it is not intended to limit the present invention. God invention with an entity, only limited to this embodiment Seoul. Familiar with this 479353
第14頁 479353 圖式簡單說明 藉由以下詳細之描述結合所附圖示,將可輕易的了解 上述内容及此項發明之諸多優點,其中: 第一 在半導體 第二 接觸孔於 第三 無電鍍沉 第四 皇冠型開 驟; 第五 氮化矽間 第六 翻金屬來 圖為半導體晶 底材上形成鎢 圖為半導體晶 接觸墊上方, 圖為半導體晶 積程序定義鉑 圖為半導體晶 口於氧化矽層 圖為半導體晶 隙壁於開口側 圖為半導體晶 構成電容器電 片之截面圖,顯示根據本發明技術 金屬層與釕金屬薄膜堆疊之步驟; 片之截面圖,顯示根據本發明形成 以曝露出釕金屬薄膜表面之步驟; 片之截面圖,顯示根據本發明使用 金屬插塞之步驟; 片之截面圖,顯示根據本發明形成 中,以曝露出鉑金屬插塞表面之步 片之截面圖,顯示根據本發明定義 壁上之步驟;及 片之截面圖,顯示根據本發明沉積 極之步驟。 _Page 479353 Brief description of the drawings The above description and the many advantages of this invention can be easily understood through the following detailed description combined with the attached drawings, among which: the first contact hole in the semiconductor and the third electroless plating Shen the fourth crown type start; the fifth silicon nitride and the sixth flip metal. The picture shows the formation of tungsten on the semiconductor crystal substrate. The picture shows the semiconductor crystal contact pads. The picture shows the semiconductor crystal deposition program. The platinum picture shows the semiconductor crystal port. The silicon oxide layer diagram is a cross-sectional view of a semiconductor crystal gap wall on the open side and a semiconductor crystal constitutes a capacitor chip, showing the steps of stacking a metal layer and a ruthenium metal film according to the technology of the present invention; Steps of exposing the surface of a ruthenium metal thin film; Sectional view of a sheet showing a step using a metal plug according to the present invention; Sectional view of a sheet showing a cross section of a step piece exposed to the surface of a platinum metal plug in the formation according to the present invention Figures showing the steps on a wall defined according to the invention; and sectional views of the sheet showing the steps of depositing a pole according to the invention. _
第15頁Page 15
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100342522C (en) * | 2003-08-20 | 2007-10-10 | 台湾积体电路制造股份有限公司 | Capcitor structure of integrated circuit and manfuacturing method thereof |
CN102592968A (en) * | 2011-11-15 | 2012-07-18 | 上海华力微电子有限公司 | Method for producing multilayer metal-silicon nitride-metal capacitor |
TWI830119B (en) * | 2021-08-30 | 2024-01-21 | 台灣積體電路製造股份有限公司 | Semiconductor device and forming method thereof |
-
2001
- 2001-01-17 TW TW090101074A patent/TW479353B/en not_active IP Right Cessation
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100342522C (en) * | 2003-08-20 | 2007-10-10 | 台湾积体电路制造股份有限公司 | Capcitor structure of integrated circuit and manfuacturing method thereof |
CN102592968A (en) * | 2011-11-15 | 2012-07-18 | 上海华力微电子有限公司 | Method for producing multilayer metal-silicon nitride-metal capacitor |
CN102592968B (en) * | 2011-11-15 | 2014-12-10 | 上海华力微电子有限公司 | Method for producing multilayer metal-silicon nitride-metal capacitor |
TWI830119B (en) * | 2021-08-30 | 2024-01-21 | 台灣積體電路製造股份有限公司 | Semiconductor device and forming method thereof |
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