TW479353B - Manufacturing method of MIM capacitor - Google Patents

Abstract

There is disclosed a manufacturing method of MIM (metal/insulator/metal) capacitor, which comprises: first, sequentially depositing a tungsten layer and a ruthenium film on a semiconductor substrate, and defining a contact pad pattern by etching the ruthenium film and tungsten layer; then, sequentially depositing an inter-layer dielectric layer and a silicon nitride film for covering the semiconductor substrate, the ruthenium film and the tungsten layer; next, defining contact holes by an etching procedure to expose the ruthenium film; performing an electroless depositing procedure to form a platinum plug in the contact hole; subsequently, depositing an insulation layer on the silicon nitride film, and defining an opening pattern by etching; next, manufacturing a silicon nitride spacer on the sidewall of the opening pattern; after depositing a platinum film, defining the bottom electrode of the capacitor by a chemical mechanical polishing process; and then depositing a capacitance dielectric layer on the surface of the platinum film, and depositing a platinum layer on the surface of the capacitance dielectric layer to define the top electrode of the capacitor.

Description

479353 V. Description of the invention (1) Field of the invention: The present invention relates to a method for manufacturing a metal / insulating layer / metal (MIM) capacitor, in particular a method for depositing platinum metal to form a capacitor with a contact plug using electrolesss (electroiess). Background of the related invention of Pt plug: Generally speaking, dynamic random access memory (DRAM) often contains tens of thousands of memory cells (ceU) arranged in an array, and for each memory cell , Usually composed of a capacitor and a transistor, in order to store the §fl number of bits. The first drain / source of the transistor can be connected to one end of the valley f, and the other end of the capacitor is connected to the reference potential. As for electricity, the second drain / source and gate of the body are respectively connected to the bit line and the word line in order to perform related operation functions. When manufacturing a DRAM memory cell, a transistor and a capacitor are often included, and are stored in a capacitor through electrical contact between the transistor and the transistor. Begu ~ However, with the development of ultra-large integrated circuits (ULSI), in order to meet the design trend of human integrated circuits, the dynamic random access memory unit is reduced to sub-micron. And as the density of DRAM elements continues to increase, the area of the storage electrodes used to make the electric valleys is also relatively reduced.

V. Description of the invention (2) Inch size: In the future, due to the continuous shrinkage of DRAM components, the capacitance of the DRAM is reduced, so the performance of the stored carriers is also relatively reduced. The question is how to match the memory unit (memory ce〇 牲 ^ 2 2 ^ ^ λ in the memory access memory (DRAM) in the case where the component & inch tends to shrink and the product I ^ Γ is two). Improve the storage capacity of capacitors and increase the reliability of power valleys. Six M ^ Therefore, the industry has designed a variety of stacked structures to increase the storage capacity of power valleys. These stacked structures include finger capacitors crown type capacitors (CrOWn), distributed capacitors (spread), f ί f (cyl inder), etc ... used to try to increase the capacitance value in various high-density dram elements through various dense stacking methods. Limited by the resolution and minimum line width of the current lithography process, it is still difficult to achieve the required target storage capacity of the valley provided by the above-mentioned stacked structure for 256 ^ or "“ "devices. . At the same time, it was also proposed to use a high dielectric film as the capacitor's electrical layer to make a capacitor with a metal / insulating layer / metal (MIM) structure in order to take advantage of its better conductivity and charge. Storage capacity to replace Tongjin Capacitors of the / insulation layer / silicon layer (M 丨 s) structure. Among them, by using metal oxides as the capacitor dielectric layer, the purpose of increasing the dielectric constant of the capacitor can be achieved. For example, using such as. 々 or BaTi〇3, etc. 介 Dielectric constant materials to make metal / insulating layers / metal capacitors can meet the demand for capacitors in future DRAM technology. And because of metal / insulation σ 479353

$ Metal capacitors are not easy to react at their interfaces, and can provide a high storage "valley", which can be fully used in the future dram process. It is not easy to have a very high definition in the research and specialized structure. Controlling will lead to a low-integrity system made of silicon. Due to the flow of platinum metal materials, it is widely used in electrode or contact plug materials. For the manufacturing process, it is difficult to refine the absolute dimension of the process. When using the previous materials, its extremely capacitive material characteristics, and the oxidation resistance and lower leakage electricity utilization of the previous BST capacitor manufacturing technology are reduced, and a large number of them are used in capacitor storage. However, in the current relevant aspects There are many difficulties in metal materials. For example, the current money engraving pattern is used to turn metal, which is related. In addition, platinum metal is extremely expensive, and the cost increases. Moreover, the use of platinum gold reacts and changes the yield of the interface. Cun Lei ^ Wai 'As the dimensions of the components continue to shrink, in the production of capacitor storage, and the aspect ratio of the contact hole facing when contacting congestion often becomes : The filling becomes more silvery, and it is easy to contact = good for the current typical Yan plug process: two = characteristics. Especially the interface effect, & carrying out crane metal sinking "belongs to Shi Xidi The barrier layer composed of "Material" / Iridium Nitride will be formed by titanium when contacted with the wire, and the aspect ratio between them will become more T and the hole becomes more difficult. In addition, the above: the filling material of the base material is made to make it to have a more uniform coverage characteristic. But for

479353

For the production of titanium metal layer, 'it can only be produced by physical vapor deposition method', it is because its step coverage ability is very poor, and it is easy to cause voids. The purpose and summary of the invention is to provide a method using platinum metal. Method for making metal / insulation / metal (MIM) capacitors. ^ Another object of the present invention is to provide a method for using a ruthenium metal film as the t layer to deposit platinum metal in a contact hole as a platinum metal plug. The present invention provides a method for manufacturing an integrated circuit capacitor. The method is as follows: step. First, a tungsten metal layer is formed on a semiconductor substrate, and a ruthenium metal thin film is formed on the tungsten metal layer. Next, an etching layer is defined to define contact on the semiconductor substrate. Heart gold = private layer on semiconductor substrate, ruthenium metal film and tungsten metal layer. An I θ nitride nitride film is deposited on the interlayer dielectric layer. Subsequently, it can be described that Shen and Lu pq Ren j etched the interstitial layer of the rat fossil thin amine thin s to form contact holes on the surface of the ruthenium metal thin film. Then, an electroless deposition process can be performed in the shape of Λ = =. Among them, the above-mentioned exposed ruthenium metal thin film can be filled by the ruthenium metal thin film by ion exchange process, and gradually fill the contact hole. The surface is 479353 V. Description of the invention (5) Two ... Chess and metal plug on the surface. The imperial system. On: the side wall, and the boat metal is deposited;; =: The partition wall is used in the crown type J soil, lice silicon film and platinum, and the emulsified silicon layer and nitrogen electrode are used. The surface of the plug is used as a capacitor. The photoresist layer is coated with platinum. The grinding process is performed until it reaches the oxidized stone: = After ’, a chemical mechanical part of the platinum metal film can be performed. Such as; = surface to remove part of the photoresist layer. Dielectric: Gold: = surface light: ~ Used for the top electrode of the capacitor. He died in the Wang Guo-type opening, and explained it in detail: Method Two difficulties in the process of making metal / insulation layer / metal capacitor = electric ore deposition process, and depositing the surname in the hole. . The detailed method of the present invention is as follows. ′ Please refer to the first figure. First, a semiconductor substrate 10 is provided for deposition.

ΙΗϋΙ 面 Page 8 479353 V. Description of the invention (6) ‘film. Among them, the semiconductor substrate 10 can be composed of a single crystal of a device < 100 > Generally speaking, other types of semiconductor materials, such as gal 1 ium arsenide, germanium, or siHcon On Insulator (SOI) on the insulation layer can also be used here. The semiconductor substrate 10 is used. In addition, since the characteristics of the surface of the semiconductor substrate 10 do not cause special effects to the present invention, the crystal orientation can also be selected as < 110 > or < 111 >. Next, a tungsten metal layer 12 may be formed on the semiconductor substrate 10. In the preferred embodiment, the tungsten metal layer 12 can be deposited by chemical vapor deposition or physical vapor deposition. In addition, for capacitors in DRAM devices, “the active area of the device can be defined before the tungsten metal layer 2 is deposited, and then it can be produced by defining the conductive layer pattern and performing the ion implantation process”. A plurality of gate structures used as word lines' and a source / drain region located between the gate structures. Because this part of the component or related manufacturing steps is not the focus of the present invention, it will not be described in detail here. After the tungsten metal layer 2 is formed, a ruthenium metal film 14 can be deposited on the tungsten metal layer 12. -Then, as shown in the second figure, the contact pad 16 shown in the figure can be defined on the semiconductor substrate 10 by using the remaining ruthenium metal film 14 and the tungsten gold metal layer 12. Next, an interlayer dielectric layer (ILD) 18 is deposited on the semiconductor substrate 10, the ruthenium metal film 14 and the tungsten metal layer 12 to cover the entire contact pad 16. Generally, the interlayer dielectric layer 18 here is made of BPSG material and TE0s oxide ^

479353 V. Description of the invention (7) --- The composite layer of materials. In a preferred embodiment, atmospheric pressure chemical vapor deposition (APCVD) or plasma enhanced chemical vapor deposition (PECVD) can be used first at a temperature of about 300 to 600. 〇, and a pressure of about 1 to Torr (Torr) in an environment to form a layer of a thickness of BPSG material. Then, ethyl acetate was used again (1 £ 03) at a temperature of 600 to 800. (: Occasionally, under a pressure of about 0.1 to 10 μm!), A TE0s oxide material layer is formed by chemical vapor deposition method, and then an interlayer dielectric layer is formed, and then a silicon nitride film is deposited. On the surface of the dielectric layer 18, in general.-Generally, this nitride film 20 can be used for low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical (PECVD) at a temperature of about 400 to 80. 〇. (: Formed in the environment. The interlayer dielectric layer 18 is formed, and the contact hole 22 is formed in ruthenium Λ. 'A photoresist material can be coated on the nitride film first, and then lithographic exposure and development are performed. , Cleaning and other procedures, and the case is in the photoresistive material. Then, the photoresistive material can be used to sequentially etch the nitrogen below and interlayer 18 to define the contact hole 22. Please refer to the third figure, and then perform an electroless plating (electr0iess) sinking sequence to form a platinum metal plug 24 in the contact hole 22. Among them, ", the ruthenium metal thin exposed at the bottom of the contact hole 22 as a seed; (Seeding layer) so that atoms are deposited on ruthenium by ion exchange On the surface of the thin film 14, gold is gradually piled up to fill 479353. V. Description of the invention (8) The entire contact hole 22 is filled. It is worth noting that because of the electroless deposition process here, the sequence is used between materials. Ion-exchange characteristics are used for deposition. Therefore, during the deposition process, platinum atoms are grown only from the bottom of the contact hole 22, but not from the sidewall of the contact hole 22. In this way, the deposition The platinum atoms will be sequentially deposited on the bottom of the contact hole 22 in a layer-by-layer manner, completely avoiding the chance of voids. In general, nitrogen can be reached on the upper surface of the platinum metal plug 24. The silicon film 20 is stopped, and the electroless deposition process is stopped. Then, a silicon oxide layer 26 is deposited on the upper surface of the nitrogen = silicon film 20 and the platinum metal plug 24, which is used as a subsequent definition of the capacitor and the insulating layer of the storage electrode. In the embodiment, a chemical vapor deposition (CVD) method can be used to produce the required oxygen with a tetraethyl silicate portal rib at a pressure of about o.um: 2 ° to w, refer to the fourth Figure, etching silicon oxide layer 2 6 2〇 film 24 and a metal plug surface turned up,;

The semiconductor substrate is stacked. Among them, you can first apply the photoresist to: = ^ surface, and then define the Emperor II by lithography process. Then, use this photoresist layer as the last mask power;; Figure =: Etching, and define the crown-shaped opening in it. On: On the bottom surface. That is, two of the two deposition gasifiers

479353 V. Description of the invention (9) Next, the surface of the Shixi film 20 and the platinum metal plug 24 is etched (RIE) and defined to be nitrided in the silicon nitride part. The silicon nitride deposited platinum thin film 20 and the platinum electrode The process layer 36 in platinum is shown in the fifth figure, and the silicon nitride layer 30 is reactively etched to remove a part of the silicon nitride layer at the bottom of the opening pattern. The f spacer 32 is on the silicon oxide layer 26. On the sidewall. That is, the layers on the upper surface of the thin film 20, the platinum metal plug 24, and the silicon oxide layer 26 are removed to form a silicon nitride spacer 32. Then, a sinker film 34 is formed on the surface of the silicon oxide layer 26, the silicon nitride spacer 32, and the silicon nitride metal plug 24, so as to provide the use of the capacitor bottom defined later. After the platinum metal thin film 34 is deposited, the photoresist thin film 34 is then coated and filled in the crown-shaped opening 28. Subsequent grinding procedures The sidewalls of the photoresist layer 36 and the bottom of the device are electrically deposited. In comparison. Then it is filled in the emerald substrate 10 for the chemical mechanical surface to remove a portion of the photoresist material that can be left in the capacitor formed by the crown-shaped opening 28 and the film 34, and the silicon oxide layer 26 and the surface layer 38 can be made of BST material. The dielectric layer 38 is on the surface, and the top electrode is used. , As above, until the bottom of the and part. In the implementation of Rongdijia, the sinkable crown-type opening six pictures reached the oxygen metal surface, and the imperial layer 38 will be removed. In the example, the platinum deposit port 28 is shown, and the fossil evening layer film 34 is defined by the crown-type opening. The above-mentioned electrical metal layer 40 of platinum is used as the semiconductor 26 as described above. In this way, the thin film 34 in the metal port 28, the capacitance, the capacitance, and the capacitance are capacitors. Using the method of the present invention to make a platinum metal capacitor has many advantages. First of all, by making crane metal contact pads, it is possible to shorten the thickness of 479353. Filled metal should be emphasized, the metal thin film is used for metal plugging, and the surface is piled up as a cover layer to produce seeds. However, there can be five, description of the invention (10) the aspect ratio of the contact hole, and (process window) is above the layer, and the layer is layered). The ions of the ruthenium metal film are used to make the platinum atoms along the ruthenium metal. Plug. That is, the continuous platinum metal plug system: atomic adhesion and deposition will not produce any characteristics. The allowable value of the process error at this time is because in the present invention, tungsten gold is used as the cap layer (cap, the platinum atom and the electroplating process can be used to form the required platinum ruthenium metal thin layer, and the latter layer The function of the platinum metal plug, which is convenient for platinum, maintains the electrical conductivity of the connection. In addition, it is prevented as an electrical response. In addition, the difficulty of the capacitor is difficult, but it can be compared in the present invention. In the transfer process, the present invention deposits thicker gold through the use of nitrogen-cut sidewalls and nitrogen-cut films, which can effectively prevent the platinum metal layer of the bottom electrode and silicon atoms from occurring, as opposed to using a chemical mechanical polishing process in the present invention The fixed electrode is an absolute dimension that can effectively solve the precise control of direct etching of the platinum metal layer. Furthermore, because the thinner metal layer is used to form the bottom electrode of the capacitor, the thicker platinum metal is used in the conventional technology. Obviously, in addition to solving the problem of etching, the method for etching the layers can also avoid the cost. The present invention is illustrated above with a preferred example, but it is not intended to limit the present invention. God invention with an entity, only limited to this embodiment Seoul. Familiar with this 479353

Page 479353 Brief description of the drawings The above description and the many advantages of this invention can be easily understood through the following detailed description combined with the attached drawings, among which: the first contact hole in the semiconductor and the third electroless plating Shen the fourth crown type start; the fifth silicon nitride and the sixth flip metal. The picture shows the formation of tungsten on the semiconductor crystal substrate. The picture shows the semiconductor crystal contact pads. The picture shows the semiconductor crystal deposition program. The platinum picture shows the semiconductor crystal port. The silicon oxide layer diagram is a cross-sectional view of a semiconductor crystal gap wall on the open side and a semiconductor crystal constitutes a capacitor chip, showing the steps of stacking a metal layer and a ruthenium metal film according to the technology of the present invention; Steps of exposing the surface of a ruthenium metal thin film; Sectional view of a sheet showing a step using a metal plug according to the present invention; Sectional view of a sheet showing a cross section of a step piece exposed to the surface of a platinum metal plug in the formation according to the present invention Figures showing the steps on a wall defined according to the invention; and sectional views of the sheet showing the steps of depositing a pole according to the invention. _

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Claims (1)

The scope of the six-application patent includes the following steps for the fabrication of integrated circuit capacitors. The method includes at least a Chenghe metal layer on a semiconductor / child product ruthenium metal film on a zirconium material, and etching the ruthenium-gold-tungsten metal layer; a conductor bottom. / Special film and the crane metal layer to define a contact pad on the semi-deposited interlayer φ film and the tungsten metal layer / to cover the semiconductor substrate and the ruthenium metal thin ": ί: 缚 ί 于On the interlayer dielectric layer; the ruthenium metal thin film table :: rhenium and the interlayer dielectric rhenium to form a contact hole in the middle; and perform an electroless core product procedure to form a molybdenum metal plug in the contact hole: an insulating layer Since the silicon nitride is thinly etched, the insulating sound occupies the upper surface of the metal insert; the surface of the metal plug; the θ y 幵 β case is on the silicon nitride film and the platinum gap on the sidewall of the opening pattern; The '= ... 1' is used to define the electric power = cut the thin film and " l accumulate the dielectric layers on the surface of the starting metal thin film and the insulating layer; deposit a platinum metal layer on the capacitor dielectric crown opening In order to define the capacitor top = face and fill in the emperor Page 16 479353 VI. Method of applying for the scope of the patent application of the thin film H application / the scope of the first item 'wherein the aforementioned nail metal 溥, I as a seed layer (seecHng layer), so that the platinum H Ϊ ion exchange program' The surface of the ruthenium metal film is deposited upwards, and is gradually filled in the contact hole. 3. The method according to item 1 of the scope of the patent application, wherein the above-mentioned thick gate eight electrical layer is composed of a BPSG material and a TEOS oxide material. "&Quot; 4 · If the method of applying for the first item of the patent scope, AL + is composed of silicon oxide material. The method of the second layer of the above-mentioned insulation layer is as described in the second section of the application? The above nitride shape: ΪΪ The pattern sidewall includes at least the following steps: the nitride: the = sidewall and bottom surface of the pattern; and the sub-neodymium engraving at the bottom of the pattern to remove the sidewall located on the opening insulation layer The method of forming the silicon nitride spacer on the bottom of the device is the first method of the W4 patent scope of the device, wherein the above-mentioned definition of the capacitor deposition surface: the method further includes the following steps: a silicon film and the molybdenum edge layer; Silicon spacer Among the nitrogen; belong to / find the film, and fill in the opening pattern. Page 17 6. Apply for a patent on the chemical mechanical film of the semiconductor substrate. And the meaning is that the photoresist layer on the bottom of the capacitor on the surface of the opening pattern is electrically removed to remove the remaining photoresist layer. 7 · As in the method of applying for the first item of the patent scope, the Gan 1 electrical layer is made of BST material. The above-mentioned capacitor dielectric 8 · The production of an integrated circuit capacitor includes the following steps: I fabricate 0. This method includes at least forming a tungsten metal layer on a semiconductor substrate; depositing a ruthenium metal film on the tungsten metal layer · Etching the ruthenium metal film and the tungsten metal acoustic conductor substrate; adding a sense contact pad to the semi-deposited interlayer dielectric layer on the semiconductive tungsten metal layer; a sacrificial exhibition material, the ruthenium metal film and the The silicon nitride film is deposited on the interlayer dielectric layer. The silicon nitride film and the interlayer dielectric are etched on the surface of the ruthenium metal film; Ί " electrical layer to form a contact hole and perform an electroless deposition process to form In which, sincerely, 貘 From—, the human metal plugs in the contact hole of the -Metal Cross :: can be used as a seed layer for the deposition, and gradually fill the contact hole; from the nail metal film surface Go to page 18, apply for a patent. The surface of the nitride film is etched on the surface of the nitride film and the #metal plug. The surface of the platinum oxide plug is 6 hours. The surface of the platinum metal plug is 711. Type 711 is opened on the silicon nitride film and the silicon nitride film. I ^ Shi Xi Fa1 p Song wall on the side wall of the crown-shaped entrance; "film and gap wall, for this purpose; clothing upwards, as a capacitor bottom electrode in the crown-shaped opening of the photoresist layer on the The turned metal film is filled with a chemical mechanical polishing process until a part of the photoresist layer and a part of the metal cutting layer are removed to remove the remaining photoresist layer; Layer on the flip metal thin film; and the "silicon layer" on the surface of the silicon layer is deposited on the surface of the capacitor dielectric layer in a 怼 -type opening to use as the top electrode of the capacitor; Person 2 The method of claim 1 in the patent scope, wherein forming the interlayer dielectric layer includes at least the following steps: depositing a BPSG layer on the semiconductor substrate to cover the surface of the contact pad; JSL depositing a TEOS oxide on the BPSG layer Above.