經濟部中央標準局員工消費合作社印製 415002 Λ7 B7 五、發明説明（1 ) 本發明係有關於半導體記憶逋的製造，且特別是有 關於一種半導體記憶體之多重錨型電容器的製造方法， 其利用酸存在情況下摻雜與未摻雜絕緣層的蝕刻率差異 性，來形成多重錨之構造，以提升電容器的電容量。 半導體記憶體是一種廣泛應用的積體電路元件，其 中動態隨機存取記憶體（DRAM)在今日資訊電子產業中 更佔有極重要的地位。隨著製程技術的演進，目前生產 線上常見的動態隨機存取記憶單元（DRAMcell)大多是由 一電晶體T和一電容器C所構成，切第1圖的電路圖所 示者。基本上，電晶體T的源極（source)係連接到一對應 的位元線（bit line)BL，汲極（drain)連接到電容器C的儲 存電極（storage electrode)，而閘極（gate)則連接到一對應 的字元線（word line)WL，電容器C的相對電極（opposed electrode)係連接到一固定電壓源，而在儲存電極和相對 電極之間則設置一介電層。如熟習此藝者所知，電容器C 是用來儲存電荷以提供電子資訊的，其應具有足夠大的 電容量，方可避免資料的流失並減低充電更新（refresh) 的頻率。 在傳統少於一百萬位元（1MB)的DRAM元件製程 中’一般多利用二度空間構造的電容器來儲存資料，亦 即泛稱的平坦型電容器（planar-type capacitor)。然而，平 坦型電容器需佔用相當大的基底面積，方足以提供足夠 的電容量，故並不適於目前日益高度積集化之DRAM元 件的製程》因此，高度積集化的DRAM元件，例如大於 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） ---------^---.---iliT------1 - - : (請先閲讀背面之注意事項再填寫本頁) 415002 Λ7 B7 經濟部中央標準局員工消費合作.杜印裝 五、發明説明（2) 一千六百萬位元（16M)的儲存容量者，必須利用三度空間 結構的電容器來實現，例如所謂的溝槽型（trench_type)或 叠層型（stack-type)電容器記憶元件β其中，由於蝕刻溝 槽來製作電容時不可避免地會在基底產生晶格缺陷 (defects),造成漏電流的增加而影響元件性質，並且隨著 溝槽縱橫比（aspectratio)的增大，其蝕刻速率亦將遞減， 不僅製程難度增加也影響了生產效率，因此實際生產線 上使用此類溝槽型電容器製程的並不普遍。相反地，疊 層型電谷器5己憶元件的製程則不會有上述缺點，因此許 多技術研發均係針對此一型式的記憶元件進行改良，用 以達到在記憶元件尺寸縮小時，仍能確保提供足夠大之 電容量的目的。 為了提咼電容器C的電容量’可從兩個方向著手： 一是減小介電層的厚度’一是增加儲存電極的表面積。 在減小介電層的厚度方面，現今製造的記憶元件電容器 均已使用極薄之介電層，然而其厚度並非可無限制地減 小’當介電層的厚度小於50A時，即可能因直接載子陡 穿（direct carrier tunneiing)而產生過大的漏電流，影響元 件的性質。因此，許乡研發都致力於増茄鈕存電極的表 面積，藉以提升電容器的電容量。 ， 第2A至2C圖的剖面圈，即分別顯一 土種習知疊層 1 I 型電容器’說明其製程和構造上的特徵首先，請參見 第2A圖，在一半導體基底1〇上形成一接觸區12，例如 是在一梦晶圓上形成一電晶體，包含閘極、源極區、和 (請先閱讀背面之注意事項再填寫本頁) •I衣· 訂 ί. 本紙張尺度適用中國國家標準（CNS ) A4^格（2)〇x297公釐） 415002 Λ7 B7 五、發明説明（3) 汲極區’其中源極區或没極區之一為圖中所示之接觸區 12。接著，形成一平坦化層13，例如是以化學氣相沈積 程序沈積的硼磷矽玻璃（BPSG)層，覆蓋在前述電晶體的 表面上。以微影成像和钱刻程序在平坦化層13中形成一 接觸窗14 ’露出半導體基底10中的接觸區12。其後， 形成一導電插塞11 ’例如是以沈積和回姓刻程序形成一 複晶石夕插塞，填滿接觸窗14 ’藉以和接觸區12形成電 性連接。 接下來，形成第一導電層15，例如是以化學氣相沈 積（CVD)程序形成一掺有雜質之複晶矽層，覆蓋在導電插 塞11和平坦化層13表面上。經由微影成像和蝕刻程序 定義其圖案’形成如圖所示之平台狀構造，構成一電容 器的儲存電極15。接著，在儲存電極15表面上形成一 介電層16 ’例如是氧化矽層、氮化矽層、氮氧化矽滑、 或氧化纽（Ta2〇5)層。之後，在介電層16上形成第二導電 層，例如，以CVD法沈積另一複晶矽層，經微影成像和 餘刻程序定義圖案’形成一電容器的相對電極17，即完 成一平台式疊層電容器C的製造》 隨著元件持續縮小化，上述平台式電容器已不敷所 需’因此一種皇冠式疊層電容器被提出，如第2B囷之剖 面圊所示。基本上，其製造程序與前述平台式電容器者 相似，惟其儲存電極15係成為一皇冠狀構造，因此較平 台式電容器增加内、外側壁之接觸面積，（與平台式電容 器相比較）可達到提高約兩倍電容量的功效。 本纸張尺度適财關祕（21〇><297公釐> 力衣1T^.— (請先閲讀背而之ΐί意事項再填寫本頁) 經濟部中央標準局員工消費合作社印聚 415002 經濟部中央標準局員工消费合作社印製 Λ7 B7 五、發明説明（4) 然而’當製程技術進展到次微米（sub-micron)甚至是 深次微米（deep sub-micron)領域時，必須進一步増加儲存 電極的表面積’方能提供足夠之電容量。第3C圖所顯示 者’即係對皇冠式疊層電容器作改良，利用在導電層表 面上沈積半球型石夕晶粒（HSG) ’以形成粗縫的表面來增加 儲存電極15的表面積，（與平台式電容器相比較）可達到 提高約四倍電容量的功效。 雖然由皇冠式疊層電容器技術演進到HSG皇冠式昼 層電容器技術，可以有效地提高電容量，而符合元件縮 小化的需求。然而，前述製造電容器的程序亦漸漸趨於 複雜，其製程的操作條件也更為嚴苛，不僅增加製程的 困難度，也影響了生產效率。 有鑑於此，本發明一個目的在於提供一種半導體記 憶體電容器的製造方法’可確保所佔平面尺寸持續縮小 的情況下，仍能維持足夠高的電容量。 本發明另一個目的，在於提供一種半導體記憶體電 容器的製造方法，其可在簡化製程步驟的同時，仍能保 有較寬的製程處理之操作範圍》 為了達成上述目的，本發明提出一種半導體記憶體 之多重錨型（Multi-Anchor)電容器的製造方法，其先交互 地沈積摻雜與未摻雜之絕緣層以形成堆疊絕緣層，並使 用含有光酸產生成分（photoacid generator, PAG)的光阻層 當作罩幕’在提供紫外光輻射環境下，藉由播雜與未摻 雜之絕緣層蝕刻速率的差異，形成多重錨形狀之開口側 本紙張尺度適用中國國家標準（CNS ) A4規格（210/297公楚> (請先閲讀背面之注意事項再填寫本頁} 裝· -Φ 415002 A7 ________________ B7 五、發明説明（5) 壁’使得後續沿著開口側壁生成之電容器也具有多重錨 形狀’達到增加電極表面積以提昇電容量的效果》 經濟部中央標隼局員工消費合作杜印製 (請先閱讀背面之；S意事項再填寫本頁) 根據本發明的較佳實施例，一種半導體記憶體之多 重錨型電容器的製造方法，包括下列步驟：（a)提供一半 導體基底，其上形成有一電晶體，以及一平坦化層，覆 蓋在電晶體上；（b)在平坦化層中形成一接觸窗，用以露 出電晶體的接觸區；（c)形成一導電插塞填滿接觸窗，並 與接觸區作電性連接；（d)形成一堆疊絕緣層於導電插塞 和平坦化層表面上，其係由至少一禾摻雜絕緣層和一摻 雜絕緣層交互堆疊而成；（e)塗佈一包含光酸產生成分之 光阻層於該堆疊絕緣層上，並形成一開口於該光阻層 中；（f)在提供紫外光輻射環境下，蝕刻堆疊絕緣層未被 光阻層蓋住的部分，以形成一堆疊絕緣層開口，其中光 阻層受紫外光輻射而產生酸離子，使得摻雜絕緣層的蝕 刻速率大於未摻雜絕緣層者，故堆疊絕緣層開口的側壁 係呈多重錨形狀；（g)去除光阻層；（h)形成一第一導電層， 覆蓋在堆疊絕緣層開口的底部和側壁上以及堆疊絕緣層 的表面上’並定義围案而與導電插塞共同形成一儲存電 極；⑴在存電極表面上形成一介電層；以及⑴在介電層 上形成一第一導電廣’並定義圖案而形成一相對電極， 完成多重錨型電容器的製造。 上述堆疊絕緣層中之未摻雜絕緣層，係以四乙氧基 矽甲烷(TEOS)為原料所沈積的氧化層，而摻雜絕緣層係 以四乙氧基矽甲烷為原料，並搀雜硼、磷離子所沈積的 本紙崁尺度適用中國國家標举（CNS ) A4規格（2IOX29：/公嫠） 經濟部中央標準局員工消費合作社印聚 415002 A7 ___________B7___ 五、發明説明（6) 氧化層。上述紫外光輻射可由蝕刻該堆疊絕緣層之機台 自然產生，也可以外加光源來提供該紫外光輻射。 為了讓本發明之上述和其他目的、特徵、及優點能 更明顯易懂’下文特舉一較佳實施例，並配合所附圖式， 作詳細說明如下： 圖式之簡箪說明 第1圖係一般DRAM中一記憶單元的電路示意圖； 第2A至2C圖均為剖面圖，顯示三種習知疊層型電 容器之構造； 第3圖顯是一種含有光酸產生成分（PAG)之光阻層 受到紫外光輻射的反應方程式；以及 第4A至4E圖均為剖面圖，顯示依據本發明多重錨 型電容器之製造方法一較佳實施例的製造流程。 實施例 首先’請參見第4A圖，在一半導體基底20，例如 是一矽晶圓上形成一電晶體’包含閘極、源極區、和汲 極區，而在圖中為了簡化圖式，僅顯示一接觸區22，代 表電晶體的源極區或没極區之一。接著，形成一平坦化 層23 ，例如是以化學氣相沈積程序沈積的硼磷矽玻璃 (BPSG)層，覆蓋在前述電晶體的表面上。以微影成像和 银刻程序在平坦化層23中形成一接觸窗24，露出半導 艘基底20中的接觸區22。其後，形成—導電插塞21 , 例如是以沈積和回蝕刻程序形成一複晶矽插塞，填滿接 觸窗24，藉以和接觸區22形成電性連接。 本紙張尺度適用中國國家標準（CNS ) A4現格（210X29?公瘦） ---------:柬— 1 (請先閱讀背面之注意事碩再填寫本頁) 訂 415002 A 7 -----------____ 五、發明説明（7) 接著，請參見第4B圖，在導電插塞21和平坦化層 23表面上交互地沈積摻雜與未摻雜之絕緣層，以形成一 疊層絕緣層50 ,例如：先以四乙氧基矽甲烷（TE〇s)為原 料，並利用電漿強化化學氣相沈積（pECVD)程序形成第 一未摻雜氧化層25a，再以TE〇s為原料，並摻雜硼磷 離子而沈積第一硼磷氧化層26a β然後，視實際需要而 反覆地施行上述兩程序，如本實施例所示者，依序又形 成了第二未摻雜氧化層25b、第二硼磷氧化層26b、以 及第三未摻雜氧化層25c，共同構成疊層絕緣層5〇。 在疊層絕緣層50的表面上塗佈一光阻層3〇，並以 微影成像程序定義圖案》形成一開口 31於光阻層3〇中。 應特別注意的是，光阻層30之材質必須有所選擇，基本 上其組成中必須含有光酸產生成分（PAG)才可，例如第3 圖之反應式所顯示者即為一例。當以紫外光輻射對光阻 層30曝光時，PAG產生的酸離子（H+)會使光阻層3〇中 的樹脂成分發生反應，例如圖中所示的斷鏈分解反應。 如此，即可利用光阻層30中曝光區與非曝光區之溶解度 的差異而定義出所需圖案。 經濟部中央標準局員工消費合作社印製 --------I •装----- I_1τ (請先閱讀背面之：a意事項再填寫本頁} 接下來’請參見第4C圖，利用光阻層3〇當作罩幕， 依序蝕刻堆疊絕緣層50中各層，用以形成一堆疊絕緣層 開口 33。其中，在蝕刻程序的同時，利用部分钱刻機台 會自然伴隨產生紫外光輻射，或是刻意以一外加光源提 供紫外光輻射，均可使當作罩幕的光阻層3〇因而產生酸 離子(H )’並隨蝕刻程序的進行而擴散到堆疊絕緣層開口 -9- __________ 本紙張尺度適财關家標準{ CNS ) A4規格（210Χ 297^$Τ^ -------—— 經濟部中央標準局員工消費合作社印製 415002 A7 _—一 . _ ____B7 五、發明説明（8) 33中。依據本發明研究的結果，上述光阻層3〇產生酸離 子（H )’會使得蝴碟氧化層26a、26b的飯刻速率大於未 摻雜氧化層25a、25b、25c者，因此堆疊絕緣層開口 33 的側壁會呈現凹凸的表面，稱之為多重錨構造。 請參見第4D圖，以適當溶液去除光阻層30»接著， 在堆疊絕緣層開口 33的底部和側壁上、以及堆疊絕緣層 5〇的表面上’形成第一導電層34與導電插塞21相連接， 例如是以化學氣相沈積程序沈積一複晶矽層，其中並可 摻植離子以提高其導電度。由於，第一導電層34係依堆 叠絕緣層開口 33的形狀而形成，因此前述多重錯構造便 轉移到第一導電層34上》 接下來’請參見第4E圖’以微影成像和银刻程序定 義第一導電層34之圊案，使其與導電插塞21共同形成 一儲存電極3536 ^接著，在儲存電極35的表面上成一 介電層36，例如是氧化矽層、氮化矽層、氮氧化矽層、 或氧化钽（Ta2〇5)層"然後，在介電層36表面上形成第二 導電層’例如，以CVD法沈積另一複晶矽層，經微影成 像和蝕刻程序定義囷案，形成一電容器的相對電極37， 即完成本發明多重錨型電容器C的製造。 綜上所述，本發明一種半導體記憶體之多重錨型電 容器的製造方法，其先交互地沈積摻雜與未摻雜之絕緣 層以形成堆疊絕緣層，並使用含有光酸產生成分 (photoacid generator，PAG)的光阻層當作罩幕，在提供紫 外光輻射環境下，藉由摻雜與未摻雜之絕緣層蝕刻速率 本紙張尺度通用中國國家標率{ CNS ) A4規格ί 2丨0Χ297公釐） (請先閲讀背面之：vi意事項再填寫本頁) 斧 、1Τ A7Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 415002 Λ7 B7 V. Description of the Invention (1) The present invention relates to the manufacture of semiconductor memory cells, and in particular to a method for manufacturing a semiconductor memory multi-anchor capacitor. The difference in etching rate between the doped and undoped insulating layers in the presence of an acid is used to form a multi-anchor structure to improve the capacitance of the capacitor. Semiconductor memory is a widely used integrated circuit component. Among them, dynamic random access memory (DRAM) has a more important position in today's information electronics industry. With the evolution of process technology, the dynamic random access memory cells (DRAMcells) currently on the production line are mostly composed of a transistor T and a capacitor C, as shown in the circuit diagram of Figure 1. Basically, the source of the transistor T is connected to a corresponding bit line BL, the drain is connected to the storage electrode of the capacitor C, and the gate It is connected to a corresponding word line WL. The opposite electrode of the capacitor C is connected to a fixed voltage source, and a dielectric layer is provided between the storage electrode and the opposite electrode. As known to those skilled in the art, the capacitor C is used to store electric charges to provide electronic information. It should have a large enough capacitance to avoid data loss and reduce the frequency of charge refresh. In the traditional DRAM device manufacturing process of less than one million bits (1MB), a capacitor with a two-dimensional structure is usually used to store data, which is generally called a planar-type capacitor. However, flat capacitors need to occupy a relatively large substrate area to provide sufficient capacitance, so they are not suitable for the current process of increasingly highly integrated DRAM devices. Therefore, highly integrated DRAM devices such as Paper size applies Chinese National Standard (CNS) Λ4 specification (210X297 mm) --------- ^ ---.--- iliT ------ 1--: (Please read the Please note this page, please fill in this page) 415002 Λ7 B7 Consumer cooperation of the Central Standards Bureau of the Ministry of Economic Affairs. Du Yinzhuang 5. Description of the invention (2) Those with a storage capacity of 16 million bits (16M) must use a three-dimensional space structure Capacitors such as trench_type or stack-type capacitor memory elements β, where lattice defects are inevitably generated on the substrate when the trench is etched to make a capacitor The increase of leakage current affects the properties of the device, and as the aspect ratio of the trench increases, its etching rate will decrease, which not only increases the difficulty of the process but also affects the production efficiency. Therefore, such trenches are used in actual production lines. groove Capacitor manufacturing process is not common. On the contrary, the manufacturing process of the memory device of the stacked type valley device 5 does not have the above disadvantages. Therefore, many technological developments are aimed at improving this type of memory device, so that when the size of the memory device is reduced, it can still be used. The purpose of ensuring a sufficiently large capacity. In order to increase the capacitance of the capacitor C, one can proceed in two directions: one is to reduce the thickness of the dielectric layer, and the other is to increase the surface area of the storage electrode. In terms of reducing the thickness of the dielectric layer, extremely thin dielectric layers have been used in memory element capacitors manufactured today. However, their thickness cannot be reduced indefinitely. When the thickness of the dielectric layer is less than 50A, it may be caused by Direct carrier tunneiing causes excessive leakage current and affects the properties of the device. Therefore, Xuxiang R & D is committed to the surface area of the storage electrode of the eggplant button to increase the capacitance of the capacitor. The section circles in Figures 2A to 2C, respectively, show a soil type conventional multilayer 1 I-type capacitor 'to explain its process and structural characteristics. First, refer to Figure 2A, forming a semiconductor substrate 10 The contact area 12 is, for example, a transistor formed on a dream wafer, including a gate electrode, a source region, and (please read the precautions on the back before filling out this page). Chinese National Standard (CNS) A4 grid (2) 0297 mm) 415002 Λ7 B7 V. Description of the invention (3) One of the drain region or the non-polar region is the contact region 12 shown in the figure . Next, a planarization layer 13 is formed, for example, a borophosphosilicate glass (BPSG) layer deposited by a chemical vapor deposition process, covering the surface of the transistor. A contact window 14 'is formed in the planarization layer 13 by lithography imaging and engraving procedures to expose the contact region 12 in the semiconductor substrate 10. Thereafter, a conductive plug 11 'is formed, for example, a polycrystalline spar plug is formed by a deposition and engraving process, and the contact window 14' is filled to form an electrical connection with the contact region 12. Next, a first conductive layer 15 is formed. For example, a polycrystalline silicon layer doped with impurities is formed on a surface of the conductive plug 11 and the planarization layer 13 by a chemical vapor deposition (CVD) process. The pattern 'is defined via the lithography imaging and etching process to form a platform-like structure as shown in the figure, and constitutes a storage electrode 15 of a capacitor. Next, a dielectric layer 16 'is formed on the surface of the storage electrode 15, such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a Ta2O5 layer. After that, a second conductive layer is formed on the dielectric layer 16, for example, another polycrystalline silicon layer is deposited by CVD, and the pattern is defined by lithography imaging and the remaining process to form a counter electrode 17 of a capacitor to complete a platform. "Manufacturing of multilayer capacitors C" With the continued shrinking of components, the above-mentioned platform capacitors are no longer sufficient, so a crown-type multilayer capacitor is proposed, as shown in Section 2B (2). Basically, its manufacturing process is similar to those of the above-mentioned platform capacitors, but its storage electrode 15 has a crown-like structure, so it can increase the contact area of the inner and outer sidewalls compared to the platform capacitors (compared to the platform capacitors). Approximately double the capacity of the capacitor. Secret of the financial standards of this paper (21〇 > < 297mm >) yiyi 1T ^ .— (please read the intent matters first and then fill out this page) Ju 415002 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 B7 V. Invention Description (4) However, when the process technology advances to the sub-micron or even deep sub-micron field, it must be Further increase the surface area of the storage electrode to provide sufficient capacitance. The one shown in Figure 3C is an improvement on the crown-type multilayer capacitor, which uses hemispherical stone grains (HSG) deposited on the surface of the conductive layer. To increase the surface area of the storage electrode 15 by forming a rough seam surface (compared to the platform capacitor), the effect of increasing the capacitance by about four times can be achieved. Although the technology of the crown laminated capacitor has evolved to the HSG crown day capacitor technology , Can effectively increase the capacitance, and meet the needs of shrinking components. However, the aforementioned process of manufacturing capacitors is gradually becoming more complex, and the operating conditions of its manufacturing process are also more stringent, Just increasing the difficulty of the process also affects the production efficiency. In view of this, an object of the present invention is to provide a method for manufacturing a semiconductor memory capacitor, which can ensure that the occupied plane size can be maintained sufficiently high while the occupied plane size continues to shrink. Capacitance. Another object of the present invention is to provide a method for manufacturing a semiconductor memory capacitor, which can simplify the process steps while still maintaining a wide operating range of process processing. "In order to achieve the above object, the present invention provides a A method for manufacturing a multi-anchor capacitor for semiconductor memory, firstly, doped and undoped insulating layers are alternately deposited to form a stacked insulating layer, and a photoacid generator (PAG) is used. The photoresist layer is used as a mask. Under the environment of providing ultraviolet radiation, the opening side of the multiple anchor shape is formed by the difference between the etching rate of the impurity and the undoped insulating layer. The paper size is applicable to the Chinese National Standard (CNS) A4 specifications (210/297) & (please read the precautions on the back before filling in this page) Installation · -Φ 41 5002 A7 ________________ B7 V. Description of the invention (5) The wall 'makes the subsequent capacitors generated along the side walls of the opening also have multiple anchor shapes' to achieve the effect of increasing the electrode surface area to increase the capacitance. According to a preferred embodiment of the present invention, a method for manufacturing a multi-anchor capacitor of a semiconductor memory includes the following steps: (a) providing a semiconductor substrate, A transistor is formed thereon, and a planarization layer covers the transistor; (b) a contact window is formed in the planarization layer to expose the contact area of the transistor; (c) a conductive plug is formed Full contact window and electrically connected to the contact area; (d) forming a stacked insulating layer on the surface of the conductive plug and the planarization layer, which is alternately stacked by at least one doped insulating layer and one doped insulating layer (E) coating a photoresist layer containing a photoacid generating component on the stacked insulating layer, and forming an opening in the photoresist layer; (f) under the environment of providing ultraviolet light radiation Etching the part of the stacked insulating layer not covered by the photoresist layer to form a stacked insulating layer opening, wherein the photoresist layer is irradiated with ultraviolet light to generate acid ions, so that the etching rate of the doped insulating layer is greater than that of the undoped insulating layer Therefore, the side walls of the opening of the stacked insulating layer are in the shape of multiple anchors; (g) removing the photoresist layer; (h) forming a first conductive layer covering the bottom and side walls of the opening of the stacked insulating layer and the surface of the stacked insulating layer 'And define a case to form a storage electrode with the conductive plug; ⑴ form a dielectric layer on the surface of the storage electrode; and ⑴ form a first conductive layer on the dielectric layer' and define a pattern to form an opposing electrode To complete the manufacture of multiple anchor capacitors. The undoped insulating layer in the above-mentioned stacked insulating layer is an oxide layer deposited using tetraethoxysilylmethane (TEOS) as a raw material, and the doped insulating layer is doped with tetraethoxysilylmethane as a raw material and doped The paper scale deposited by boron and phosphorus ions is applicable to the Chinese National Standards (CNS) A4 specification (2IOX29: / public money). The Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, Yinzhu 415002 A7 ___________B7___ 5. Description of the invention (6) Oxidation layer The above-mentioned ultraviolet radiation may be naturally generated by a machine for etching the stacked insulating layer, or a light source may be added to provide the ultraviolet radiation. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: Brief description of the drawings FIG. 1 It is a circuit diagram of a memory cell in general DRAM; Figures 2A to 2C are cross-sectional views showing the structure of three conventional multilayer capacitors; Figure 3 is a photoresist layer containing a photoacid generating component (PAG) The reaction equations under ultraviolet radiation; and FIGS. 4A to 4E are cross-sectional views showing a manufacturing process of a preferred embodiment of a method for manufacturing a multi-anchor capacitor according to the present invention. Embodiment First, please refer to FIG. 4A, a transistor formed on a semiconductor substrate 20, such as a silicon wafer, includes a gate electrode, a source region, and a drain region. In order to simplify the diagram, Only one contact region 22 is shown, representing one of the source or non-electrode regions of the transistor. Next, a planarization layer 23 is formed, for example, a borophosphosilicate glass (BPSG) layer deposited by a chemical vapor deposition process, covering the surface of the transistor. A contact window 24 is formed in the planarization layer 23 by lithography and silver engraving procedures, exposing the contact area 22 in the semiconductor substrate 20. Thereafter, a conductive plug 21 is formed, for example, a polycrystalline silicon plug is formed by a deposition and etch-back process to fill the contact window 24 so as to form an electrical connection with the contact region 22. This paper size applies Chinese National Standard (CNS) A4 now (210X29? Male thin) ---------: Cambodia — 1 (Please read the cautions on the back before filling this page) Order 415002 A 7 -----------____ 5. Description of the invention (7) Next, referring to FIG. 4B, alternately depositing doped and undoped insulation on the surfaces of the conductive plug 21 and the planarization layer 23 Layer to form a laminated insulating layer 50, for example, firstly using tetraethoxysilylmethane (TE0s) as a raw material, and using a plasma enhanced chemical vapor deposition (pECVD) procedure to form a first undoped oxide layer 25a, and then use TE0s as a raw material, and dope boron phosphorus ions to deposit a first boron phosphorus oxide layer 26a β, and then repeatedly perform the above two procedures as needed, as shown in this embodiment. A second undoped oxide layer 25b, a second boron-phosphorus oxide layer 26b, and a third undoped oxide layer 25c are formed to collectively constitute a laminated insulating layer 50. A photoresist layer 30 is coated on the surface of the laminated insulating layer 50, and an opening 31 is formed in the photoresist layer 30 by a pattern defined by a lithography imaging procedure. It should be particularly noted that the material of the photoresist layer 30 must be selected. Basically, its composition must contain a photoacid generating component (PAG). For example, the reaction formula shown in FIG. 3 is an example. When the photoresist layer 30 is exposed to ultraviolet light radiation, acid ions (H +) generated by the PAG cause the resin components in the photoresist layer 30 to react, such as the chain-breaking decomposition reaction shown in the figure. In this way, the difference in solubility between the exposed and non-exposed areas in the photoresist layer 30 can be used to define a desired pattern. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs -------- I • Equipment ----- I_1τ (Please read the back: a matter of interest before filling out this page} Next 'Please refer to Figure 4C The photoresist layer 30 is used as a mask to sequentially etch each layer of the stacked insulating layer 50 to form a stacked insulating layer opening 33. Among them, during the etching process, the use of a part of the money engraving machine will naturally be accompanied by Ultraviolet radiation, or deliberately providing ultraviolet radiation with an external light source, can cause the photoresist layer 30 as a mask to generate acid ions (H) 'and diffuse to the opening of the stack insulation layer as the etching process proceeds. -9- __________ This paper size is suitable for financial and family care standards {CNS) A4 specification (210 × 297 ^ $ Τ ^ ----------- Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 415002 A7 _— 一. _ ____B7 5. In the description of the invention (8) 33. According to the results of the research of the present invention, the above-mentioned photoresist layer 30 generates acid ions (H) ', which will make the etch rate of the butterfly oxide layers 26a, 26b greater than that of the undoped oxide layer. 25a, 25b, 25c, so the side wall of the stack insulation layer opening 33 will show unevenness The surface is called a multiple anchor structure. Please refer to FIG. 4D to remove the photoresist layer 30 with an appropriate solution. Then, the bottom and side walls of the stacked insulating layer opening 33 and the surface of the stacked insulating layer 50 are formed. The first conductive layer 34 is connected to the conductive plug 21, for example, a polycrystalline silicon layer is deposited by a chemical vapor deposition process, and ions can be implanted to improve its conductivity. Because the first conductive layer 34 is stacked, The shape of the insulating layer opening 33 is formed, so the aforementioned multiple fault structure is transferred to the first conductive layer 34. "Next, please refer to Fig. 4E. To form a storage electrode 3536 with the conductive plug 21, and then, a dielectric layer 36 is formed on the surface of the storage electrode 35, such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a tantalum oxide ( Ta205) layer "Then, a second conductive layer is formed on the surface of the dielectric layer 36 ', for example, another polycrystalline silicon layer is deposited by CVD, and a solution is defined by a lithography imaging and etching process to form a capacitor. Opposite electrode 37 is completed The manufacturing of the multi-anchor capacitor C of the present invention. In summary, in the method for manufacturing the multi-anchor capacitor of the semiconductor memory of the present invention, firstly doped and undoped insulating layers are alternately deposited to form a stacked insulating layer, A photoresist layer containing a photoacid generator (PAG) is used as a mask. Under the environment of providing ultraviolet radiation, the etching rate of the doped and undoped insulating layers is common. Rate {CNS) A4 specifications ί 2 丨 0 × 297 mm) (Please read the back of the page: vi intentions before filling out this page) Axe, 1Τ A7
415002 五、發明説明（9 ) 的差異性’形成多重錨形狀之開口側壁，使得後續沿著 開口側壁生成之電容器也具有多重錨形狀，達到增加電 極表面積以提昇電容量的效果。 本發明雖然已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明 之精神和範圍内，當可作些許之更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所界定者為準。 ----------衣---·--Γ-ιτ------妓— (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標嗥局員工消费合作社印繁 -U- 本纸張尺度顧 (eNS > --~~~—415002 V. Differences in the description of the invention (9) ′ The opening side walls with multiple anchor shapes are formed, so that subsequent capacitors generated along the opening side walls also have multiple anchor shapes, which has the effect of increasing the surface area of the electrodes and improving the capacitance. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. ---------- Cloths --- · --Γ-ιτ ------ Prostitute— (Please read the notes on the back before filling this page) Staff Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs印 繁 -U- This paper size Gu (eNS >-~~~ —