TW413931B - Manufacturing method of the crown-type capacitor in DRAM cell - Google Patents

Abstract

There is disclosed a manufacturing method of the crown-type capacitor in DRAM cell. The method utilizes a selective etching process to transform the flat sidewall of a stack structure into a ragged shape. Then, the stack structure is used as a model to transfer the ragged sidewall to the protrusions of the bottom electrode in the crown-type capacitor. Therefore, the surface area of the top and bottom electrodes can be increased, such that the crown-type capacitor is able to have a large capacitance.

Description

413931 V. Description of the invention (1) The present invention relates to a method for manufacturing a semiconductor memory element, and more particularly to a method for manufacturing a crown capacitor of a dynamic random access memory (DRAM). Dynamic random access memory is a widely used integrated circuit component, especially in today's information electronics industry. With the evolution of technology, the DRAM memory cells commonly used in production lines are mostly composed of a transistor T and a capacitor C, as shown in the circuit diagram in Figure 1. The source of the transistor T is connected to a corresponding bit line (BL) and the drain is connected to the upper electrode of a capacitor c, and the gate is Connected to a corresponding word line (WL), the lower electrode of the capacitor C is connected to a fixed voltage source 'with a dielectric layer between the upper and lower electrodes. Capacitance Frequency. Reduce the number of dielectric layers. However, the current capacity of 50A tunnel is used to store electronic information in container C, which should be large enough to avoid data loss and reduce charging refresh. The capacitor c can be increased in two directions. Capacitance, one is the thickness of the electrical layer, one is to increase the surface area of the upper electrode. In terms of reducing the dielectric thickness, the capacitors manufactured today have used extremely thin dielectrics and their thickness cannot be reduced indefinitely. When the thickness of the dielectric layer is small, it is extremely possible. • Because of direct carrier tunneling (direct carrier ing ) And generate excessive leakage current, which affects the properties of the device. Therefore, R & D is committed to increasing the surface area of the upper electrode to increase the capacitance and improve the quality of the component. In traditional DRAM processes with less than 1 million bits and 1 MB, more

413931 V. Description of the invention (2) '~ = Use a two-dimensional capacitor to store data, which is also known as a planar-type capacitor. However, planar capacitors use a substrate-a relatively large area to form the upper electrode, and 7Λ is sufficient: capacitance, so it is not suitable for the current process requirements of increasingly highly integrated DRAM devices. Usually 'highly integrated DRAMs, such as those with a storage capacity greater than 16M bits', need to use a three-dimensional capacitor structure, such as a trench type or a! Stack type capacitor memory IT · 〆 .Pieces. And when the grooves are used to make capacitors, lattice defects will inevitably be generated on the substrate, which will increase the leakage current and affect the properties of the components. As the aspect ratio of the grooves increases, the remaining The rate will decrease 'not only increases the difficulty of the process, but also affects the production efficiency'. Therefore, the application of the process of the groove type capacitor in the actual production line has its difficulty. In contrast, the manufacturing process of stacked capacitors does not produce the above disadvantages. In the memory elements of various stacked capacitors, the electrodes have a crown-type capacitor structure that protrudes upwards, because the inner and outer surfaces can provide effective The capacitor area is quite suitable for manufacturing highly integrated components, especially memory devices larger than 64MB bits. Therefore, many technologies have been modified for this form of crown capacitor to achieve the purpose of ensuring a sufficient capacitance when the component size is reduced. Therefore, an object of the present invention is to provide a method for manufacturing a crown capacitor, which can achieve the purpose of increasing the capacity of a dynamic random access memory. According to the above purpose, the present invention and the present invention propose a dynamic random access memory list

Page 5 413931 V. Description of the invention (3) The manufacturing steps on the base of the crown-shaped capacitor body: the insulating layer on the base opening; the insulating layer and the conductive body form a second opening in the second opening and the first opening; The first conductive layer is formed on top of a dielectric layer to be used as the above-mentioned crown-shaped capacitor base substrate according to the above-mentioned unit. The steps are as follows: the above-opened insulating layer, the above-mentioned insulating layer and the upper etching stop layer are formed one less. Stacked layers; etch stop layer in two openings to define and remove a part of the second opening mentioned above, and form a kind of capacitor having at least one of the above-mentioned to form a sacrificial layer capacitor in addition to the above-mentioned lower electrode layer It is used for the formation of the above-mentioned access to the upper and upper layers—the money-carved animal layer and the above pile; through the connection of the contact-cut port, the conductive element of the switching element that becomes the upper switching element is removed; the sacrificial layer of the above range; The second state randomly stores the switching element manufacturing method. The switching element takes half of the memory element and includes the first conductive plug of the lower part; The above barrier layer; the second sacrificial stack inner shape, the second barrier layer being exposed to the above-mentioned stacking layer, the manufacturing of the coronal electricity, and the coronal electricity base being formed on the first plug to define the above-mentioned formation within A guide to the above-mentioned crown; and a shape of the above-mentioned crown-shaped base for the manufacture of the capacitor; the above-mentioned conductive plug is formed with at least the above-mentioned conductivity and the above-mentioned capacitor is a sacrificial layer, so that the first method is applicable, The container has a plurality of layers of the above-mentioned coronal sacrificial layers interconnected within an opening σ; the above-mentioned dielectric upper electrode of the capacitor is removed. Ming proposed another method, the capacitor, so that the first opening plug is formed with a range of the first sacrificial plug on the device; remove the above-mentioned second open conductive layer ;, a conductive layer of the semiconductor includes the following. The first stopper; the sacrifice layer described above; removing the position; the upper conductive layer of the lower electrode mentioned above, the first opening of the layer is exposed to the top stopper; and

Page 6 413931 7 * ": —___ _____ 5. Description of the invention ~ I electrode; forming a dielectric layer on the above lower electrode; and forming a second conductive layer on the above dielectric as the above-mentioned crown capacitor In order to make the above-mentioned objects and features of the present invention more obvious and easy to understand, the following specific embodiments of the present invention are described in detail with the accompanying drawings as follows: Brief description of the drawings Fig. 1 is a schematic circuit diagram of a general dynamic random access memory unit; Figs. 2 to 7 are cross-sectional diagrams for explaining a manufacturing process according to a preferred embodiment of the present invention. Symbol description r 1 0 ~ substrate; 1 2 ~ field oxide layer; G ~ gate structure: 2 0 ~ gate spacer; 22 ~ source / drain region; 24 ~ insulating layer; 26 ~ conductive plug; 28 ~ Resistance barrier layer; 30 ~ borophosphosilicate glass layer; 32; silicon oxynitride layer; 34 ~ borophosphosilicate glass layer; 36 ~ silicon oxynitride layer; 40 ~ first stack structure: 40 '~ second stack Structure; 40 * first opening; 41, ~ second opening; 4 2 ~ first conductive layer, 46 ~ dielectric layer; 48 · • second conductive layer. Embodiments The method for manufacturing a crown capacitor using a dynamic random access memory unit according to the present invention can be implemented on a memory element, for example, a metal oxide semiconductor field effect transistor (MOS transistor) with N channels is used as a switching element. DRAM cells. However, the method for manufacturing the crown capacitor of the dynamic random access memory cell described in the present invention can also be applied to a MOSFET device with p-channels. * 凊 Refer to FIG. 2 which shows the beginning of the present invention. The first step is to first provide a semiconductor substrate 10, where the p-type silicon substrate with a lattice orientation of < 100 > is

413931 V. Description of Invention (5) Example. An oxide layer 12 is formed on the substrate 10 by a thermal oxidation process, such as a local oxidation method (LOCOS), to define an active area that will form a memory cell. Next, a gate oxide layer 14, a polycrystalline silicon layer 16 and a lithographic crane layer (WS ix) 1 8 are formed in sequence. The above-mentioned layers are etched using lithography and anisotropic etching and etching procedures. 'To form a gate structure G ^ Next, a lightly doped source / drain region is formed next to the gate structure G, for example, using the gate structure G as a screen' Ion implantation such as phosphorus or arsenic n-type doping The source is formed by entering the semiconductor substrate 10. A spacer (s p a c e r) 2 0 ′ is then formed on the sidewall of the gate structure G, such as depositing and anisotropically etching back an insulating layer. Afterwards, a heavily doped source / drain region is formed 'to complete the fabrication of the source / drain region 2 2 < For example, using a spacer 20 as a mask' I-implanted N-type doped source with a higher concentration 'such as Scales or arsenic enter the semiconductor substrate 10. So far, the manufacture of a transistor element is completed. Then deposit at least one insulating layer 'on the above-mentioned substrate 10 including the transistor element to isolate the transistor from the subsequent conductive layer, and provide a flat surface that is beneficial to the subsequent process, and the necessary wires can be made between different element designs. . For example, an insulating layer 24 is formed on the substrate. The insulating layer 24 may be a borophosphosilicate glass layer, a phosphosilicate glass layer, a borosilicate glass layer, or a silicon oxide layer, and then a lithography technique and a remaining process are used to form a first- [opening (not labeled) 'in the insulating layer 24. The source / drain region 22 of the transistor is exposed. Then, a conductive plug 26 is formed in the opening, thereby forming an electrical connection with the source / drain region 22. The conductive plug 26 may be composed of tungsten, tungsten silicide or doped polycrystalline silicon. Among them, tungsten is preferred. For example, after a layer of blanket 413931 is deposited on the insulating layer 24. 5. Description of the invention (6) Blanket Tungsten, a portion of the metal tungsten covering the surface of the insulating layer 24 is removed by a dry contact etch step, and a tungsten is completed. Plug it. Production. After that, an etching stopper 28 is deposited on the insulating layer 24 and the conductive plug 26 described above. The etching stopper layer 28 is preferably made of silicon nitride. Next, see Figure 3. A plurality of stacked layers are deposited on the etch stop layer 28, and the above stacked layer is composed of a dish; a glass layer and a oxynitride layer; and the number of the above stacked layers is about 1.0. It ’s better to take two stacked layers as an example. A borophosphosilicate glass layer 30, a nitrogen oxynitride layer 32, a glass filling layer 34, and a silicon nitride oxide layer 36 are sequentially deposited on the etch stop layer 28. Then, a first opening is etched to the layers 30, 32, 34 and 36 to define the range of the capacitor, and a first stacked structure 40 'with a flat sidewall is formed. The result is shown in FIG. Hereafter, referring to Fig. 4, it shows the important steps for carrying out the production of the crown electrode of the present invention. Implementation of the first stacked structure 40-an etching method that has a higher selectivity to borophosphosilicate glass than silicon oxynitride, so that the flat sidewalls of the stacked structure 40 are turned into irregularities. For example, a wet etching method based on 5% ". 5% diluted hydrofluoric acid (Diluted Hydrogen nUolaride, DHF) as the main etching liquid, because its selectivity to Shuishida Shixi glass and gas oxidation dream is ^ 3, so the above wet engraving method is used to deal with the problem-the concavity layer is more, so that the side wall of the first stacked structure 4 ° is transformed into 5 t. The barrier layer 28 is not covered by the stacked structure 40. The etch stop layer 28, the layer 30, the layer 32, the layer 34, and the yttrium constitute a second stacked structure 40 having a concave-convex sidewall. And form one

Page 9 ^ After a period of time, the removed borophosphosilicate is broken. 5. Description of the invention (7) The second opening 4 丨 which is in communication with the conductive plug 26 is shown in FIG. 4. For example to contain about 1 50 ~ 1 70. (: The thermal phosphoric acid is a wet etching method of an etching liquid to remove the etching stopper layer 28. After that, referring to FIG. 5, a chemical vapor deposition (CVD) method is used to deposit a compliance on the second-stacked structure 40 * ( confromal) first conductive layer 42 'which is connected to the conductive plug 26 through the second opening 41. The first conductive layer 42 may be a doped polycrystalline silicon layer, a tungsten layer, tungsten silicide, and titanium nitride Among them, the mixed crystal layer is better. Then, please refer to FIG. 6. Remove the upper conductive layer 42 from the second stacked structure 40 and form the upper electrode 42 of the crown capacitor of the present invention. The first conductive layer 42 is deposited by chemical vapor deposition (CVD), so the uneven sidewalls on the second stacked structure 40 will be transferred to the upper electrode 42, which will protrude upward to increase the surface area of the upper electrode. The invention capacitance can have a larger capacitance than the conventional capacitor. A photoresist 44 is formed on the _th conductive layer 42, and the photoresist 44 is filled with the photoresist 44 and the second stack structure by a chemical mechanical polishing method. 40。 The top surface. After that, the first yttrium yttrium structure 40, light Resist and etch resist the upper electrode 42 as shown in Fig. 6. It is as good as Fig. 6 and see Fig. 7 for a complete picture. It shows that the crown capacitor p of the moving capacitor is completely removed. Take g as the upper electrode 42, ^ T, first, conformally deposited on the surface of the dielectric electrode 42. Then, the dielectric layer 4βK + ^ conductive layer 48 is used as the lower Leitian 2; The fourth electrode 48 can be assembled into a ceramic | B 4, the upper electrode 42 ', the dielectric layer 46, and the mountain. The invention is a crown capacitor. The dielectric layer is not acceptable.

Page 10 413931 V. Description of the invention (8)

It is composed of materials with high dielectric constant such as fossil / nitride / oxide layer (ONO: oxide / nitride / oxide) or oxide group (Ta205). The second conductive layer 48 may be a doped polycrystalline silicon layer, a tungsten layer, a tungsten silicide layer, and a nitride. Among them, the doped polycrystalline silicon layer is preferred. Based on the above process, the upper electrode can be easily added. 42, the surface area 'provides greater capacitance. For example, prior to forming the dielectric layer 46, a plurality of hemi-spherical silicon grains (HSG) may be formed on the surface of the upper electrode 42 'by a conventional procedure, or a low-pressure vapor deposition method ( LPCVD) forms a rugged polysilicon structure, which can effectively increase the surface area of the upper electrode 42 ′. After that, a dielectric layer 46 and a second conductive layer 48 are sequentially formed to complete a capacitor for a dynamic random access memory cell. Because the method for manufacturing a crown capacitor of a dynamic random access memory unit proposed by the present invention has the following characteristics: no complicated lithography process steps are needed (the selective etching process can be used to fabricate electrodes with uneven sidewalls): and ( 2) Depending on the situation, it is necessary to increase the number of stacked layers to increase the capacitance, so it can meet the requirements of the next generation of high memory and effective space utilization. At the same time, those skilled in the art should understand that the material materials usable in the present invention are not limited to those cited in the examples, they can be replaced by substances and forming methods of appropriate characteristics, and the structural space of the present invention is not limited to The dimensions cited in the examples. 'Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes, modifications, and decorations without departing from the spirit and scope of the present invention. Therefore the protection of the present invention

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Claims (1)

413931 Six 'Scope of Patent Application 1. A method for manufacturing a crown capacitor of a dynamic random access memory cell' is suitable for manufacturing the above-mentioned crown-shaped electrical container on a semiconductor substrate having a switching element, and the above manufacturing method includes the following steps: On the above substrate Forming an insulating layer having a first opening and opening communicating with the switching element; forming a conductive plug in the first opening; forming a plurality of sacrificial layers on the insulating layer and the conductive plug; forming a first sacrificial layer in the sacrificial layer; Two openings to define the range of the crown capacitor; removing at least one of the f of the sacrificial layer in the second opening; forming a first conductive layer in the first opening; removing the sacrificial layer to make the first A conductive layer becomes the lower electrode of the crown-shaped capacitor; a dielectric layer is formed on the lower electrode; and a second conductive layer is formed on the dielectric layer to serve as the upper electrode of the crown-shaped container. 2. The manufacturing method described in item 1 of the scope of patent application, wherein the above-mentioned first conductive layer is composed of doped polycrystalline silicon. 3. The manufacturing method described in item 1 of the scope of patent application, wherein the second conductive layer is composed of doped polycrystalline silicon. '4_ The manufacturing method described in item 1 of the scope of patent application, wherein The above-mentioned insulating layer is composed of borophosphosilicate glass. · 5. The manufacturing method as described in the item of the scope of application for a patent, wherein the above Page 13 413931 6. The patented conductive plug in the patent scope is composed of doped polycrystalline silicon, metallic tungsten or siliconized silicon. 6. The manufacturing method described in item 5 of the scope of patent application, wherein The steps of at least one of the above-mentioned sacrificial layers are completed by a touch-engraving method with a difference in #selectivity between the pair of sacrificial layers. 7. · A method for manufacturing a crown capacitor of a dynamic random access memory unit 'suitable for manufacturing the above-mentioned crown capacitor on a semiconductor substrate having a switching element', and the above-mentioned manufacturing method includes the following steps: forming on the substrate having a connection to the switching element An insulating layer of the first opening; forming a conductive plug in the first opening; forming at least a stacked layer having at least a first sacrificial layer and a second sacrificial layer on the conductive plug and the insulating layer; A second opening is formed in the stacked layer on the conductive plug to define the range of the capacitor; a portion of the first sacrificial layer is removed through the second opening to form a first conductive layer in the second opening; The first conductive layer has a crown shape to form a dielectric layer on the lower electrode; and a second conductive layer is formed on the dielectric layer as the crown shape to form an upper electrode of the capacitor. The manufacturing method described in item 7 of the scope of the patent application, wherein the previous conductive layer is composed of doped multiple crystals and fragments. 413931 6. Scope of patent application 9. The manufacturing method as described in item 8 of the scope of patent application, wherein the second conductive layer is composed of doped polycrystalline silicon. -10. The manufacturing method according to item 9 of the scope of patent application, wherein the above-mentioned insulating layer is made of borophosphosilicate glass. 11. The manufacturing method according to item 10 of the scope of patent application, wherein the conductive plug is composed of doped polycrystalline silicon, metal tungsten or tungsten silicide. 12. The manufacturing method according to item 11 of the scope of patent application, wherein the step of removing a portion of the first sacrificial layer located in the second opening is performed by a pair of the first sacrificial layers having an etching selectivity greater than that of the second The sacrifice layer is processed by etching. 13. —A method for manufacturing a crown capacitor of a dynamic random access memory unit, which is suitable for manufacturing the above-mentioned crown capacitor on a semiconductor substrate having a switching element, and the manufacturing method includes the following steps: forming on the substrate having a connection to the switching element; An insulating layer of the first opening; forming a conductive plug in the first opening; forming an etch stop layer on the insulating layer and the conductive plug; forming at least a first sacrificial layer on the etch stop layer and At least one stack of plutonium layers of the second sacrificial layer forms a second opening in the stacked layer of the conductive plug to define the range of the capacitor; a part of the first sacrificial layer is removed through the second opening; A part of the etching layer is exposed on the second opening, and the second opening communicates with the plug; 413931 ---------------- " '—____ VI. The scope of the application for a patent forms a first conductive layer in the second opening; removes the stacked layer and the last-named insulation layer' Making the first conductive layer of the upper capacitor the lower electrode of the crown capacitor; forming a dielectric layer on the lower electrode; and-forming a second conductive layer on the dielectric layer to be used as the crown capacitor electrode. 14. The manufacturing method according to item 13 of the scope of the patent application, wherein the first conductive layer is composed of doped polycrystalline silicon. 15. The manufacturing method according to item 13 of the scope of patent application, wherein the second conductive layer is composed of doped polycrystalline silicon. ^ 16. The manufacturing method according to item 13 of the scope of the patent application, wherein the insulating layer is made of borophosphosilicate glass. 17. The manufacturing method according to item 16 of the scope of the patent application, wherein the conductive plug is composed of doped polycrystalline silicon, metal tungsten or tungsten silicide. 18. The manufacturing method according to item 17 of the patent application park, wherein the etching stopper layer is made of silicon nitride. 19. The manufacturing method as described in item 18 of the scope of the patent application, wherein the first sacrificial layer is composed of borophosphosilicate glass' and the second sacrificial layer is composed of hafnium silicon oxide. 20. The manufacturing method as described in item 19 of the scope of the patent application, wherein the step of removing a part of the first sacrificial layer through the second opening is based on-the etching selectivity of borophosphosilicate glass is greater than nitrogen The silicon oxide is etched and processed. 21. The manufacturing method as described in item 20 of the patent application scope, wherein- Page 16 413931 VI. Scope of patent application The narrative method adopts the impurity + wood dilute hydrofluoric acid solution. A dynamic random access method α is suitable for the manufacture of a crown capacitor with a switching element ^ early 7 " and the above manufacturing method includes the following steps + manufacturing a capacitor on a conductor substrate: ΐΪίΐΪ1 is formed to have -Forming a conductive plug in the first opening; forming a silicon nitride on the conductive plug and the insulating layer; forming at least one of a borophosphosilicate glass layer and a silicon oxynitride layer on the etching stop layer; A stacked layer; forming a second opening in the stacked layer on the conductive plug to define the scope of the capacitor; applying a pair of borophosphosilicate glass to the stacked layer via the second opening has a greater selectivity than silicon oxynitride The etching method removes part of the borophosphosilicate glass layer; removes the part of the etching stop layer exposed to the second opening, so that the second opening communicates with the conductive plug; and forms a first conductive in the second opening Layer, removing the stack layer and the etch stop layer to make the first conductive layer the crown capacitor A lower electrode of the device; forming a dielectric layer on the lower electrode; and forming a second conductive layer on the dielectric layer as the upper electrode of the crown capacitor. 23_ The manufacturing method described in item 22 of the scope of patent application, wherein the above Page 17 413931 VI. The scope of the application patent describes the conductive plug 24. Hydrofluoric acid with glass release from Rugao Butterfly 25. Stacked layer system 2 as described on the right 2 6. Such as ^ In addition to the above etching, doped polycrystalline silicon , Metal tungsten or tungsten silicide? Please refer to the manufacturing method described in item 22 of the patent, wherein the selectivity of / is greater than the above-mentioned method of oxynitride to the solution. V. Use the dilute manufacturing method described in item 24 of the patent, which uses a dilute hydrofluoric acid solution to remove it. 7. The manufacturing method described in item 7 of the above patent scope, wherein the step of the barrier layer uses a phosphoric acid solution. ,go with