TW417291B - Manufacture method of crown-type DRAM capacitor - Google Patents

Abstract

A manufacture method of crown-type DRAM capacitor suitable for a semiconductor substrate with switch device on it is disclosed. It comprises the following steps. (1) Sequentially form insulated and barrier layers on the above mentioned substrate and make a contact connected to the switch device through the insulated and cover layers. (2) Form the first conduction layer on the barrier layer and contact to link the switch device. (3) Make a groove to divide each memory cell area. Form a divider on the said groove sidewall and anisotropically etch the first conduction layer to barrier layer by using the sidewall as etch mask. The bottom electrode of the capacitor is formed. (4) Selectively etch the divider and form a dielectric layer smoothly covered the bottom electrode and insulated layer. (5) Form the second conduction layer as the capacitor top electrode.

Description

-HK91-- V. Description of the invention (1) The present invention relates to a method for manufacturing a semiconductor memory element, and particularly to a method for manufacturing a crown capacitor of a dynamic random access memory (DRAM). Dynamic random access memory is a widely used integrated circuit component, especially in today's information electronics industry. With the evolution of technology, the DRAM memory cells commonly used in production lines are mostly composed of a transistor T and a capacitor C, as shown in the circuit diagram in Figure 1. The source of the transistor T is connected to a corresponding bit line (BL) and the drain is connected to a bottom electrode of a capacitor C, and the gate ) Is connected to a corresponding word line (WL), a top electrode of the capacitor C is connected to a fixed voltage source, and a dielectric layer is separated between the lower electrode and the upper electrode. Capacitor C is used to store electronic information. It should have a sufficiently large capacitance ′ to avoid data loss and reduce the frequency of charge refresh. There are two directions to increase the capacitance of the capacitor C, one is to reduce the thickness of the dielectric layer ', and the other is to increase the surface area of the lower electrode. In terms of reducing the thickness of the dielectric layer, the capacitors manufactured today have used extremely thin dielectric layers, but their thickness is not unlimitedly reduced. When the thickness of the dielectric layer is less than 50 angstroms, it is extremely possible because of direct loading. The direct carrier tunnel ing causes excessive leakage current, which affects the properties of the device. Therefore, many researches and developments are focused on increasing the surface area of the lower electrode to increase the capacitance. In traditional DRAM processes with less than one million bits (1 MB), more

_ 417291____ 5 'Explanation of the invention (2) Storage of data by using second-degree capacitors', also known as planar-type capacitors. However, planar capacitors need to use a relatively large area of the substrate to form the lower electrode C in order to provide a sufficient amount of capacitance ', so they are not suitable for the current process requirements of highly integrated trending components. Generally, 'highly integrated DRAM', for example, having a storage capacity greater than 16M bits, requires a three-dimensional space capacitor structure, such as a trench-type or stack-type capacitor memory element. As the grooves are etched to make capacitors, lattice defects will inevitably be generated on the substrate, which will increase the leakage current and affect the properties of the elements. As the aspect ratio of the grooves increases, the etching will The speed will decrease, which not only increases the difficulty of the process, but also affects the production efficiency. Therefore, the application of the process of the groove type capacitor in the actual production line has its difficulty. In contrast, the manufacturing process of stacked capacitors does not produce the above disadvantages, so many technologies are improved for this form of memory elements to achieve the purpose of ensuring a sufficient capacitance when the size of the elements is reduced. In the memory elements of various stacked capacitors, a crown capacitor (cr0wn_typecapacitr) of the electrode part, because of its quotation: the effective capacitance area is quite suitable for manufacturing a high product, especially larger than 64MB bits. Memory element. > How to make a crown capacitor of a dynamic random access memory cell? Process: Adding the complexity of the process ′ This affects production efficiency. : Also simple and not: It is necessary to be strict in the control of process conditions, so it is not conducive to the implementation of the production line.

417291 V. Description of the invention (3) For a clearer explanation, please refer to Figs. 2A to 2C to explain the manufacturing process of a dynamic random access memory unit with a crown capacitor. As shown in FIG. 2A, an oxide layer 212 is formed on a semiconductor substrate 210 to define an actiVe region. Then it is sequentially formed—gate oxide layer 2 1 4, a polycrystalline silicon layer 2 1 5, a tungsten silicide (WS ix) layer 2 1 6, and an insulating layer 218 ′, and a gate is formed by etching to define a pattern. electrode) Structure g. Using this gate structure G as a mask, implanted impurities enter the semiconductor substrate 210 to form a lightly doped source / drain region. A gate spacer 220 is formed on the sidewall of the gate electrode structure G by a deposition and etch-back procedure, and then the gate structure g and the insulating spacer 220 are used as a mask, and a higher concentration of impurities is implanted into the semiconductor substrate 210 to The source / drain region 2 22 ′ is completed, and thus a transistor device is completed. Next, an insulating layer 2 2 4 is deposited on the surface of the transistor element, and then the insulating layer 2 2 4 ′ is planarized to form a planar surface which is favorable for subsequent processes. Then, a contact opening 228 is formed in the insulating layer 224 by a microlithography (lithography imaging procedure) to expose the source / and region 222 of the transistor. A first conductive layer 230 is then formed to cover the surface of the insulating layer 224 The contact opening 228 is formed and filled ′, thereby forming an electrical connection with the source / non-electrode region 222. Then, a plurality of shallow grooves 232 are formed on the first conductive layer 23 by using a lithography imaging and etching process, and exposed for use. To separate the regions of the memory cells. Then, an insulating spacer 234 is formed on the side wall of the shallow groove 232. Next, as shown in FIG. 2B, the insulating spacer 2 3 4 is used as a cover, and a non- The isotropic etching method etches the first conductive layer 2 3 0 so that it

Page 7 V. Description of the invention (4) The portion below the shallow groove 2 3 2 is completely removed to separate the range of each capacitor ', forming a crown-shaped lower electrode 230'. Then refer to Figure 2C to remove the green door spacer 234 using an anisotropic silver engraving procedure. A dielectric layer 238 'and an upper electrode 2 40 are sequentially formed on the surface of the lower electrode 2 30', and together form a capacitor. Obviously, the step of manufacturing the crown capacitor structure in the conventional method is to form a crown capacitor by using an insulating spacer 234 as an etching mask, and then removing the insulating spacer 234 by an etching process. In order to ensure that the insulating spacers 2 3 4 are completely removed, this money engraving step is usually engraved on the insulating layer 2 2 4 ′, which causes the flat surface of the insulating layer 2 2 4 to be damaged, which affects the properties of the component. In addition, because this etching process usually uses an anisotropic touch method, the shape of the spacer 234 will be transferred to the crown-shaped lower electrode 230, forming a sharp structure as shown in FIG. 2C, which easily causes the problem of the tip discharge of the crown capacitor. .

In view of this, the present invention proposes a method for manufacturing a dynamic random access memory unit with a crown capacitor, which mainly improves the aforementioned conventional method, and further deposits a shielding layer on the first insulating layer different from the insulating spacer material. . Therefore, in the step of removing the insulating spacer, the protection of the shielding layer can prevent the insulating layer from being etched, so that the surface can be kept flat. It is suitable for manufacturing capacitors on a semiconductor substrate with a switching element ', and the above manufacturing method includes the following steps: sequentially forming an insulating layer and a shielding layer on the substrate; forming an accessible layer in the insulating layer and the shielding layer. The contact opening of the switching element; on the shielding layer and

Page 8 417291 V. Description of the invention (5) A first conductive layer is formed in the contact opening to form an electrical connection with the switching element; a groove is formed in the first conductive layer to define a space for separation A region of each memory cell unit; a spacer is formed on a side wall of the groove; the spacer is used as a cover, and the first conductive layer to the shielding layer are engraved anisotropically to form the capacitor A lower electrode; selectively removing the spacer; forming a dielectric layer to cover the lower electrode and the insulating layer compliantly; forming a second conductive layer on the dielectric layer as the capacitor upper electrode. In order to make the above-mentioned objects and features of the present invention more comprehensible, several preferred embodiments are exemplified below and described in detail with the accompanying drawings as follows: Brief Description of the Drawings Figure 1 is a general dynamic random access memory The circuit diagram of the unit; Figures 2A to 2C are cross-sectional schematic diagrams' to explain the conventional manufacturing process of manufacturing a crown capacitor. 3A to 3E and 4 are schematic cross-sectional views for explaining a manufacturing process according to a preferred embodiment of the present invention. Explanation of symbols <Known technology> 21 0 to substrate, 2 2 2 to source and non-electrode regions, g to gate, 2 2 to gate spacers, 22 [first insulating layer, 230 to first conductive layer , 232 to four slots, 234 to groove spacers, 230 'to lower electrodes, 238 to dielectric layers, 24 to upper electrodes <Example> 300 to substrate, 322 to source and drain regions, H to Interpolar

Page 9 417291 V. Description of the invention (6) Spacer, 324 ~ first insulation layer, 326 ~ shielding layer, 330 ~ first conductive layer, 332 ~ groove '334 ~ groove spacer, 330' ~ lower electrode 338 ~ dielectric layer, 340 ~ upper electrode. Explanation of Examples Please refer to FIG. 3A, which shows the initial steps of the present invention. A semiconductor substrate 3 1 0 'is provided. Here, a p-type hair substrate having a lattice orientation of &lt; 100 is used as an example. An oxide layer 312 is formed on the substrate 310 by a thermal oxidation process, such as a local oxidation method (LOCOS), to define an active area that will form a memory cell. Next, a gate oxide layer 31 4, a polycrystalline silicon layer 31 5, a tungsten silicide layer (WSix) 316 and a silicon oxide layer 3 1 8 are sequentially deposited on the substrate, and then a photolithography technique and an anisotropic surname are used. The engraving procedure defines the above-mentioned layer patterns to form a gate structure. Next, a lightly doped source and drain region is formed next to the gate structure 11. For example, the gate structure is used as a mask, and an N-type dopant such as sulfon or arsenic is implanted into the semiconductor substrate 3 and formed. Then, a gate spacer 3 2 0 is formed on the side wall of the gate structure Η, and the surname-insulating layer is returned to complete it. The formation of "hybrid" pole regions is made by forming source and drain regions 3 2 2. For example, the gate spacer 320 and the gate structure η are used as a mask, and a high-concentration ^ -type dopant is implanted in the cloth, such as filling or 珅 'into the semiconductor substrate 3 10 to form. So far, the manufacture of a transistor element is completed. Next, at least one insulating layer is deposited on the substrate 3 10 including the transistor element to isolate the transistor from the subsequent conductive layer and provide a flat surface that is conducive to the subsequent process. The necessary components can also be manufactured according to different element designs. The lead is in between. For example depositing a first insulating layer on a substrate

Page 10 V. Description of the invention (7) After 3 2 4, a flattening procedure is performed to make the surface flat, as shown in Figure 3a. The first insulating layer may be a borophosphosilicate glass layer, which may be made of tetraethoxysilane (TEOS), 03/02, triethylborate (TEB), and trimethylsuccinic acid. Salt (tr i me thy 1 phosphate, TMP) was deposited by atmospheric pressure chemical vapor deposition (APCVD) of the reactants. The planarization technology may be after chemical-mechanical polishing. In order to ensure that the insulating layer is not etched during the subsequent process of removing the groove spacers, it is convenient to deposit a mask on the first insulating layer 324. Layer 326, in which the shielding layer 326 and the groove spacer 334 formed later are made of different materials, so when the groove spacer 334 is removed using a selective etching process, the groove spacer 334 and the mask are masked by the selective etching process described above. The difference in the etch rate of the layer 326 'so the shielding layer 3 2 6 can not be etched, and therefore has the effect of protecting the integrity of the first insulating layer. The shielding layer 326 may be a silicon nitride (Si3N4) layer, which may be produced by a low-pressure chemical vapor deposition method using SiH2Cl2 and NHS as the main reactants, and deposited to a thickness between about 400 angstroms and 800 angstroms. Better. After that, the masking layer 3 26 and the first insulating layer 324 are defined by a lithography technique and an anisotropic money engraving process to form a contact opening 328, which exposes the source and the transistor of the transistor: and the electrode region 3 2 2. The etching process may be performed using a reactive ion etch (RIE) method using carbon fluoride (CFO as the main etched reactive gas). Then, a first conductive layer 330 is formed to cover the surface of the shielding layer 326. And fill the contact opening 3 2 8 ′, so that subsequent components can form an electrical connection with the source region. The first conductive layer 330 may be a polycrystalline silicon layer, and silicon may be used.

Page U 417291 V. Description of the invention (8) '--- Methane (S1H4) is produced by low pressure chemical vapor deposition (LpcVD) as the main reactant' and is deposited to a thickness of about 15,000 angstroms to 3,000 Better between Egypt. To make the "electrical layer conductive", diffusion, ion implantation of arsenic or disk ions can be used, or synchronous doping can be used. Please refer to FIG. 3B, which shows the important steps for making the crown capacitor of the present invention. First, a photoresist layer (not shown) is formed to define the range of each capacitor. Then using this photoresist layer as a mask, the first conductive layer is anisotropically etched to a depth t1 'to form a shallow groove 332, which can define the area to separate the capacitors' and its depth can be determined Later the thickness of the lower electrode is formed. The depth of the groove 332 needs to be smaller than the thickness of the first conductive layer 330. The above-mentioned etching process can be performed using a reactive etch method (RIE) using carbon fluoride (Cf3) as the main etching reaction. After that, please refer to FIG. 3C, which shows the result of making a groove spacer 334 on the side wall of the groove 332. After forming a second insulating layer to conformably cover the groove 332 and the first conductive layer 330, the second insulating layer is etched back to the first conductive layer 330, leaving only the portion of the second insulating layer on the sidewall of the groove 332 ' It forms a groove spacer 334. The second insulating layer may be a non-doped silicon glass (NSG) layer, which may be made of tetraethoxy oxalate (161 ^ 36'1: 11〇75 丨 13116). 08) Low pressure chemical vapor deposition (LPCVD) deposition as the main reactant, and it is preferably deposited to a thickness between about 1,000 angstroms and 1,500 angstroms. After that, please refer to Fig. 3D, which shows the important steps for forming the lower electrode. Using the groove spacer 3 3 4 as a mask, the first conductive is anisotropically etched

417291 V. Description of the invention (9) The layer 330 to the shielding layer 326 'make the first conductive layer 330 below the groove 332 completely removed' to form a region 3 for separating the capacitors 3 32, e At the same time, leaving a part of the first The conductive layer 334 forms a crown-shaped lower electrode 330 ′. This etching process can be performed by a reactive ion etching method using gas (Cl2), hydrochloric acid (HC1) or silicon chloride (SiCl2) as an etching reaction gas. Since the present invention is combined with the shielding layer 3 2 6 'groove 3 3 2 and the groove spacer 334', an unnecessary first conductive layer can be removed in one etching step to form a crown-shaped lower electrode 330 'and maintain the substrate. The flat surface is not damaged. Therefore, the number of process steps and process costs can be reduced. Afterwards', please refer to FIG. 3E. The groove spacers 334 are removed in a selective etching process. The selective etching process needs to etch the groove spacers 334 much more than the shielding layer to protect the first insulating layer 324. For example, a wet etching process with 0.5-1% hydrofluoric acid as the main etching reactant is used to selectively remove the spacers. Because the hydrofluoric acid etching liquid has a very high etching selectivity (&gt; 300) for silicon nitride (shielding layer) and NSG (groove spacer), it can be used to selectively remove the groove space of NSG Article 3 34. Since conventional techniques mostly use anisotropic etching to remove the recessed spacer 334 ', this will transfer the sharp structure of the recessed spacer 334 to the lower electrode', and this sharp structure will cause the tip to discharge and affect the properties of the element. Therefore, the present invention avoids the problem of sharp tops caused by removing spacers by the conventional anisotropic etching method, and instead uses a selective wet etching process to remove the groove spacers so that the upward protrusion of the lower electrode remains. Complete top surface. Next, a dielectric layer 338 is formed to conformably cover the lower electrode 330 'and the first insulating layer 330. A first layer is then formed on the dielectric layer 338

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DESCRIPTION OF THE INVENTION (10) The three conductive layers 340 serve as upper electrodes. So far, the lower electrodes 33q, 3 38 and the upper electrode 340 can be combined into the crown capacitor of the present invention. Said 338 can be oxidized crushed / nitrided sand / oxidized layer (〇N〇: electric layer = material with electric coefficient). Among them, silicon oxide / silicon nitride / silicon oxide is preferred, and chemical vapor phase can be adopted. The deposition method is deposited to a thickness between about 50 angstroms and 70 angstroms. The third conductive layer 340 may be a polycrystalline silicon layer, which may be deposited to The thickness is between about 2000 angstroms and 300 angstroms. To make the polycrystalline silicon layer conductive, it can use diffusion, ion implantation of arsenic (As) or phosphorus ions (p), or synchronization Doping method. The above-mentioned dynamic random access memory cells with a crown capacitor should provide sufficient capacitance to be used in the process of highly integrated components. Based on the above process, the surface area of the electrodes can also be easily increased to provide more Large capacitance. As shown in FIG. 4, a plurality of hemi-spherical silicon grains (hemi-spherical silicon grains) can be formed on the exposed surface of the lower electrode 330 'by a conventional procedure before forming the dielectric layer 338. , HSG), or pleated compound crystals formed by low pressure vapor deposition (LPCVD) The (rugged polysilicon) structure 339 can effectively increase the surface area of the lower electrode 330 '. After that, the dielectric layer 338 and the upper electrode 340 are sequentially formed to complete the crown capacitance of the dynamic random access memory cell. The manufacturing method of the crown capacitor of the dynamic random access memory cell has the following characteristics: (1) it is not limited to the critical size required for the lithography process; (2) the use of grooves and spacers can be etched in one step

Page 14 417C31__ 5. Description of the invention (11) The step of forming a crown-shaped lower electrode can reduce the process steps and the cost of the process; (3) the depth of the groove can be used to control the thickness of the lower electrode; Layer to protect the flat insulation layer, so it can meet the high memory requirements and effective space utilization of the next generation. Therefore, the crown capacitor structure of the present invention can be applied to a dynamic random access memory, which can greatly increase the equivalent capacitance under a limited material. At the same time, those skilled in the art should understand that the material materials usable in the present invention are not limited to those cited in the examples, they can be replaced by various appropriate characteristics of materials and forming methods, and the structural space of the present invention is not limited to implementation. The size of the example. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

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Claims (1)

417291 Six 'Scope of Patent Application' ~ 1. A method for manufacturing a crown capacitor of a dynamic random access memory cell 'is suitable for manufacturing a capacitor on a semiconductor substrate with a switching element, and the above-mentioned manufacturing method includes the following steps: An insulating layer and a shielding layer are formed on the substrate; a contact opening that can communicate with the switching element is formed in the insulating layer and the shielding layer; a first conductive layer is formed on the shielding layer and in the contact opening, and The switching element is electrically connected; a groove is formed in the first conductive layer to define a region for separating each memory cell unit; a spacer is formed on a side wall of the groove; and the spacer is used as A mask, anisotropically etching the first conductive layer to the shielding layer to form the capacitor lower electrode; removing the spacer; forming a dielectric layer on the lower electrode and the shielding layer; on the dielectric An electrode above the capacitor is formed on the electrical layer. 2. The manufacturing method according to item 1 of the scope of patent application, wherein the thickness of the shielding layer is between 300 angstroms and 600 angstroms. 3. The manufacturing method according to item 1 of the scope of the patent application, wherein the first conductive layer is a polycrystalline silicon layer, and the degree of angulation is between 1500 and 3000 angstroms. 4. The manufacturing method as described in item 丨 of the patent application scope, wherein the spacers are removed by a selective money engraving process with a pair of the spacers having a far greater etching rate than the masking layer. No. 16 buttercup 417291 --------------------- --- 6. Application for patent scope 5. The manufacturing method described in item 1 of the scope of patent application, where The upper electrode is composed of polycrystalline silicon and has a thickness between 500 angstroms and 100 angstroms. 6. —A method for manufacturing a crown capacitor of a dynamic random access memory unit, which is suitable for manufacturing a capacitor on a semiconductor substrate having a switching element, and the above manufacturing method includes the following steps: forming an insulating layer and a shielding layer on the substrate; Forming a contact opening in the insulating layer that can communicate with the switching element '' forming a first conductive layer on the insulating layer and the contact opening to form an electrical connection with the switching element; in the first conductive layer A groove is formed to define a region for separating each memory cell unit, wherein the depth of the groove is smaller than the thickness of the first conductive layer; an insulating spacer is formed on a side wall of the groove; The spacer is a mask, and the first conductive layer to the shielding layer are anisotropically etched to form the lower electrode of the capacitor; the spacer is removed by a wet etching process; the lower electrode and the insulating layer are formed A dielectric layer; forming the above capacitor electrode on the dielectric layer. 7. The manufacturing method according to item 6 of the scope of patent application, wherein the above-mentioned etching process for forming the lower electrode completely removes the first conductive layer located below the groove, exposing a part of the shielding layer and leaving it in the above. The first conductive layer under the spacer and the first conductive layer partially between the grooves form the lower electrode of the capacitor. Page 17 The masking layer is the manufacturing method described in Item 6 of the above, wherein the thickness of the above 9. Ruhuamiao layer is between 3 ⑽ and 6 ⑽. The manufacturing method described in item 6 of the insulating spacer ^ g range, wherein the above-mentioned 10. The thickness is in the range of 6000 angstroms to 800 angstroms as described in the patent application. The manufacturing method described in item 6 of removing the insulating spacers, wherein the wet etching procedure described above uses the dilute hydrofluoric acid as the main etching reactant dielectric layer as the free oxygen 1 &amp; ^ f6 A manufacturing method in which the two gaseous stone / oxidized stone layers composed of the above-mentioned stone and nitride stone are formed by a substance in an oxide &lt; rank. Page 18