1242292 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電容，特別是有關於一種具有多 層電極之電容及其製造方法。 【先前技術】 著半導體工業的快速發展，縮減元件的特徵尺寸來 增加積集度及減少晶片尺寸大小已成為渴望的需求。然而 當記憶體產品中的電容尺寸微縮後，儲存電量的空間也相 對的細小’導致儲存電能大減。因此，如何在不增加元件 尺寸的情況下製造出具有較高電容值（capacitance value)的 電谷便是目前電容製造技術發展的方向。 目前半導體產品上的電容可依製程分為堆疊式電容 (stack capacitor)與溝渠式電容(trench capacitor)。堆疊式電 容係為，當在基材上方完成電晶體與其他電子元件及内部 連線後，才在覆蓋在電晶體上方之介電層上製造出電容結 構。此種電谷生產技術較為簡單，成本低，但產出的電容 晶粒數較少。而溝渠式電容則以類似淺溝渠隔離製程的技 術在晶圓基材中蝕刻出溝渠，隨後在溝渠中填入介電層與 導電層來製造出電容結構。 不論溝渠式電容或堆疊式電容都期望能達到在不增加 電容體積的條件下提高電容值的目的。因此，在美國專利 第6261895號中曾揭露具有多層電極的電容結構以提高電 容值。請參考第1圖之剖面圖，傳統多層電極之電容結構 係在基材102(或電晶體上方的絕緣層）中蝕刻出溝渠。並依 1242292 完成第lAffl之剖面結構。帛⑺圖則為帛以目之電容結 構的上視圖。 ^在溝渠^部表面上依序沈積第—金屬層H)4、第-多晶石夕 曰06 一第’’電層108、第二多晶矽層110、第二金屬層 ⑴、第三多晶矽層114、第二介電層116以及第四多晶矽 層H8。最後將第三金屬層12〇沈積在第四多晶石夕層118 方直至填滿溝槽。對此基材表面執行平坦化步驟（如化學 機械研磨步驟，CMP)直至暴露出第_金屬層1()4為止，即 完成第1A圖之結構後，以微影蝕刻技術在第一金屬層 104、第一金屬層112與第三金屬層12〇暴露出來的頂面上 拉出接引線（1叫128、126、124與122。當藉著接引線128、 124與122將第一金屬層104與第三金屬層12〇連接至一電 極，並藉著接，引線126來將第二金屬層112連接至另一電 極後，第一金屬層104與第二金屬層112可形成一電容， 而第二金屬層112又可與第三金屬層12〇形成另一個電 容。因此，此種結構可增加電容面積而得到提高電容值的 效果。 但第1A圖之習知電容的缺點在於接引線製造困難。由 於為了不增加電容在基材上的佔據面積，故溝槽内的每异 材料厚度皆極薄’可能只有數個奈米（nm)，甚至僅達數十 個A的厚度。此種厚度下’以現有之微影技術無法精準地 在各金屬層之暴露面上製造出接引線122、124、u6 & 12 8。當接引線位置稍有位移，便可能發生漏電、短路或無 法與金屬層做電性連接的問題而失去電容的作用。 習知電谷亦揭露另一種連接各層金屬層的方法。过央^ 1242292 考第ID圖，其利用導電層13〇來將第一金屬層ι〇4、第二 金屬層112與第三金屬層電性連通至導線132 Ji。然而此 連接方去雖然克服了上述之微影技術的問題，但因三層 金屬層全部連通成為同一組電極上，此種連接方法無法達 到利用兩不同電極來組成電容的作用。 〜因此，需要一種電容結構及其製造方法，能在不增加 電合體積的情況下，達成利用形成多層電容板來增加電量 儲存空間的目㈤。並且此種多層電容板結構之電容可應用 在堆叠式電容或溝渠式電容之製造上。 【發明内容】 因此本發明的目的在於提供一種具有多電極之電容， 能在不增加電容體積的條件下，提高電容值。 本發明的另一目的在於提供一種具有高電容值之多電 極電容，其可應用於溝渠式電容或堆疊式電容。 根據本發明之上述目的，提出一種多電極電容及其製 造方法。係在基材中或基材上方之絕緣層形成一溝渠。隨 後在溝渠内壁上依序形成第一導電層、介電層、第二導電 層、介電層，並可重複上述步驟數次直至填滿溝渠。移除 部分第一導電層、介電層與第二導電層至一深度，並執行 濕蝕刻使第一導電層與基材頂面距離一第一深度，亦使第 二導電層與基材頂面距離一第二深度，其中可使第一深度 大於第二深度，或使第二深度大於第一深度。形成第一絕 緣層，並且當第一深度大於第二深度時，第一絕緣層會覆 蓋第一導電層並暴露出第二導電層。當第二深度大於第一 U42292 深度時，筮Λ 、、、巴緣層會霜荖楚-道 層。形成第n/ 導電層並暴露出第-導電 或與暴露之第層與暴露之第二導電層電性連通， 層與部分第-絕緣層層=:移除部分第-連通導電 :導電層。執行表面處理:：中:;第:::層與部分第 :電f電性連通時，表面處理使第一導電與第-絕緣表面時，會使第 暴路面成為 表面；或當第-連通導電層成為第二導體 面處理使第一導電芦 、：¥電層電性連通時，表 使第二導電声上 成為第一導體表面時，會 二連通導電居表面成為第二絕緣表面。隨後形成第 電層會導電層電性連通。此時第二連通導 隔：第-導電層或與具有第二絕緣表面之第二導電層電性 /表面處理可為氧化錢化反應1表面處理為氣 η反應時，表面轉變為導體表面之第一或第二導電層材質 :為鈦或氮化鈦。當表面處理為氧化反應時，表面轉變為 導體表面之第-或第二導電層㈣可為釕㈣、氧化釘 (Ru02)、銦錫氧化物（indium如〇仙，ιτ〇)或銦辞氧化物 (indiUm ZinC 〇Xide，ΙΖ0)。此外在氧化或氮化反應中使表面 轉變為絕緣表面之第一或第二導電層的材質可為多晶矽或 鋁。介電層之材質可為介電係數大於或等於3·9之介電材 料，例如氮化矽（SiN)、氧化矽、氧化鋁（Al2〇3)、氧化鍅 (Zr〇2)、氧化鈦（Tl〇2)、氧化铪（Hf02)、氧化勰（sr〇)、鈦酸 1242292 鋇（pzt)、氧化鋇（Ba0)與鈦酸銷鋇（BST)。本發明中執行濕 蝕刻之步驟係為使第-導電層與第二導電層因钱刻選擇二 ，不同產生距離基材頂面之高低差，使其中一組導電層與 第-連通導電層相連。而表面處理之步驟係為使不盘= 連通導電層相連之另-組導電層形成導體表面，而盛第二 連通導電層電性相連，而與第一連通導電層相連導電層電 性隔離。由以上之方法而產生兩組互相電性隔離之電極。 然上述之㈣刻步驟與表面處理步驟兩者並無特定之順 序，亦可先執行表面處理步驟使第一連通導電層鱼一植導 電層電性相連’之後利用濕餘刻步驟使另一組導電層因姓 刻選擇比之不同’使其頂部與基材頂面距離較近，而與第 二連通導電層電性相連。本發明之兩組導電層分別與第一 連通導電層及第二連通導電層電性相連之方法，亦可同為 利用濕蝕刻步驟，此將於後詳細描述。 本發明之優點在於不增加電容所佔空間的情況下，在 電容中形成多層電極結構以提高電容值。且本發明之多層 電極電容結構適合用來做為溝渠式電容或堆叠式電容。 【實施方式】 本發明揭露-種多層電極之電容及其製造方法。請參 考第2A ®之流程圖’純行㈣)步驟以在半導體基材 或電子7L件之電晶體上方的介電層中製造出一溝渠。執行 反覆沈積步驟202以在溝渠内部表面上依序反覆沈積第一 導電層與第二導電層，並在第一導電層與第二導電層之間 均炎置有介電層，並沈積至溝渠填滿。執行平坦化與姓刻 1242292 步驟203’使得溝渠内之各層導電層與介電層的頂面暴露出 來並距離溝渠頂面一深度。 隨後執行濕蝕刻步驟204來蝕刻第一導電層、第二導 電層與介電層以產生高度差。濕蝕刻步驟2〇4需對第一導 電層、第二導電層與介電層具有不同的蝕刻速率，以使第 一導電層距離溝渠頂面一第一深度，並使第二導電層距離 溝渠頂面一第二深度，其中第一深度可大於或小於第二深 度。而各介電層距離溝渠頂面之深度則大於第一深度與第 二深度。例如，當第一導電層、第二導電層與介電層分別 為氮化鈦、多晶矽與氮化矽時，可使用5 :丨的緩衝氫氟酸 之緩衝液（buffered hydrofluoric acid, BHF)在 20°C 下進行濕 蝕刻，其對氮化鈦、多晶矽與氮化矽的蝕刻速率分別為25 A/min、9 A/min與82 A/min。當第一導電層與第二導電層 分別為鈦與多晶矽時，可使用溶液8〇0/。之磷酸、5%硝酸、 5%醋酸、與1〇%水在5(rc下進行濕蝕刻，其對鈦與多晶矽 的餘刻速率分別為〇 A/min與1 〇 A/min，蝕刻後第一導電 層具有之第一深度小於第二導電層具有之第二深度；而使 用溶液9%硝酸鈽氨（NH4)2Ce(N〇3)6、6%過氣酸（HC1〇心、 與水在20°C下進行濕蝕刻，其對鈦與多晶矽的蝕刻速率分 別為20 A/min與〇 A/min，#刻後第一導電層具有之第一 深度大於第二導電層具有之第二深度。 將溝渠内之各導電層與介電層以濕蝕刻步驟製造出高 低差後’執行步驟2 0 6 ’係在基材、溝槽側壁、第一導電層、 第二導電層與介電層上方沈積第一絕緣層。並蝕刻第一絕 緣層’其中當上述之第一深度大於第二深度時，第一絕緣 1242292 層會覆蓋住第一導+M 宜 度小於苐二深度時兒二，露出第二導電層；當第1 暴露出第—導電層。、:€緣層會覆蓋住第二導電層，而 執行步驟208將第一遠 導電層與介電層之承露面Γ二層沈積在溝渠内之各層 而暴露出第二導電層時第導 二導電層電性連n 第一連通導電層會與第 通’右第一絕緣層霜筌/士梦一、兹 暴露出第—導m覆盖住第二導電層，並 電性連ϋπ /曰，，則第一連通導電層會與第一導電； 電【連通而形成本發明電容之 導電層 驟21〇,以溝渠中心為基準，將溝渠内之影餘刻步 電層移除以暴露出部分的第一導電芦第一連通導 層。 $ ^層、第二導電層與介電 可為32—表面處理㈣212,此表面處理步驟m 反應’並使第一連通導電廣與各導電層之 產生導體表面或絕緣表面。其中，當步驟所 I成之第-連通導電層電性連 時，則笛一道吸乐―導電層以形成一電極 之材料而裳s的材質需為表面處理後會產生導體表面 的導電層則需為表面處理後會產生絕緣表面 導雷厗右A 208所形成之第一連通導電層電性連通第 :導，形成一電極時，則第—導電層的材質需為表面 =理後會產生絕緣表面之材料，而第二導電層則需為表面 處理後會產生導體表面的材料。 執行沈積步驟2H’係將第二連通導電層沈積在基材上 方並覆蓋在溝渠内具有導體表面或絕緣表面之導電㈣ 介電層上。第二連通導雷展 逆通导电層了電性連通溝渠内的具有導體 1242292 表面的第一或第二導電層以行成本發明電容之另一電極。 便可得到本發明之多電極電容結構.。 本發明之製造方法亦可根據第2A圖所示之本發明方 法來加以變化。請參考第2B圖之流程圖，首先同第2八圖 之v驟進行至步驟203後，先執行表面處理216使各導電 層與各導電層之暴露面上產生導體表面或絕緣表面。若第 一導電層的材質為氧化或氮化後會產生導體表面之材料 時，第一導電層則需為表面處理後會產生絕緣表面的材 料。若第—導電層的材質需為氧化或氮化後會產生絕緣表 面之材料’第二導電層則需為表面處理後會產生導體 的材料。 隨後執行步驟218沈積第一連通導電層覆蓋在具有導 體表面與絕緣表面的各導電層與介電層上。第一連通導電 層會與具有導體表面的第一導電層電性連通，或與具有導 體表面的第二導電層電性連通以形成本發明電容之一電 極。執行微影蝕刻步驟22〇,以溝渠中心為基準，將溝渠内 之半邊的第—連通導電層移除，並接著選擇性地移除:電 層上之絕緣表面或導體表面，以暴露出部分的第— 層、第一導電層與介電層。 第一深度，使第二導 隨後執行濕蝕刻步驟222來蝕刻暴露出來的 層、第二導電層與介電層以產生高度差。㈣刻步驟222 會蝕刻各導電層與介電層，以使第一導電層距離溝渠頂面 一第二深度 並 使w電層距離溝渠頂面之深度大於第一深度與第二深度。 當步驟218所形成之第一連通導電層與第一導電層；：連 12 1242292 通時’則濕蝕刻步驟222需使第一深度 第-連通導電層與第二導電層電性連4 222需使第二深度大於第-深度。 則濕㈣步驟 執行步驟224,係在基材、溝槽側壁、 喷 二導電層與介電層上方沈積第—絕緣層。^電層^ 層以暴露出第一導電層或第二導電層。4:第一絕緣 第二深度時，第—絕緣層會覆蓋住第 :暴露出第二導電層。當第一深度小於第二深度：電二 絶緣層會覆蓋住第二導電層，而暴露出第—導電層 =料㈣226,係將第三料導電觀餘基材上 Μ:則第絕T層覆蓋住第一導電層，而暴露出第二導電 層時則第二連通導電層會與第二導電層電性； 緣層覆盍住第二導電層，並暴露出第一導電層日寺，則第二 連通導電層會與第—導電層電性連通而形成本發明電容之 另電極’遂完成本發明之電容結構。 …本發明方法更可根據第2A與第⑼圖所示之方法再加 乂變化。明參考第2C圖，其顯示本發明之另一變化方法的 ，程圖、。首圖之步驟進行至步驟㈣後，選擇執 仃另-祕刻步驟228。濕㈣步驟⑽會使第一導電層距 離溝渠頂面-第三深度，並使第二導電層距離溝渠頂面一 第四深度，其中第三深度可大於或小於第四深度。而各介 電層距離溝渠頂面之隸則大於第三深度與第四深度。當 步驟208所形成之第—連通導電層與第—導電層電性連通 時’則祕刻步驟228需使第四深度小於第三深度。若步 驟208戶斤形成之第一連通導電層與第二導電層電性連通 13 1242292 時，則濕—步驟228需使第四深度大於第三深度。 ，執仃步驟230，係在基材、.溝槽側壁、第一導電層、第 二導電層、介電層與第-連通導電層之暴露面上方^積 :絕緣層。並蝕刻第二絕緣層以暴露出第一導電層或第二 ^電a其中虽上述之第二深度大於第四深度時，第二0 緣層會覆蓋住第一導電層，而暴露出第二導電層。當^ 深度小於第四深度時，第二絕緣層會覆蓋住第二導;層， 而暴露出第一導電層。 曰 隨後執行沈積步驟232,係將第二連通導電層沈積在夷 材上方。當第二絕緣層覆蓋住第一導電層，而暴露出第二 4導電層時，則第二連通導電層會與第二導電層電性連通； 若第二絕緣層覆蓋住第二導電層，並暴露出第一導電層 時，則第二連通導電層會與第一導電層電性連通而形成: 發明電容之另一電極，並完成本發明之電容結構。 上述第2A至第2C流程圖之步驟中，當第一種導電層 之材料在表面處理後仍能保持其導電能力時，則第二種^ 電材料需為表面處理後成為絕緣的導電材料。若第一種導 電材料在表面處理後成為絕緣的導電材料日寺，則第二種導 電材料需為表面處理後仍能保持導電能力的導電材料。其 中氮化後仍可導電的材料可為鈦(Ti)或氮化鈦（TiN);氧^匕 後可導電之材料可為釕、氧化釕、銦錫氧化物或銦辞氧化 物。而氧化或氮化後不導電的材料可為多晶㊉（ρ_ s出叫 或紹（A1)。介電層之材料則可以是各種介電係數大於或等於 3.9之”一電材料’如氮化石夕、氧化石夕、氧化銘、氧化錯、氧 化鈦、氧化铪、氧化錄、鈦酸鋇、氧化鎖與鈦酸銷鋇。並 14 1242292 且溝渠内之各導電層與介電層的層數與厚度可依習知技藝 者的需求而加以變化。· 為使本發明之技術敘述能更清楚明白，係以下列應用 本發明技術之較佳施例來說明本發明之多電極電容的製造 技術、結構與應用領域。 、 JL 一較佳實施例 第一較佳實施例係利用本發明之製造方法來在半導體 基材上製造出溝渠式多電極電容。請參考第3A圖，係在基 材300上產生墊氧化層302與硬罩幕304以保護基材或作 為蝕刻或平坦化步驟的終止層。再利用微影蝕刻技術在半 導體基材300中蝕刻出溝渠306。完成溝渠3〇6後，在基材 3〇〇與溝渠306之内部表面上沈積一層摻雜物氧化層（d〇ped 〇xide)308，此摻雜物氧化層3〇8係用來在基材中執行離子 驅入（drive in)之用。同樣以沈積與乾蝕刻步驟來在溝渠3〇6 中填入光阻3 10，便可得到第3A圖所示之結構。 當完成第3A圖之結構，利用濕㈣步驟來移除未被光 阻310覆蓋住的摻雜物氧化層3〇8後，以習知技藝者所熟 悉之程序來移除溝II 306中的光阻310。隨後在基材表面： 溝渠306之暴露面及保留的掺雜物氧化層规上方沈積氧 曰311氧化層311之作用在於執行離子驅入步驟時，避 免換雜物向未被摻雜氧化層谓覆蓋的地方擴散。隨後執 仃離子驅人步驟後便可在基材細中產生摻雜區312，而得 =第3B圖所示之結構。摻雜區312係用來與電容 的導電層做電性連接。 15 1242292 牛完成離子驅入步驟來形成摻雜區312後，執行濕蝕刻 步驟將第3B圖中的氧化層311與摻雜氧化層3〇8完全移 除。並在溝渠306之内壁上依序沈積第一導電層Η#、第一 =電層316、第二導電層318、第二介電層32〇、第三導電 :322、第二介電層324、第四導電層326、第四介電層Mg、 =五導電層33G、第五介電層332、第六導電層说、第六 介電層336、第七導電層338與第七介電層340,並沈積第 八導電層342直至填滿溝渠则。執行平坦化步驟或钱刻步 驟使得溝渠内之各層導電層與介電層的頂面暴露出來，並 :、硬罩幕304形成共平面之平坦表面，即可完成第3c圖所 不之結構。 其中第一導電層314、第三導電層322、第五導電層33〇 與第七導電層338可使用氮化鈦（TiN);第二導電層318、 第四導電層326、第六導電層334與第八導電層342則可使 用多晶矽（poly silicon);第一介電層316至第七介電層34〇 之材料則可以是各種高介電常數之材質，例如氮化石夕⑻N)。 ^完成第3C圖之多層導電層的結構後，執行乾蝕刻步驟 來移除溝渠内部分導電層與介電層至—深度。隨後執行濕 蝕刻步驟，例如使用緩衝氫氟酸之緩衝液（buffered hydt〇fiuodc acid，BHF)來蝕刻溝渠内的各導電層與介電 層，使溝渠内各導電層與介電層產生高度差，而得到如第 30圖所不之結構。第3E圖為第3D圖之方格344的放大 圖，其顯示由多晶矽所構成之第二導電層318、第四導電層 326、第六導電層334與第八導電層342的蝕刻速率最慢， 因此兩度最高。由氮化鈦所構成之第一導電層314、第三導 16 1242292 電曰322帛五導電層33〇與第七導電層338之银刻速率次 之而各層介電層之餘刻速度最快，因此高度最低。 凊參考帛3F圖，係在溝渠内壁與各導電層及介電層之 暴露面上沈積第-絕緣層346，並填滿溝渠内各導電層與介 電層之間的間隙。此時，第3F圖之〜方袼344處的放大結構 ^如第3G圖所π。參考第3H圖，係執行乾姓刻步驟移除 部分第-絕緣層346以暴露出第二導電層318、第四導電層 似、第六導電層334與第八導電層342。此時第圯圖: 方=344的放大結構則如第31圖所示。第3i圖顯示出在移 除邛分的第一絕緣層後，第二導電層318、第四導電層Μ。 第’、導電層334與第八導電層342之頂面會暴露出來。而 第—導電層314、第三導電層322、第五導電層33()、第七 ，電層338以及溝渠306之侧壁仍被第一絕緣層346所覆 蓋。 當完成第31圖之結構後’在基材上沈積第_連通導電 層348直到填滿溝渠3〇6。隨後執行平坦化步驟，例如化學 機械研磨來移除基材表面上的第—連通導電層直至暴露: 硬罩幕304而成為第3J圖所示之結構。請參考第3J圖， ^時第-連通導電層348會電性連通第二導電層318、第四 2層326、第六導電層334與第八導電層如，而成為電 谷中的第一組電極。 疋成第3J圖中之結構後，依序將墊氧化層35〇、氮化 層352與罩幕354沈積在基材3〇〇與第一絕緣層348之上 方。並以習知的微影蝕刻技術來移除以溝渠中間為基準之 半邊的第一連通導電層348,而暴露出部分的第二導電層 17 1242292 3U、第四導電層326、第六導電層334與第八導電層 即可得到如第3K圖所示之結構。 隨後可利用乾#刻或濕蝕刻步騾來移除第图 罩幕層354與部分氮化層352。並執行濕韻刻步驟 濕蝕刻來移除未被第一連通導電層348所覆蓋之第—夂 層346,使得第一導電層314、第三導電層322、第二= 層330與第七導電層338之頂面暴露出來。便可得到如= 3L圖所示之結構。第3M圖為第几圖中方格奶的 圖’用來顯示第二導電層318、第四導電層似、第 層334與第人導電層342之高度最高。由氮化鈦所構成之 第-導電層314、第三導電層322、第五導電層33〇與第七 導電層338之高度次之。各層介電層之高度最低。1242292 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a capacitor, and more particularly to a capacitor having a plurality of layers of electrodes and a method for manufacturing the same. [Previous technology] With the rapid development of the semiconductor industry, reducing the feature size of components to increase the degree of integration and reducing the size of wafers has become a desire. However, when the size of the capacitors in the memory products shrinks, the space for storing electricity is also relatively small, which leads to a large reduction in stored power. Therefore, how to make an electric valley with a higher capacitance value without increasing the component size is the current development direction of capacitor manufacturing technology. Current capacitors on semiconductor products can be divided into stack capacitors and trench capacitors according to the manufacturing process. A stacked capacitor is a capacitor structure that is formed on the dielectric layer overlying the transistor after the transistor and other electronic components and internal interconnections are completed over the substrate. This kind of power valley production technology is relatively simple and low cost, but the number of capacitor grains produced is small. For trench capacitors, a trench is etched into the wafer substrate using a technique similar to the shallow trench isolation process, and then a dielectric layer and a conductive layer are filled in the trench to create a capacitor structure. Both trench capacitors and stacked capacitors are expected to achieve the purpose of increasing the capacitance value without increasing the volume of the capacitor. Therefore, U.S. Patent No. 6,261,895 has disclosed a capacitor structure having a multilayer electrode to increase the capacitance value. Please refer to the cross-sectional view of FIG. 1. The capacitance structure of the conventional multilayer electrode is etched with a trench in the substrate 102 (or the insulating layer above the transistor). And according to 1242292, the section structure of lAffl is completed. The figure shows the top view of the capacitor structure. ^ Sequentially deposited the first-metal layer on the surface of the trench ^ 4,-the first-polycrystalline stone 06-the first `` electrical layer 108, the second polycrystalline silicon layer 110, the second metal layer ⑴, the third The polycrystalline silicon layer 114, the second dielectric layer 116, and the fourth polycrystalline silicon layer H8. Finally, a third metal layer 120 is deposited on the fourth polycrystalline silicon layer 118 until the trench is filled. Perform a planarization step (such as a chemical mechanical polishing step, CMP) on the substrate surface until the _ metal layer 1 () 4 is exposed, that is, after the structure of FIG. 1A is completed, the first metal layer is lithographically etched. 104. The lead wires (1 called 128, 126, 124, and 122) are pulled out on the exposed top surfaces of the first metal layer 112 and the third metal layer 120. When the first metal layer is connected by the lead wires 128, 124, and 122, 104 and the third metal layer 120 are connected to an electrode, and the second metal layer 112 is connected to the other electrode by a lead 126, and the first metal layer 104 and the second metal layer 112 can form a capacitor. The second metal layer 112 can form another capacitor with the third metal layer 120. Therefore, this structure can increase the capacitance area and improve the capacitance value. However, the conventional capacitor of FIG. 1A has the disadvantage of connecting leads. Manufacturing difficulties. In order not to increase the area occupied by the capacitor on the substrate, the thickness of each different material in the trench is extremely thin. It may be only a few nanometers (nm), or even only a few tens of A. This This thickness cannot be accurately measured with existing lithography technology. The lead wires 122, 124, u6 & 12 are manufactured on the exposed surface of the metal layer. When the position of the lead wire is slightly shifted, leakage, short circuit or failure to make an electrical connection with the metal layer may occur and lose the function of capacitance. . Known Electric Valley also revealed another method to connect the various metal layers. Pass the center ^ 1242292 As shown in Figure ID, it uses the conductive layer 13 to connect the first metal layer ι04, the second metal layer 112, and the third metal. The layer is electrically connected to the conductor 132 Ji. However, although this connection method overcomes the problems of the lithography technology described above, because all three metal layers are connected to form the same group of electrodes, this connection method cannot achieve the use of two different electrodes. The role of the capacitor. ~ Therefore, there is a need for a capacitor structure and a method of manufacturing the capacitor structure that can increase the amount of electricity storage space by forming a multi-layer capacitor plate without increasing the electrical volume. And such a multi-layer capacitor plate structure The capacitor can be applied to the manufacture of stacked capacitors or trench capacitors. [Summary of the Invention] Therefore, the object of the present invention is to provide a capacitor with multiple electrodes. The capacitance value is increased without increasing the volume of the capacitor. Another object of the present invention is to provide a multi-electrode capacitor having a high capacitance value, which can be applied to a trench capacitor or a stacked capacitor. According to the above object of the present invention, A multi-electrode capacitor and a manufacturing method thereof are proposed. A trench is formed in an insulating layer in or above a substrate. Subsequently, a first conductive layer, a dielectric layer, a second conductive layer, and a dielectric are sequentially formed on an inner wall of the trench. Layer, and the above steps can be repeated several times until the trench is filled. Remove part of the first conductive layer, the dielectric layer and the second conductive layer to a depth, and perform wet etching to make the first conductive layer and the top surface of the substrate a distance away from each other. The first depth also distances the second conductive layer from the top surface of the substrate by a second depth, wherein the first depth may be greater than the second depth, or the second depth may be greater than the first depth. A first insulating layer is formed, and when the first depth is greater than the second depth, the first insulating layer covers the first conductive layer and exposes the second conductive layer. When the second depth is greater than the first U42292 depth, the 筮 Λ,, and BA marginal layers will frost the Chu-dao layer. Form the n / conductive layer and expose the -conducting layer or be in electrical communication with the exposed first layer and the exposed second conductive layer, layer and part of the -conducting layer layer =: remove part of the -conducting conductive: conductive layer. Performing a surface treatment :: middle :; first :: layer and part first: When the electrical f is electrically connected, the surface treatment makes the first conductive and insulating surface to make the first pavement a surface; or when the first-connected When the conductive layer becomes the second conductive surface and the first conductive layer is electrically connected, when the second conductive surface becomes the first conductive surface, the second conductive surface becomes the second insulating surface. The subsequent formation of the second electrical layer electrically connects the conductive layers. At this time, the second communication barrier: the first conductive layer or a second conductive layer with a second insulating surface, the electrical / surface treatment can be an oxidation reaction, and the surface becomes a conductor surface when the surface treatment is a gas η reaction. Material of the first or second conductive layer: titanium or titanium nitride. When the surface treatment is an oxidation reaction, the surface is changed to the first or second conductive layer of the conductor surface. The ㈣ may be ruthenium, ruthenium oxide (Ru02), indium tin oxide (indium such as 〇 仙, ιτ〇), or indium oxide oxidation. (IndiUm ZinCoxide, IZ0). In addition, the material of the first or second conductive layer that changes the surface to the insulating surface during the oxidation or nitridation reaction may be polycrystalline silicon or aluminum. The material of the dielectric layer may be a dielectric material having a dielectric constant greater than or equal to 3 · 9, such as silicon nitride (SiN), silicon oxide, aluminum oxide (Al203), hafnium oxide (ZrO2), titanium oxide (T102), hafnium oxide (Hf02), hafnium oxide (sr0), barium titanate (1242292) (pzt), barium oxide (Ba0), and barium titanate (BST). The step of performing wet etching in the present invention is to make the first conductive layer and the second conductive layer choose two because of the money engraving. The difference between the first conductive layer and the top surface of the substrate is different, and one of the conductive layers is connected to the first conductive layer. . The surface treatment step is to make the non-disk = another conductive layer connected to the conductive layer to form a conductor surface, and the second conductive conductive layer is electrically connected, and the conductive layer connected to the first conductive conductive layer is electrically isolated. . Two sets of electrodes which are electrically isolated from each other are generated by the above method. However, there is no specific order between the above-mentioned engraving step and surface treatment step. The surface treatment step may be performed first to electrically connect the first conductive conductive layer and the conductive layer, and then use the wet etching step to make another The conductive layer of the group is electrically connected to the second connected conductive layer due to the difference in the selection ratio between the top and bottom of the conductive layer. The method of electrically connecting the two sets of conductive layers of the present invention to the first and second connected conductive layers, respectively, can also be a wet etching step, which will be described in detail later. The advantage of the present invention is that a multilayer electrode structure is formed in the capacitor without increasing the space occupied by the capacitor to increase the capacitance value. And the multilayer electrode capacitor structure of the present invention is suitable for use as a trench capacitor or a stacked capacitor. [Embodiment] The present invention discloses a capacitor of a multilayer electrode and a manufacturing method thereof. Please refer to the flow chart of 2A ® 'Pure Line') to create a trench in the dielectric layer above the semiconductor substrate or the transistor of the electronic 7L part. The repeated deposition step 202 is performed to sequentially deposit the first conductive layer and the second conductive layer on the inner surface of the trench, and a dielectric layer is disposed between the first conductive layer and the second conductive layer, and is deposited to the trench. Fill up. Performing planarization and engraving 1242292 Step 203 'exposes the top surfaces of the conductive layers and the dielectric layers in the trench to a depth from the top surface of the trench. A wet etching step 204 is then performed to etch the first conductive layer, the second conductive layer and the dielectric layer to produce a height difference. The wet etching step 204 requires different etching rates for the first conductive layer, the second conductive layer, and the dielectric layer, so that the first conductive layer is a first depth from the top surface of the trench, and the second conductive layer is away from the trench. The top surface has a second depth, wherein the first depth may be greater than or less than the second depth. The depth of each dielectric layer from the top surface of the trench is greater than the first depth and the second depth. For example, when the first conductive layer, the second conductive layer, and the dielectric layer are titanium nitride, polycrystalline silicon, and silicon nitride, respectively, a buffered hydrofluoric acid (BHF) buffer solution of 5: 丨 can be used. Wet etching at 20 ° C, the etching rates of titanium nitride, polycrystalline silicon and silicon nitride are 25 A / min, 9 A / min and 82 A / min, respectively. When the first conductive layer and the second conductive layer are titanium and polycrystalline silicon, respectively, a solution of 800/50 can be used. Phosphoric acid, 5% nitric acid, 5% acetic acid, and 10% water were wet-etched at 5 ° C, and the remaining rates of titanium and polycrystalline silicon were 0A / min and 10A / min, respectively. A conductive layer has a first depth that is less than a second depth of the second conductive layer; and a solution of 9% ammonium nitrate (NH4) 2Ce (N03) 6, 6% peroxyacid (HC10 core, and water) is used. Wet etching is performed at 20 ° C, and its etch rates for titanium and polycrystalline silicon are 20 A / min and 0 A / min, respectively. After the etch, the first conductive layer has a first depth greater than the second conductive layer has a second depth. Depth. After the difference between the conductive layer and the dielectric layer in the trench is produced by the wet etching step, perform the step 2 0 6 'on the substrate, the trench sidewall, the first conductive layer, the second conductive layer and the dielectric. A first insulating layer is deposited on top of the layer. The first insulating layer is etched. Where the first depth is greater than the second depth, the first insulating 1242292 layer will cover the first conductive layer. , The second conductive layer is exposed; when the first-conductive layer is exposed. The edge layer will cover the second conductive layer, and the step is performed Step 208: When the exposed surface of the first remote conductive layer and the dielectric layer are deposited in two layers in the trench and the second conductive layer is exposed, the second conductive layer is electrically connected to the first conductive layer and the first conductive layer. Through the first right insulating layer of frost / Shimeng I, it is exposed that the first conductive layer m covers the second conductive layer and is electrically connected to π / y, the first connected conductive layer will be conductive with the first; Electrically [connecting to form the conductive layer of the capacitor of the present invention is step 21. With the trench center as a reference, the shadow electrical layer in the trench is removed to expose a portion of the first conductive reed first conductive layer. $ The layer, the second conductive layer, and the dielectric may be 32-surface treatment 212, and this surface treatment step m reacts and makes the first communication conductive layer and each conductive layer generate a conductor surface or an insulating surface. Among them, when the step When the first-connected conductive layer is electrically connected, the flute will absorb music—the conductive layer to form an electrode material, and the material of the skirt must be surface treated. The conductive layer that produces the conductor surface needs to be surface treated. A first conductive conductive layer formed by an insulated surface conducting right A 208 will be generated The first conductive layer is conductive. When forming an electrode, the material of the first conductive layer must be a material that will produce an insulating surface after processing, and the second conductive layer should be a material that will produce a conductor surface after surface treatment. Deposition step 2H 'is to deposit a second connected conductive layer on the substrate and cover the conductive ㈣ dielectric layer having a conductor surface or an insulating surface in the trench. The second connected conductive layer conducts an electrical connection to the trench. The first or second conductive layer having the surface of the conductor 12422292 can be used as the other electrode of the capacitor of the invention. The multi-electrode capacitor structure of the invention can be obtained. The manufacturing method of the invention can also be based on the method shown in FIG. 2A. The method of the present invention is changed. Please refer to the flow chart of FIG. 2B. First, proceed to step 203 with step v of FIG. 28 and then perform surface treatment 216 to generate conductors on each conductive layer and the exposed surface of each conductive layer. Surface or insulating surface. If the material of the first conductive layer is a material that will produce a conductor surface after oxidation or nitridation, the first conductive layer must be a material that will produce an insulating surface after surface treatment. If the material of the first conductive layer needs to be a material that will produce an insulating surface after oxidation or nitridation, the second conductive layer needs to be a material that will produce a conductor after surface treatment. Step 218 is then performed to deposit a first connected conductive layer covering each conductive layer and dielectric layer having a conductor surface and an insulating surface. The first connected conductive layer is in electrical communication with the first conductive layer having a conductive surface, or is in electrical communication with the second conductive layer having a conductive surface to form an electrode of the capacitor of the present invention. Perform the lithography etching step 22, taking the center of the trench as a reference, remove the first-connecting conductive layer on the half of the trench, and then selectively remove: the insulating surface or the conductive surface on the electrical layer to expose a part The first layer, the first conductive layer and the dielectric layer. The first depth causes the second conductive layer to subsequently perform a wet etching step 222 to etch the exposed layer, the second conductive layer, and the dielectric layer to produce a height difference. The engraving step 222 will etch each conductive layer and dielectric layer so that the first conductive layer is a second depth from the top surface of the trench and the depth of the w-electric layer from the top surface of the trench is greater than the first depth and the second depth. When the first connected conductive layer and the first conductive layer formed in step 218 are connected to: 12 1242292, the wet etching step 222 needs to electrically connect the first depth-connected conductive layer to the second conductive layer 4 222 The second depth needs to be greater than the -th depth. Then, the wet-up step is performed in step 224, where a first insulating layer is deposited on the substrate, the sidewall of the trench, the sprayed second conductive layer and the dielectric layer. ^ Electrical layer ^ to expose the first conductive layer or the second conductive layer. 4: First insulation At the second depth, the first-insulating layer will cover the first: the second conductive layer is exposed. When the first depth is less than the second depth: the second insulating layer will cover the second conductive layer, and the first conductive layer = material 226 is exposed, the third material is conductive on the substrate. Covering the first conductive layer, and when the second conductive layer is exposed, the second connecting conductive layer is electrically conductive with the second conductive layer; the edge layer covers the second conductive layer and exposes the first conductive layer Risi, Then the second connected conductive layer will be in electrical communication with the first conductive layer to form another electrode of the capacitor of the present invention, and the capacitor structure of the present invention is completed. … The method of the present invention can be further changed according to the method shown in Figures 2A and ⑼. Reference is made to FIG. 2C, which shows another method of the present invention. After the steps in the first picture proceed to step 选择, choose to execute another-secret step 228. The wet step may cause the first conductive layer to be a third depth from the top surface of the trench, and the second conductive layer to be a fourth depth from the top surface of the trench, where the third depth may be greater than or less than the fourth depth. The distance between each dielectric layer and the top surface of the trench is greater than the third depth and the fourth depth. When the first-connecting conductive layer and the first-conductive layer formed in step 208 are in electrical communication, the step 228 needs to make the fourth depth smaller than the third depth. If the first connected conductive layer and the second conductive layer formed in step 208 are in electrical communication 13 1242292, then the wet-step 228 needs to make the fourth depth greater than the third depth. Step 230 is performed on the substrate, the trench sidewall, the first conductive layer, the second conductive layer, the dielectric layer, and the exposed surface of the -connecting conductive layer, and an insulating layer is formed thereon. And the second insulating layer is etched to expose the first conductive layer or the second conductive layer. Although the second depth is greater than the fourth depth, the second 0 edge layer will cover the first conductive layer and expose the second conductive layer. Conductive layer. When the depth is smaller than the fourth depth, the second insulating layer covers the second conductive layer, and the first conductive layer is exposed. The deposition step 232 is subsequently performed to deposit a second connected conductive layer over the material. When the second insulating layer covers the first conductive layer and the second 4 conductive layer is exposed, the second connecting conductive layer will be in electrical communication with the second conductive layer; if the second insulating layer covers the second conductive layer, When the first conductive layer is exposed, the second connected conductive layer is in electrical communication with the first conductive layer to form: another electrode of the capacitor is invented, and the capacitor structure of the present invention is completed. In the steps of the above 2A to 2C flowcharts, when the material of the first conductive layer can maintain its conductivity after surface treatment, the second electrical material needs to be a conductive material that becomes insulating after surface treatment. If the first type of conductive material becomes an insulating conductive material after the surface treatment, the second type of conductive material needs to be a conductive material that can maintain conductivity after the surface treatment. The material that can be conductive after nitriding can be titanium (Ti) or titanium nitride (TiN); the material that can be conductive after oxygen can be ruthenium, ruthenium oxide, indium tin oxide, or indium oxide. The non-conductive material after oxidation or nitridation can be polycrystalline silicon (ρ_s or sho (A1). The material of the dielectric layer can be various "electric materials" such as nitrogen with a dielectric constant greater than or equal to 3.9 Fossil, oxidized stone, oxidized oxide, oxidized oxide, titanium oxide, hafnium oxide, oxidized oxide, barium titanate, oxidized lock and barium titanate. And 14 1242292 and the layers of each conductive layer and dielectric layer in the trench The number and thickness can be changed according to the needs of the skilled artisan. In order to make the technical description of the present invention clearer, the following preferred embodiments using the technology of the present invention are used to illustrate the manufacture of the multi-electrode capacitor of the present invention. Technology, structure and application fields. A preferred embodiment The first preferred embodiment is to use the manufacturing method of the present invention to produce a trench-type multi-electrode capacitor on a semiconductor substrate. Please refer to FIG. A pad oxide layer 302 and a hard mask 304 are formed on the material 300 to protect the substrate or as a termination layer for the etching or planarization step. Then, a lithography etching technique is used to etch a trench 306 in the semiconductor substrate 300. The trench 306 is completed After the substrate 3 A dopant oxide layer 308 is deposited on the inner surface of the trench 306. The dopant oxide layer 308 is used for performing ion drive in the substrate. Similarly, the photoresist 3 10 is filled in the trench 3 06 with the deposition and dry etching steps, and the structure shown in FIG. 3A can be obtained. When the structure shown in FIG. 3A is completed, the wet process is used to remove the unexposed light. After the dopant oxide layer 308 covered by the resist 310 is removed, the photoresist 310 in the trench II 306 is removed by a procedure familiar to those skilled in the art. Then on the surface of the substrate: the exposed surface of the trench 306 and the remaining Oxygen layer 311 is deposited on the dopant oxide layer. The function of the 311 oxide layer 311 is to prevent diffusion of impurities to the place not covered by the doped oxide layer during the ion driving step. After performing the ion driving step, The doped region 312 can be generated in the substrate, and the structure shown in FIG. 3B is obtained. The doped region 312 is used to make an electrical connection with the conductive layer of the capacitor. 15 1242292 Complete the ion driving step to form After the doped region 312, a wet etching step is performed to oxidize the oxide layer 311 and the doped oxide in FIG. 3B. The layer 308 is completely removed. On the inner wall of the trench 306, a first conductive layer Η #, a first = electric layer 316, a second conductive layer 318, a second dielectric layer 32, and a third conductive layer are sequentially deposited: 322, second dielectric layer 324, fourth conductive layer 326, fourth dielectric layer Mg, = five conductive layer 33G, fifth dielectric layer 332, sixth conductive layer, sixth dielectric layer 336, seventh The conductive layer 338 and the seventh dielectric layer 340 are deposited, and the eighth conductive layer 342 is deposited until the trench is filled. A planarization step or a money engraving step is performed so that the top surfaces of the conductive layers and the dielectric layers in the trench are exposed, and :, The hard cover 304 forms a coplanar flat surface, and the structure shown in FIG. 3c can be completed. The first conductive layer 314, the third conductive layer 322, the fifth conductive layer 33, and the seventh conductive layer 338 may use titanium nitride (TiN); the second conductive layer 318, the fourth conductive layer 326, and the sixth conductive layer. 334 and the eighth conductive layer 342 can be made of poly silicon; the materials of the first dielectric layer 316 to the seventh dielectric layer 340 can be made of various materials with a high dielectric constant, such as nitride nitride (N). ^ After the structure of the multi-layer conductive layer in FIG. 3C is completed, a dry etching step is performed to remove part of the conductive layer and the dielectric layer in the trench to the depth. Subsequently, a wet etching step is performed. For example, a buffered hydrofluoric acid buffer (BHF) is used to etch each conductive layer and the dielectric layer in the trench, so that there is a height difference between the conductive layer and the dielectric layer in the trench. , And get the structure as shown in Figure 30. FIG. 3E is an enlarged view of the grid 344 in FIG. 3D, which shows that the second conductive layer 318, the fourth conductive layer 326, the sixth conductive layer 334, and the eighth conductive layer 342 made of polycrystalline silicon have the slowest etching rates. , So two degrees are the highest. The first conductive layer 314 and the third conductive layer 16 made of titanium nitride 16 1242292 are the second silver engraving rate of 322, the fifth conductive layer 33 and the seventh conductive layer 338, and the dielectric layer has the fastest remaining etching speed. So it has the lowest height. (Refer to Figure 3F.) The first insulation layer 346 is deposited on the inner wall of the trench and the exposed surfaces of the conductive layers and dielectric layers, and fills the gaps between the conductive layers and the dielectric layers in the trench. At this time, the enlarged structure at ~ 344 in Figure 3F is as shown in Figure 3G. Referring to FIG. 3H, the dry-engraving step is performed to remove part of the first-insulating layer 346 to expose the second conductive layer 318, the fourth conductive layer, the sixth conductive layer 334, and the eighth conductive layer 342. At this moment, the enlarged structure of the second figure: square = 344 is shown in figure 31. Fig. 3i shows the second conductive layer 318 and the fourth conductive layer M after the first insulating layer is removed. The top surfaces of the first and the eighth conductive layers 334 and 342 are exposed. The side walls of the first-conductive layer 314, the third conductive layer 322, the fifth conductive layer 33 (), the seventh layer, the electrical layer 338, and the trench 306 are still covered by the first insulating layer 346. When the structure of FIG. 31 is completed, a __th conductive conductive layer 348 is deposited on the substrate until the trench 306 is filled. Subsequently, a planarization step is performed, such as chemical mechanical polishing, to remove the first-connected conductive layer on the surface of the substrate until exposed: the hard mask 304 becomes the structure shown in FIG. 3J. Please refer to FIG. 3J. When the first-connecting conductive layer 348 is electrically connected to the second conductive layer 318, the fourth second layer 326, the sixth conductive layer 334, and the eighth conductive layer, it becomes the first group in the valley. electrode. After forming the structure in FIG. 3J, a pad oxide layer 35, a nitride layer 352, and a mask 354 are sequentially deposited on the substrate 300 and the first insulating layer 348. The conventional lithographic etching technique is used to remove the first conductive conductive layer 348 on the half of the trench as a reference, and a part of the second conductive layer 17 1242292 3U, the fourth conductive layer 326, and the sixth conductive layer are exposed. The layer 334 and the eighth conductive layer can obtain the structure shown in FIG. 3K. The mask layer 354 and a portion of the nitride layer 352 can be subsequently removed using dry etching or wet etching steps. A wet etching step is performed to remove the first- 移除 layer 346 which is not covered by the first connected conductive layer 348, so that the first conductive layer 314, the third conductive layer 322, the second = layer 330, and the seventh The top surface of the conductive layer 338 is exposed. You can get the structure shown in the = 3L diagram. Fig. 3M is a graph of the square milk in the first few figures, which is used to show that the second conductive layer 318, the fourth conductive layer, and the first layer 334 and the first conductive layer 342 have the highest height. The heights of the first-conductive layer 314, the third conductive layer 322, the fifth conductive layer 330, and the seventh conductive layer 338 made of titanium nitride are the second highest. The dielectric layers have the lowest height.
請參考第3N®，執行氮化步驟使得㈣為多晶妙之第 二導電層318、帛四導電層326、第六導電層叫與第八導 電層342之暴露面上產生電性絕緣的氮化矽層356。而材質 為钦或氮化鈦之第-導電層314、第三導電層322、第五導 電層330與第七導電層338的暴露面上產生的氮化層則能 導電。再沈積第二連通導電$ 358(例如氮化鈦）覆蓋在基材 上’使第—導電層314、第三導電層322、第五導電層33〇 與第七導電層338之間電性連通，並透過第一導電層314 與摻雜區312連接而形成電容之第二組電極。沈積第二絕 緣層360直至溝渠填滿，並執行平坦化步驟後便可得到第 3N圖的結構。方格355之局部放大圖則如第3〇圖所示。 可利用習知的乾或濕蝕刻技術來移除部分的第二連通 導電層358與第二絕緣層36〇,使得第二連通導電層僅與第 18 1242292 -導電層314、第二導電層322、第五導電層别與第七導 電層338電性連接，而與第一連通導電層348電性絕緣， 請參考第3P圖所示之結構。最後將第三絕緣層％】沈積在 基材上方4到填滿溝渠，並執行平坦化步驟來移除基材3〇〇 上方之第三絕緣層362與氮化層352,即可完成如第3Q圖 所不之溝渠式多電極電容。其中第—連通導電層348可透 過導線來連接至電晶體之沒極，並利用電容内的多層電極 結構所組成的電容來儲存電荷。 1二較佳實施例 第二較佳實施例係利用本發明之製造方法在半導體元 件之電晶體上方的絕緣層巾造出堆疊式多電極電容。 第4A圖係繪示在半導體基材400上完成電晶體402與 内金屬連線傷後的基材剖面圖。在應用本發明方法來製 造堆疊式多電極電容之前，需在製造電晶體402、内金屬連 線406與中介窗插塞4〇4的同時，亦製造出導線彻用來 與多電極電容之部分電極做電性連接。 月參考第4B @ ’係利用微影颠刻技術在絕緣層彻上 敍刻出-溝渠4!2，並暴露出導、線彻之頂面。導線彻 目當於第-較佳實施例中的摻雜區312，係用來與後 續元成之多電極電容中的部分電極做電性連通。 、…·「丨又，叩3如弟一較佳實施例中所 …冑明製造方法，依序在在溝渠41 沈積第-導電層、第一介電声、繁一…^上依序 乐寬盾第一導電層、第二介電層、 導電層、第三介電層、第四導電層、第四介電層、第 19 1242292 五導電展、μ 導電層i第介電層、第六導電層、第六介電層、第七 此時，第—；|一電層，並沈積第八導電層直至填滿溝渠。 第四、:、第三、第五、第七導電層可使用鈦（Ti);第二、 層之絲％Γ與第八導電層則可使用铭（A1);第—至第七介電 (SiN)。’則可以是各種高介電常數之材質，例如氮化矽 疋成4渠内之各導電層與介電層後的後續製程 一較佳警士― / ^ 例中敘述之步驟相同。當依照第一較佳實施例Please refer to 3N®. Perform the nitriding step to make the second conductive layer 318, the fourth conductive layer 326, the sixth conductive layer, and the eighth conductive layer 342 to be electrically insulating nitrogen.化 硅 层 356。 Silicon layer 356. The nitride layers formed on the exposed surfaces of the first conductive layer 314, the third conductive layer 322, the fifth conductive layer 330, and the seventh conductive layer 338 made of silicon or titanium nitride can conduct electricity. Then deposit a second conductive conductive $ 358 (such as titanium nitride) on the substrate to make the first conductive layer 314, the third conductive layer 322, the fifth conductive layer 33 and the seventh conductive layer 338 in electrical communication. And is connected to the doped region 312 through the first conductive layer 314 to form a second group of electrodes of the capacitor. The second insulation layer 360 is deposited until the trench is filled and a planarization step is performed to obtain the structure of FIG. 3N. A partial enlarged view of the square 355 is shown in FIG. 30. A portion of the second connected conductive layer 358 and the second insulating layer 36 may be removed by using a conventional dry or wet etching technique, so that the second connected conductive layer is only 18th to 1242292 to the conductive layer 314 and the second conductive layer 322. The fifth conductive layer is electrically connected to the seventh conductive layer 338, and is electrically insulated from the first connected conductive layer 348. Please refer to the structure shown in FIG. 3P. Finally, a third insulating layer is deposited on the substrate 4 to fill the trench, and a planarization step is performed to remove the third insulating layer 362 and the nitride layer 352 above the substrate 300, which can be completed as The trench-type multi-electrode capacitors are not shown in the 3Q picture. The first-connected conductive layer 348 can be connected to the electrode of the transistor through a wire, and uses a capacitor composed of a multilayer electrode structure in the capacitor to store electric charges. Twelve Preferred Embodiments The second preferred embodiment uses the manufacturing method of the present invention to fabricate a stacked multi-electrode capacitor over an insulating layer of a semiconductor element over a transistor. FIG. 4A is a cross-sectional view of the substrate after the transistor 402 and the inner metal wire are wound on the semiconductor substrate 400. FIG. Before the method of the present invention is used to manufacture a stacked multi-electrode capacitor, the transistor 402, the inner metal connection 406 and the intermediary window plug 404 need to be manufactured, and at the same time, the part of the wire used for the multi-electrode capacitor is also manufactured The electrodes are electrically connected. The reference 4B @ ′ system uses the lithography technique to etch out the trenches 4! 2 on the insulation layer, and exposes the top surfaces of the guides and wires. The wires serve as the doped regions 312 in the first preferred embodiment, and are used to electrically communicate with some of the electrodes in the multi-electrode capacitor of the subsequent element. ..... again, 叩 3 is as described in the preferred embodiment of 一. 胄 Ming manufacturing method, sequentially depositing the first-conductive layer, the first dielectric sound, and the first one on the trench 41 ... ^ Broad shield first conductive layer, second dielectric layer, conductive layer, third dielectric layer, fourth conductive layer, fourth dielectric layer, 19th 1242292 five-conductance exhibition, μ conductive layer, i-th dielectric layer, Six conductive layers, sixth dielectric layers, seventh at this time, the first-; | an electrical layer, and the eighth conductive layer is deposited until the trench is filled. The fourth, third, fifth, and seventh conductive layers may be Titanium (Ti) is used; the wire% Γ of the second and eighth layers and the eighth conductive layer can use the inscription (A1); the first to seventh dielectrics (SiN). 'Can be a variety of high dielectric constant materials, For example, after the silicon nitride is formed into four channels, the conductive layers and the dielectric layers are used in the subsequent process. A better policeman-the steps described in the example are the same. When following the first preferred embodiment
斤敘述之步驟分別將第一、第三、第五與第七導電層的電 ^連通而形成電容内之第一組電極，並將第二、第四、第 八與第八導電層電性連通而形成電容内之第二組電極後， 即可得到本發明之堆疊式多電極電容414,其結構如第4(： 圖所示。The steps described are to electrically connect the first, third, fifth, and seventh conductive layers to form a first group of electrodes in the capacitor, and to electrically conduct the second, fourth, eighth, and eighth conductive layers. After the second group of electrodes in the capacitor are connected to form a stacked multi-electrode capacitor 414 according to the present invention, the structure is as shown in FIG. 4 (:).
雖然本發明已以數個較佳實施例揭露如上，然其並非 用以限疋本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍内，當可作各種更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 上述詳說明與附圖能讓本發明之上述和其他目的、特 徵、優點能更明顯易懂，且所附圖式之詳細說明如下·· 第1A圖係繪示習知之多層電極電容的剖面圖，用來顯 示其内部之多層結構。 第1B圖係繪示習知之多層電極電容的上視圖。 第1C圖係繪示習知之多層電極電容的剖面圖，用來顯 20 1242292 示此電 第 示此電 第 程圖。 第 流程圖 第 流程圖 第 第 區〇 容内之各導電層與電極的連接方法。 m圖係繪示習知之多層電極電容的剖面圖用來顯 容内之各導電層與電極的另一種連接方法。 2A圖係繪示本發明之多電極電容_製造方法㈣Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application. [Brief description of the drawings] The above detailed description and drawings can make the above and other objects, features, and advantages of the present invention more comprehensible, and the detailed description of the drawings is as follows: Figure 1A shows the conventional knowledge A cross-sectional view of a multilayer electrode capacitor is used to show the multilayer structure inside. FIG. 1B is a top view of a conventional multilayer electrode capacitor. Figure 1C is a cross-sectional view of a conventional multilayer electrode capacitor, which is used to display the circuit diagram of the circuit. Flowchart Flowchart Flowchart Flowchart No. 0 The method for connecting the conductive layers and electrodes in the capacitor. The m diagram is a cross-sectional view showing a conventional multi-layer electrode capacitor, which is used to show another connection method between the conductive layers and the electrodes in the capacitor. Figure 2A shows the multi-electrode capacitor of the present invention_manufacturing method㈣
2B2B
2C 圖係繪示本發明之多電極電容另一製造方法的 圖係繪示本發明之多電極電容又_製造方法的 3A圖係繪示一半導體基材剖面圖，其具有一溝準。 3B圖係繪示一剖面圖，用來顯示溝渠周圍具有摻雜 第3C圖係繪示一剖面圖，用來顯示半導體基材中的溝 渠内具有多層導電層與介電層之結構。 第3D圖係繪示一剖面圖，用來顯示溝渠内之各導電； 與介電層之間的高度差。 第3E圖係為第3D圖的局部放大圖。 第3F圖係繪示一剖面圖，用來顯示溝渠内各導電層上 方覆蓋一層介電層。 第3G圖係為第3F圖的局部放大圖。 第3H圖係繪示一剖面圖，用來顯示未完成之多電極電 容的結構。 第31圖係為第3H圖的局部放大圖。 第3 J圖係繪示一剖面圖，用來顯示未完成尤多電極電 容的結構。 21 1242292 第3 K圖係έ备- a t η Μ丨年臂不一剖面圖 容的結構。 第3L圖係％示一剖面圖 容的結構。 ，用來顯示未完成之多電極電 ’用來顯示未完成之多電極電 第3Μ圖係為第3L圖的局部放大圖。 第3Ν圖係繪示一剖面圖，用來顯示未完成之 容的結構。 夕电極電 第30圖係為第3Ν圖的局部放大圖。2C is a drawing showing another method for manufacturing the multi-electrode capacitor of the present invention. FIG. 3A is a cross-sectional view of a semiconductor substrate having a groove standard. Figure 3B is a cross-sectional view showing doping around the trench. Figure 3C is a cross-sectional view showing the structure of a multi-layer conductive layer and a dielectric layer in a trench in a semiconductor substrate. Figure 3D is a cross-sectional view showing the height difference between the conductive layer and the dielectric layer in the trench. Figure 3E is a partially enlarged view of Figure 3D. Figure 3F is a cross-sectional view showing a dielectric layer overlying each conductive layer in the trench. Figure 3G is a partially enlarged view of Figure 3F. Figure 3H is a cross-sectional view showing the structure of an unfinished multi-electrode capacitor. Figure 31 is a partially enlarged view of Figure 3H. Figure 3J is a cross-sectional view showing the structure of the unfinished multi-electrode capacitor. 21 1242292 Figure 3 K is prepared-a t η Μ 丨 the structure of the different sections of the year arm. Figure 3L shows the structure of a sectional view. , Used to display the unfinished multi-electrode electricity ′ is used to display the unfinished multi-electrode electricity The 3M picture is a partial enlarged view of the 3L picture. Figure 3N is a cross-sectional view showing the structure of the unfinished contents. Evening Electrode Figure 30 is a partial enlarged view of Figure 3N.
第3Ρ圖係繪示一剖面圖，用來顯示未完成 容的結構。 第3Q圖係繪示一剖面圖，用來顯示應用本發明之較佳 實施例的多電極電容完成結構。 又 第4Α圖係％示一半導體產品剖面圖，用來顯示基材上 方具有電晶體與内連線線路等結構。 第4Β圖係繪示一半導體產品剖面圖，用來顯示在半導 體元件上方之介電層中形成一溝渠。 第4C圖騎示—半導體產品剖面圖，用來顯示利用本 發明方法在半導體產品上方之介電層中製造出堆疊式多電 極電容。 【主要元件符號說明】 102 基材 104 第 一金屬層 106 第一多晶石夕層 108 第 一介電層 110 第二多晶碎層 112 第 二金屬層 114 第三多晶矽層 116 第 二介電層 22 1242292 342 118 :第四多晶矽層 122 :接引線 126 :接引線 130 :導電層 200 :蝕刻步驟 203 :蝕刻步驟 206 :沈積與蝕刻步驟 210 :蝕刻步驟 214 :沈積步驟 218 :沈積步驟 222 :濕蝕刻步驟 226 :沈積步驟 230 :沈積與蝕刻步驟 302 ··墊氧化層 306 :溝渠 3 10 :光阻 312 :摻雜區 316 :第一介電層 320 :第二介電層 324 :第三介電層 328 :第四介電層 332 :第五介電層 336 :第六介電層 340 :第七介電層 344 :方格 120 :第三金屬層 124 :接引線 128 :接引線 132 :導線 202 ··沈積步驟 204 :濕蝕刻步驟 208 :沈積步驟 212 :表面處理 216 :表面處理 220 :蝕刻步驟 224 :沈積與蝕刻步驟 228 :濕蝕刻步驟 232 :沈積步驟 300 :基材 304 :硬罩幕 308 ··摻雜物氧化層 311 :氧化層 314 :第一導電層 318 :第二導電層 322 :第三導電層 326 :第四導電層 330 :第五導電層 334 :第六導電層 338 ··第七導電層 :第八導電層 23 1242292Figure 3P is a cross-sectional view showing the structure of the unfinished volume. Figure 3Q is a cross-sectional view showing a multi-electrode capacitor completion structure to which a preferred embodiment of the present invention is applied. Fig. 4A is a cross-sectional view of a semiconductor product, which is used to show that there are structures such as transistors and interconnect lines above the substrate. Figure 4B is a cross-sectional view of a semiconductor product used to show that a trench is formed in the dielectric layer above the semiconductor device. FIG. 4C is a cross-sectional view of a semiconductor product, which is used to show that a stacked multi-electrode capacitor is manufactured in a dielectric layer above the semiconductor product by using the method of the present invention. [Description of main component symbols] 102 Substrate 104 First metal layer 106 First polycrystalline silicon layer 108 First dielectric layer 110 Second polycrystalline layer 112 Second metal layer 114 Third polycrystalline silicon layer 116 Second Dielectric layer 22 1242292 342 118: fourth polycrystalline silicon layer 122: lead wire 126: lead wire 130: conductive layer 200: etching step 203: etching step 206: deposition and etching step 210: etching step 214: deposition step 218: Deposition step 222: Wet etching step 226: Deposition step 230: Deposition and etching step 302 · Pad oxide layer 306: Trench 3 10: Photoresist 312: Doped region 316: First dielectric layer 320: Second dielectric layer 324: third dielectric layer 328: fourth dielectric layer 332: fifth dielectric layer 336: sixth dielectric layer 340: seventh dielectric layer 344: grid 120: third metal layer 124: lead wire 128 : Lead wire 132: lead wire 202 · deposition step 204: wet etching step 208: deposition step 212: surface treatment 216: surface treatment 220: etching step 224: deposition and etching step 228: wet etching step 232: deposition step 300: substrate Material 304: Hard cover 308. Dopant oxide layer 311: Oxide layer 314: first conductive layer 318: second conductive layer 322: third conductive layer 326: fourth conductive layer 330: fifth conductive layer 334: sixth conductive layer 338 seventh seventh layer: eighth conductive layer 23 1242292
348 :第一連通導電層 346 ： 第一絕緣層 352 :氮化層 350 ： 墊氧化層 355 :方格 354 ： 罩幕 358 :第二連通導電層 356 ·· 氮化層 362 :第三絕緣層 360 ： 第二絕緣層 402 :電晶體 400 ： 基材 406 :内金屬連線 404 ·· 中介窗插塞 410 :絕緣層 408 ： 導線 414 :堆疊式多電極電容 412 ： 溝渠348: first conductive conductive layer 346: first insulating layer 352: nitride layer 350: pad oxide layer 355: grid 354: mask 358: second conductive conductive layer 356 ... nitride layer 362: third insulation Layer 360: Second insulating layer 402: Transistor 400: Substrate 406: Inner metal connection 404. Intermediary window plug 410: Insulating layer 408: Conductor 414: Stacked multi-electrode capacitor 412: Ditch
24twenty four