i 4 3 2 7 .：： 3407twf.doc/005 A7 _____________B7 ___ 五、發明説明（丨） - :γ本發明是有關於一種積體電路的製造方法，且特別是 有關於一種製造動態隨機存取記憶體（Dynamic Random Access Memory，DRAM)之電容器的方法。 當電腦微處理器功能逐漸增強、軟體所進行的程式與運 算愈來愈龐大時，記憶體的電容需求也就愈來愈高。而隨 著動態隨機存取記憶體積集度的增加，目前所發展之記憶 胞係由一個轉移場效電晶體與一個儲存電容器所構成。第1 圖是動態隨機存取記憶體元件之記憶胞的電路示意圖。其 中，由半導體基底表面之電容陣列（Array of Capacitors) 中所篩選出的電容器C，可利用其充放電的特性儲存資料。 最常用的作法，是將二進位的單一位元資料儲存在所有的 電容器中，當未充電時其電容爲邏輯0,而充電後其電容則 爲邏輯1。通常’在電容器C的上電極（胞電極）102與下 電極（儲存電極）100間塡入介電質101，以提供電極間所 需的介電常數，並且將電容器C耦合至一位元線（Bit Line) BL，藉由電容器C的充放電而達到讀寫的目的。而電容器 C其充放電之間的切換工作是透過轉移場效電晶體 (Transfer Field Effect Transistor，TFET) T 以執行之。其 方法是將位元線BL與轉移場效電晶體T的汲極相連，電容 器C與轉移場效電晶體T的源極相接，而字元線（Word Lae) WL的信號則餽入轉移場效電晶體T之閘極，以決定 電容器C是否與位元線BL相連接。 在傳統DRAM的儲存電容量少於(Mega=百萬）位 元時，於積體電路製程中，主要是利用二度空間的電容器 3 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐) _ ----.------Ί^—------IT------.^ (諳先閱讀背面之注意事項再蜞寫本頁) 3407twf.d〇c/〇〇5 A7 __________B7 五、發明説明（γ) 來實現’亦即泛稱的平坦型電容器（Planar Type Capacitor)。由於平坦型電容器需佔用半導體基底相當大 的面積來儲存電荷，故並不適合應用於高度的積集化。高 度積集化的DRAM，例如大於4M位元的儲存電容量者， 需要利用三度空間的電容器來實現，例如所謂的堆疊型 (Stacked Type)或溝槽型（Trench Type)電容器。 與平坦型電容器比較，堆疊型或溝槽型電容器可以在記 憶單元的尺寸進一步縮小的情況下，仍能獲得相當大的電 容量。雖然如此，當記憶體元件再進入更高度積集化時， 例如，具有64M位元容量的DRAM，單純的三度空間電容 器結構已不再適用。 解決的方法之一是將電容器的電極與介電膜層向水平 延伸，並且向上堆疊而形成所謂的鰭型（Fin Type)的堆疊 電容器，使電容器可藉由表面積的增加以增加儲存的電容 量。其相關技術可參考Ema等人的論文“3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs" international Electron Devices Meeting, pp592-595，Dec. 1988。或參考美國專利第5,071，783號、第 5,126,810 號以及第 5,206,787 號。 另一種解決之道則是使電容器的電極與介電膜層延伸 成一垂直狀結構而形成一所謂的柱型（Cylindrical Type) 堆疊電容器，使電容器可藉由表面積的增加以增加其所能 儲存的電容量。其相關技術可參考Wakamiya等人的論文 “Novel Stacked Capacitor Cell for 64Mb DRAM”，丨989 4 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） I---..------1^1------IT------.^ (誚先閲讀背面之注意事項再填寫本頁} 407twf.doc/0〇5 A7 B7 五、發明説明（）） -i 4 3 2 7. :: 3407twf.doc / 005 A7 _____________B7 ___ 5. Description of the Invention (丨)-: γ The present invention relates to a method for manufacturing an integrated circuit, and in particular to a method for manufacturing dynamic random access Capacitor method of memory (Dynamic Random Access Memory, DRAM). As the functions of computer microprocessors are gradually enhanced and the programs and calculations performed by the software are becoming larger and larger, the capacitance requirements of memory are also increasing. With the increase of the dynamic random access memory volume concentration, the currently developed memory cell system consists of a transfer field effect transistor and a storage capacitor. FIG. 1 is a schematic circuit diagram of a memory cell of a dynamic random access memory element. Among them, the capacitor C selected from the Array of Capacitors on the surface of the semiconductor substrate can use its charge and discharge characteristics to store data. The most common method is to store a single bit of binary data in all capacitors. When not charged, the capacitance is logic 0, and when it is charged, the capacitance is logic 1. Generally, a dielectric 101 is inserted between the upper electrode (cell electrode) 102 and the lower electrode (storage electrode) 100 of the capacitor C to provide the required dielectric constant between the electrodes, and the capacitor C is coupled to a bit line (Bit Line) BL achieves the purpose of reading and writing by charging and discharging the capacitor C. The switching operation between the charge and discharge of the capacitor C is performed by a transfer field effect transistor (TFET) T. The method is to connect the bit line BL to the drain of the transfer field effect transistor T, the capacitor C is connected to the source of the transfer field effect transistor T, and the signal of Word Lae WL is fed into the transfer The gate of the field effect transistor T determines whether the capacitor C is connected to the bit line BL. When the storage capacity of traditional DRAM is less than (Mega = million) bits, in the integrated circuit manufacturing process, the capacitor of the second space is mainly used. 3 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (2 丨0X297mm) _ ----.------ Ί ^ -------- IT ------. ^ (谙 Read the precautions on the back before writing this page) 3407twf. d〇c / 〇〇5 A7 __________B7 V. Description of the Invention (γ) to realize 'also known as Planar Type Capacitor'. Since a flat capacitor requires a relatively large area of a semiconductor substrate to store charges, it is not suitable for high accumulation. Highly integrated DRAMs, such as those with a storage capacity greater than 4M bits, need to be implemented using capacitors with three degrees of space, such as so-called stacked type or trench type capacitors. Compared with flat type capacitors, stacked or trench type capacitors can still obtain a considerable capacitance even when the size of the memory cell is further reduced. Nonetheless, when the memory elements are further integrated, for example, a DRAM with a capacity of 64M bits, the simple three-dimensional capacitor structure is no longer applicable. One of the solutions is to extend the capacitor's electrodes and dielectric film layers horizontally and stack them up to form a so-called Fin Type stacked capacitor, so that the capacitor can increase the stored capacitance by increasing the surface area. . For related technologies, refer to the paper "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs" by Ema et al. &Quot; international Electron Devices Meeting, pp592-595, Dec. 1988. Or refer to U.S. Patent Nos. 5,071,783, 5,126,810 and No. 5,206,787. Another solution is to extend the capacitor's electrodes and the dielectric film into a vertical structure to form a so-called Cylindrical Type stacked capacitor, so that the capacitor can increase its surface area by increasing its surface area. Electric capacity that can be stored. For related technologies, please refer to the paper "Novel Stacked Capacitor Cell for 64Mb DRAM" by Wakamiya et al., 989 4 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) I-- -..------ 1 ^ 1 ------ IT ------. ^ (诮 Please read the notes on the back before filling this page} 407twf.doc / 0〇5 A7 B7 Five , Invention description ())-
Symposium on VLSI Technology Digest of Technical Papers, pp 69-70。或參考美國專利第5,077,688號。 隨著積集度不斷地增加，DRAM記憶胞的尺寸仍會繼 續縮小。如熟悉此技藝者所知，記憶胞尺寸的縮小，儲存 電容値亦將減少。而電容値的減少又將造成α射線入射所引 起的軟錯誤（Soft Error)機會的增加。因此，此技藝者仍 不斷在找尋新的儲存電容器結構及其製造方法，藉以使得 在儲存電容所佔的平面縮小的情況下，仍能維持所需之電 容値。 緣此，本發明的主要目的就是在提供一種電容器的製造 方法，藉以使得在儲存電容所佔的平面縮小的情況下，仍 能維持所需之電容値，並能增加製程的容忍度 (Tolerance)，以提昇產品之良率，減少製造的成本。 根據本發明的目的’提出一種動態隨機存取記憶體之電 容器的製造方法，此方法係在覆蓋於基底上的介電層中形 成接觸窗開口之後，在基底上形成一層導體層，使其覆蓋 介電層表面，並且塡入接觸窗開口，與源極/汲極區電性稱 接。接著，再於導體層上形成絕緣層，並將此絕緣層與部 份的導體層圖案化，以使圖案化之絕緣層與部份的導體層 對應於接觸窗開口的上方。其後，在圖案化的絕緣層與導 體層之側壁形成間隙壁，然後’將圖案化的絕緣層去除， 並以間隙壁爲罩幕’將導體層部份回鈾刻。然後，將間隙 壁去除，再於回蝕刻之後’導體層的兩側壁形成另二間隙 壁，並以此二間隙壁罩幕’介電層爲蝕刻終止層，將導體 5 本紙張尺度適用中國國家梯準（CNS ) A4规格（210X297公釐） I----------Ί^— — {請先閲讀背面之注^^項再填寫本頁〕 ,1Τ 恕浐部中""^^^消资合竹^"$,! ^43 92 7 4 3407twf.doc/0Q5 A7 B7 五、發明説明（4 ) . 層回蝕刻，然後，再將二間隙壁去除，以使所留下的導體 層作爲電容器之儲存電極。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1圖是動態隨機存取記憶體元件之記憶胞的電路示 意圖；以及 請參照第2A圖至第2F圖，其繪示依照本發明一較佳 實施例的一種動態隨機存取記憶體的製造流程剖面圖。 圖式標記說明： C :電容器 T，201 :場效電晶體 BL :位元線 WL :字元線 100 :下電極 101，222 :介電膜層 102 :上電極 200 :基底 202 :場氧化層 206 :源極/汲極區 207 * 216，2〗7，218 :間隙壁 208 :介電層 210 :接觸窗開口 6 本紙張尺度適用中國國家標準（CNS ) A4#見格（210X 297公釐） I----------11-------ir------.^ ("先閱讀背面之注意事項再填寫本頁) ^ 4 3 9 2 ： 4. 3407twf . doc/005 β^η ______________B7 五、發明説明（f) 212，212a，212b，212c，224 :導體層 214，214a :絕緣層 230，240，250 :側壁 實施例 請參照第2A圖至第2F圖，其繪示依照本發明一較佳 實施例的一種動態隨機存取記憶體之電容器的製造流程剖 面圖。 請參照第2A圖，首先，在所提供的基底2〇〇表面上， 形成場隔離區202以定義元件之主動區，續再於基底2〇〇 的主動區上形成動態隨機存取記憶體的場效電晶體2〇1。接 著，再於基底200上覆蓋一層介電層208 ^ 其中，基底200的材質例如爲p型矽基底；場隔離區 202的形成方法例如爲局部區域氧化法（LOCOS)或淺溝 渠隔離法（STI)。典型形成場效電晶體201的方法係先以 熱氧化法於基底200上形成一層薄氧化層，然後，再於閘 極氧化層上依序形一層導體層與一層絕緣層，接著，將此 三層圖案化，以形成閘極氧化層203、導體閘極204與閘極 頂蓋層2〇5。然後，再於基底200中摻入雜質，以形成源極 /汲極區206。接著，在基底200上覆蓋一層絕緣層並進行 冋蝕刻，以在閘極氧化層203、導體閘極2〇4與閘極頂蓋層 205之側壁形成間隙壁2〇7。其中，導體閘極204之材質例 如爲摻雜的複晶矽，形成的方法例如爲化學氣相沈積法 (CVD);閘極頂蓋層205與間隙壁之材質例如爲氮化矽’ 形成的方法例如爲化學氣相沈積法。介電層208之材質則 7 本紙張尺廋適用中國國家標準（CNS ) Α4规格（210Χ297公釐） ： ^------—^:------ΐτ------.^ (誚先閲讀背韵之注意事項再填寫本育) ψ -: \ ' 3407twf.d〇c/005 Α7 ___— __Β7_ 五、發明説明（t ) — 包括氧化矽或硼磷矽玻璃（BPSG)，形成的方法例如爲化 學氣相沈積法= 接著，請參照第2B圖，將介電層208圖案化，以形成 接觸窗開口 210，裸露出源極/汲極區206。然後，在基底 2〇〇上形成一層導體層212，使其覆蓋介電層208的表面， 並且塡入接觸窗開口 210中，與源極/汲極區206電性耦 接。接著，再於導體層212上形成一層絕緣層214。其中， 導體層212之材質包括摻雜複晶矽，形成的方法例如爲化 學氣相沈積法；絕緣層之材質則包括氮化矽，形成的方法 亦可使用化學氣相沈積法。 其後，請參照第2C圖，定義絕緣層214與部份的導體 層212,以使圖案化之絕緣層214a與部份的導體層212a對 應於接觸窗開口 210的上方。然後，再於圖案化之絕緣層 214a與導體層212a之側壁230形成間隙壁216。典型的方 法係在絕綠層214上形成一層圖案化的光阻層，然後，再 以此光阻層爲蝕刻罩幕，依序蝕刻絕緣層214與部份的導 體層212，其後，將光阻層剝除的方式以形成圖案化之絕緣 層214a與導體層212a。其中，間隙壁216之材質與導體層 212具有不同的蝕刻率，當導體層之材質爲摻雜複晶矽時， 較佳的間隙壁216之材質包括氧化矽，其形成的方法，例 如以化學氣相沈積法，在基底200上覆蓋一層氧化矽，然 後，再經由回飩刻，以在圖案化之絕緣層214a與導體層2〗2a 之側壁230形成氧化矽材質之間隙壁216。 然後，請參照第2D圖’去除絕緣層214a’裸露出導體 8 J-----------------ΪΤ------象、 (讀先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家樣準（CNS ) A4規格（210X297公釐） 34〇7tWf'd〇C/〇05 A7 ------ 67 五、發明説明（？ ) —--- 層212。然後，以間隙壁216爲蝕刻罩幕，進行回蝕刻，以 去除部份的導體層212a，使所留下的導體層2121)具有內側 壁240與外側壁25〇。其中，去除絕緣層η粍的方式包括 濕式蝕刻法’例如，使用磷酸爲餓刻溶液，以去除絕緣層 214a 而去除部份的導體層212&的方式，例如以以間隙壁 216爲蝕刻罩幕，利用非等向性飩刻的方式，以使部份的導 體層212 a回蝕刻。 接者，請參照第2E圖，去除間隙壁216，再於導體層 212b之內側壁240與外側壁25〇 ,分別形成間隙壁217與 218。其中，去除間隙壁216的方法包括濕式蝕刻法，例如 使用氫氟酸（HF)溶液；而間隙壁217與218之材質與導 體層212具有不同的蝕刻率，當導體層之材質爲摻雜複晶 矽時，較佳的間隙壁217與218之材質包括氧化矽，其形 成的方法’例如以化學氣相沈積法，在基底2〇〇上覆蓋一 層氧化矽，然後，再經由回蝕刻，以在導體層212b之內側 壁240與外側壁25〇，分別形成間隙壁2n與218。 其後，請參照第2F圖，以間隙壁217與218爲蝕刻罩 幕’介電層208爲蝕刻終止層，進行回蝕刻，以去除部份 的導體層212b，使所留下的多環柱狀導體層212c作爲儲存 電極之架構。接著，去除間隙壁2Π與21S，並於導體層 212c所裸露出的表面上形成依序一層介電膜層222與導體 層2M。其中，去除部份導體層2〗2b的方法包括非等向性 蝕刻法；去除間隙壁217與218的方法包括濕式蝕刻法。 介電膜層226之材質例如爲氧化矽、氮化矽層/氧化矽層 9 卜國國家標準（CNS〉A4規格（210X297公釐） ~ I ~ H „ 11 n ^ ~ I. i I n 訂^~ 1 n 1 ~ 線 (誚先閲讀背面之注^項再填寫本頁) «5439274 34〇7twf . doc/ 005 八7 —_____ B7 五、發明説明（？） - (NO)結構、氧化矽層/氮化矽層/氧化矽層（ΟΝΟ)結構 或五氧化二鉅（Ta2〇5)、Pb ( Zr，Ti) 〇3，即 ΡΖΤ 以及（Ba， Sr) Ti〇3 ’即BST等高介電常數的材料。導體層228之材 質例如爲摻雜複晶矽，形成的方法例如爲化學氣相沈積 法，在沈積複晶矽層的同時摻入雜質。 因此’根據以上實施例所述，本發明之特徵是所形成之 儲存電極呈多環柱狀’可以使電容器之有效表面積大大地 增加’以大幅提昇動態隨機存取記憶體之電容器其儲存電 荷的能力。 雖然本發明已以一較佳實施例揭露如上，然其並非用以 限定本發明’任何熟習此技藝者’在不脫離本發明之精神 和範圍內’當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 ί Γ I . n I. I I 訂 练 {誚先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家襟準（CNS ) A4規格（2IOX297公釐）Symposium on VLSI Technology Digest of Technical Papers, pp 69-70. Or refer to US Patent No. 5,077,688. As the degree of accumulation continues to increase, the size of DRAM memory cells will continue to shrink. As those skilled in the art know, the shrinking memory cell size will also reduce the storage capacitance. The decrease of the capacitance chirp will increase the chance of soft errors caused by the incidence of alpha rays. Therefore, the artist is still looking for new storage capacitor structures and manufacturing methods, so that the required capacitance can be maintained even when the plane occupied by the storage capacitor is reduced. For this reason, the main object of the present invention is to provide a method for manufacturing a capacitor, so that the required capacitance can be maintained while the plane occupied by the storage capacitor is reduced, and the tolerance of the process can be increased. In order to improve the yield of products and reduce manufacturing costs. According to the purpose of the present invention, a method for manufacturing a capacitor of a dynamic random access memory is proposed. After the contact window opening is formed in a dielectric layer covered on a substrate, a conductive layer is formed on the substrate to cover it. The surface of the dielectric layer penetrates into the opening of the contact window, and is electrically connected to the source / drain region. Next, an insulating layer is formed on the conductive layer, and the insulating layer and a part of the conductive layer are patterned so that the patterned insulating layer and a part of the conductive layer correspond to the opening of the contact window. Thereafter, a gap wall is formed on the sidewalls of the patterned insulating layer and the conductor layer, and then the patterned insulating layer is removed, and the conductor layer is partially etched back to the uranium with the gap wall as a cover. Then, the spacer is removed, and after the etchback, another two spacers are formed on the two side walls of the conductor layer, and the dielectric layer of the two spacers is used as the etching stop layer. Ladder (CNS) A4 specification (210X297 mm) I ---------- Ί ^ — — {Please read the note ^^ on the back before filling out this page], 1Τ In the Ministry of Justice " " ^^^ 消 资 合 竹 ^ " $ ,! ^ 43 92 7 4 3407twf.doc / 0Q5 A7 B7 V. Description of the invention (4). The layer is etched back, and then the two spacers are removed to make The remaining conductor layer serves as a storage electrode for the capacitor. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: Figure 1 is dynamic A schematic circuit diagram of a memory cell of a random access memory element; and FIG. 2A to FIG. 2F are cross-sectional views illustrating a manufacturing process of a dynamic random access memory according to a preferred embodiment of the present invention. Description of graphical symbols: C: capacitor T, 201: field effect transistor BL: bit line WL: word line 100: lower electrode 101, 222: dielectric film layer 102: upper electrode 200: substrate 202: field oxide layer 206: source / drain region 207 * 216, 2〗 7, 218: spacer 208: dielectric layer 210: contact window opening 6 This paper size applies to China National Standard (CNS) A4 # see grid (210X 297 mm) ) I ---------- 11 ------- ir ------. ^ (&Quot; Read the notes on the back before filling in this page) ^ 4 3 9 2 ： 4 3407twf .doc / 005 β ^ η ______________ B7 V. Description of the Invention (f) 212, 212a, 212b, 212c, 224: Conductor layer 214, 214a: Insulation layer 230, 240, 250: For examples of side walls, please refer to FIG. 2A to FIG. 2F is a cross-sectional view showing a manufacturing process of a capacitor of a dynamic random access memory according to a preferred embodiment of the present invention. Please refer to FIG. 2A. First, a field isolation region 202 is formed on the surface of the provided substrate 200 to define an active region of the device, and then a dynamic random access memory is formed on the active region of the substrate 200. Field effect transistor 201. Next, a dielectric layer 208 is covered on the substrate 200. The material of the substrate 200 is, for example, a p-type silicon substrate; the formation method of the field isolation region 202 is, for example, a local area oxidation method (LOCOS) or a shallow trench isolation method (STI). ). A typical method for forming the field effect transistor 201 is to first form a thin oxide layer on the substrate 200 by a thermal oxidation method, and then sequentially form a conductor layer and an insulating layer on the gate oxide layer. Layer patterning to form a gate oxide layer 203, a conductor gate 204, and a gate cap layer 205. Then, impurities are doped into the substrate 200 to form a source / drain region 206. Next, a substrate 200 is covered with an insulating layer and etched to form a gap wall 207 on the sidewalls of the gate oxide layer 203, the conductor gate 204, and the gate cap layer 205. The material of the conductive gate 204 is, for example, doped polycrystalline silicon, and the method of forming the conductive gate 204 is, for example, chemical vapor deposition (CVD); the material of the gate cap layer 205 and the spacer is, for example, silicon nitride. For example, it is a chemical vapor deposition method. The material of the dielectric layer 208 is 7 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm): ^ ------— ^: ------ ΐτ ------ . ^ (诮 Read the notes on the rhyme first and then fill in this education) ψ-: \ '3407twf.d〇c / 005 Α7 ___ — __Β7_ 5. Description of the Invention (t) — Including silicon oxide or borophosphosilicate glass (BPSG ), For example, a chemical vapor deposition method = Next, referring to FIG. 2B, the dielectric layer 208 is patterned to form a contact window opening 210 and the source / drain regions 206 are exposed. Then, a conductive layer 212 is formed on the substrate 200 so as to cover the surface of the dielectric layer 208, and is inserted into the contact window opening 210 to be electrically coupled to the source / drain region 206. Next, an insulating layer 214 is formed on the conductor layer 212. Wherein, the material of the conductive layer 212 includes doped polycrystalline silicon, and the formation method is, for example, a chemical vapor deposition method; the material of the insulation layer includes silicon nitride, and the method of formation may also use a chemical vapor deposition method. Thereafter, referring to FIG. 2C, the insulating layer 214 and a portion of the conductive layer 212 are defined so that the patterned insulating layer 214a and a portion of the conductive layer 212a correspond above the contact window opening 210. Then, a spacer 216 is formed on the sidewall 230 of the patterned insulating layer 214a and the conductive layer 212a. A typical method is to form a patterned photoresist layer on the green insulating layer 214, and then use this photoresist layer as an etching mask to sequentially etch the insulating layer 214 and a portion of the conductor layer 212, and then, The photoresist layer is stripped to form a patterned insulating layer 214a and a conductive layer 212a. Wherein, the material of the spacer 216 and the conductor layer 212 have different etch rates. When the material of the conductor layer is doped polycrystalline silicon, a better material of the spacer 216 includes silicon oxide. In the vapor deposition method, a layer of silicon oxide is covered on the substrate 200, and then, a spacer 216 made of silicon oxide is formed on the patterned insulating layer 214a and the sidewall 230 of the conductor layer 2a through back engraving. Then, please refer to FIG. 2D, 'removing the insulating layer 214a' and exposing the conductor 8 J --------------------- Τ ------ image, (read first read the back Please fill in this page for the matters needing attention) This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) 34〇7tWf'd〇C / 〇05 A7 ------ 67 V. Description of the invention (?) ----- layer 212. Then, the spacer wall 216 is used as an etching mask to perform an etch-back to remove a part of the conductive layer 212a, so that the remaining conductive layer 2121) has an inner wall 240 and an outer wall 250. Among them, the method for removing the insulating layer η 蚀刻 includes a wet etching method. For example, using phosphoric acid as the etching solution to remove the insulating layer 214a and remove a part of the conductor layer 212 & In order to etch back a part of the conductive layer 212 a, the method is performed using anisotropic etching. Then, referring to FIG. 2E, the spacer 216 is removed, and then the spacers 217 and 218 are formed on the inner side wall 240 and the outer side wall 25 of the conductive layer 212b, respectively. Among them, the method for removing the spacer 216 includes a wet etching method, such as using a hydrofluoric acid (HF) solution; and the material of the spacers 217 and 218 and the conductor layer 212 have different etching rates. When the material of the conductor layer is doped, In the case of polycrystalline silicon, a preferred material for the spacers 217 and 218 includes silicon oxide, and the method of forming the same, for example, by chemical vapor deposition, covers a layer of silicon oxide on the substrate 200, and then etches back. Spacers 2n and 218 are formed on the inner sidewall 240 and the outer sidewall 250 of the conductive layer 212b, respectively. Thereafter, referring to FIG. 2F, the spacers 217 and 218 are used as the etching mask, and the dielectric layer 208 is used as the etching stop layer. Etching is performed to remove a part of the conductor layer 212b, so that the remaining multi-ring pillars are left. The conductor-like layer 212c serves as a framework for the storage electrode. Next, the spacers 2Π and 21S are removed, and a dielectric film layer 222 and a conductor layer 2M are sequentially formed on the exposed surface of the conductor layer 212c. Among them, a method of removing a part of the conductor layer 2b 2b includes an anisotropic etching method; a method of removing the spacers 217 and 218 includes a wet etching method. The material of the dielectric film layer 226 is, for example, silicon oxide, silicon nitride layer / silicon oxide layer 9 National Standard of China (CNS> A4 specification (210X297 mm) ~ I ~ H „11 n ^ ~ I. i I n Order ^ ~ 1 n 1 ~ Line (诮 Please read the note ^ on the back before filling this page) «5439274 34〇7twf .doc / 005 8 7 —_____ B7 V. Description of the invention (?)-(NO) structure, silicon oxide Layer / silicon nitride layer / silicon oxide layer (〇ΝΟ) structure or pentoxide (Ta205), Pb (Zr, Ti) 〇3, namely PTZ and (Ba, Sr) Ti〇3 ', namely BST The material of the dielectric constant. The material of the conductor layer 228 is, for example, doped polycrystalline silicon, and the formation method is, for example, a chemical vapor deposition method, and impurities are deposited while depositing the polycrystalline silicon layer. The feature of the present invention is that the formed storage electrode has a multi-ring column shape, which can greatly increase the effective surface area of the capacitor, to greatly improve the capacity of the capacitor of the dynamic random access memory to store charge. Although the present invention has The preferred embodiment is disclosed above, but it is not intended to limit the present invention to 'anyone skilled in the art' Without departing from the spirit and scope of the present invention, 'it can be modified and retouched. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application. Γ I. N I. II Subscription {诮 Please read the notes on the back before filling in this page) This paper size applies to China National Standard (CNS) A4 specification (2IOX297 mm)