TW392338B - Method for manufacturing DRAM capacitors - Google Patents

Abstract

A method for manufacturing DRAM capacitors is disclosed, which first sequentially forms and defines a silicon nitride etching stop layer, a first isolation layer, a first conductive layer and a second isolation layer, so as to form the opening for a contact window. Then, a second conductive layer is formed on the surface of the second isolation layer and in the opening. Next, the second conductive layer is patterned, and a second silicon nitride layer is formed on the spacer thereof. Subsequently, part of the second isolation layer and first conductive layer are removed by using the second silicon nitride layer as a mask for exposing the surface of the first isolation layer. Next, a third conductive layer is formed on the substrate, and part of the third conductive layer is removed to expose the surfaces of the second silicon nitride layer and part of the first isolation layer. Finally, the second silicon nitride layer, the second isolation layer and the first isolation layer are removed to expose the lower electrode structure formed by the first, second and third conductive layers.

Description

3232twf.doc / 005 ---__ B7 ^ ______ V. Description of the invention (I) — The present invention relates to a method for manufacturing integrated circuits, and in particular The invention relates to a method for manufacturing a capacitor of Dynamic Random Access Memory (Memory 'DRAM). As the functions of computer microprocessors are gradually enhanced and the programs and calculations performed by the software are becoming larger and larger, the capacitance requirements of memory are also increasing. With the increase of the dynamic random access memory volume concentration, the currently developed memory cell system consists of a transfer field effect transistor and a storage capacitor. FIG. 1 is a schematic circuit diagram of a memory cell of a dynamic random access memory element. Among them, capacitor C, which is selected from the array of capacitors on the surface of the semiconductor substrate, can use its charge and discharge characteristics to store data. The most common method is to store a single bit of binary data in all capacitors. When not charged, the capacitance is logic 0, and when charged, the capacitance is logic 1. Generally, a dielectric 101 is inserted between the upper electrode (cell electrode) 102 and the lower electrode (storage electrode) 100 of the capacitor C to provide the required dielectric constant between the electrodes, and the capacitor C is coupled to one bit. The bit line BL 'achieves the purpose of reading and writing by charging and discharging the capacitor C. The switching operation between the charge and discharge of the capacitor C is performed by a transfer field effect transistor (TFET) T. The method is to connect the bit line BL to the drain of the transfer field effect transistor T, the capacitor C is connected to the source of the transfer field effect transistor T, and the signal of the word line WL is fed into the transfer The gate of the field effect transistor T determines whether the capacitor C is connected to the bit line BL. When the storage capacity of traditional DRAM is less than 1M (Mega = million) bits, in the integrated circuit manufacturing process, the capacitor of the second space is mainly used. 3 The paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297). (Mm) (Please read the precautions on the back and fill in this page first)-Pack., Ιτ d · 3232twf.doc / 005 A7 B7 Printed by the Central Bureau of Procurement of the Ministry of Economic Affairs J. Consumer Cooperatives V. Invention Description (> ) To achieve, also known as the Planar Type Capacitor. Since a flat capacitor requires a relatively large area of a semiconductor substrate to store charges, it is not suitable for high accumulation. Highly integrated DRAMs, such as those with a storage capacity of more than 4M bits, need to be realized using a three-dimensional capacitor, such as a so-called stacked type or trench type capacitor. Compared with flat type capacitors, stacked or trench type capacitors can still obtain a considerable capacitance even when the size of the memory cell is further reduced. Nonetheless, when the memory elements are further integrated, for example, a DRAM with a capacity of 64M bits, the simple three-dimensional capacitor structure is no longer applicable. One of the solutions is to extend the capacitor's electrodes and dielectric film layers horizontally and stack them up to form a so-called Fin Type stacked capacitor, so that the capacitor can increase the stored capacitance by increasing the surface area. . For related technologies, please refer to the paper "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs" by Ema et al. &Quot; international Electron Devices Meeting, pp592-595, Dec. 1988. Or refer to US Patent Nos. 5,071,783, 5,126,810 No. and No. 5,206,787. Another solution is to extend the capacitor's electrodes and the dielectric film into a vertical structure to form a so-called cylindrical type capacitor, which can increase the surface area of the capacitor. The electric capacity that can be stored. For related technology, please refer to the paper "Novel Stacked Capacitor Cell for 64Mb DRAM" by Wakamiya et al., 1989 4 This paper size is applicable to China National Standard (CNS) A4 specification (2 丨 0X297 mm) (Please read the notes on the back before filling this page)

, 1T Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Hong Kong 3232twf.doc / 005 A7 _B7 Five 'Explanation of Invention (Today)

Symposium on VLSI Technology Digest of Technical Papers, pp 69-70. Or refer to US Patent No. 5,077,688. As the degree of accumulation continues to increase, the size of the DRAM memory cell will continue to shrink. As those skilled in the art know, the shrinking memory cell size will also reduce the storage capacitance. The decrease of the capacitance chirp will increase the chance of soft errors caused by the incidence of alpha rays. Therefore, this artist is still looking for a new storage capacitor structure and manufacturing method, so that the required capacitance can be maintained even when the plane occupied by the storage capacitor is reduced. Therefore, the main purpose of the present invention It is to provide a method for manufacturing a capacitor, so that the required capacitance can be maintained while the plane occupied by the storage capacitor is reduced, and the tolerance of the process can be increased to improve the yield of the product. Reduce manufacturing costs. According to the purpose of the present invention, a method for manufacturing a capacitor of a dynamic random access memory is proposed. After forming a field-effect transistor on a provided substrate, a dielectric layer and a nitride are sequentially formed and defined on the substrate. The silicon etching stop layer, the first insulating layer, the first conductor layer and a second insulating layer form a contact window opening, exposing the source / drain regions of the field effect transistor. Then, a second conductor layer is formed on the substrate so as to cover the surface of the second insulating layer, and is inserted into the contact window opening to be electrically coupled to the source / drain region. Next, the second conductor layer is patterned, and a second silicon nitride layer is formed on the sidewall. Then, the second silicon nitride layer is used as a mask to remove a portion of the second insulating layer and the first conductor layer. A part of the surface of the first insulating layer is exposed. After that, a third conductor layer conforming to the surface of the element is formed on the substrate, and it will cover the second 5 This standard applies to the Chinese national standard ^ M CNS) 4 specifications (210X297 cm) " 1.1 _-- 1- -: --Γ outfit-(Please read the precautions on the back before filling this page) Stitching in the Shoulder J-Consumer Hezhu Society Printing Purple 3232twf.doc / 005 A7 __B7_ V. Invention Explanation (+) The third conductor layer of the silicon nitride layer and the third conductor layer partially covering the first insulating layer are removed to expose the surfaces of the second silicon nitride layer and part of the first insulating layer. Then, the second silicon nitride layer, the second insulating layer, and the first insulating layer are sequentially removed, and the structure of the lower electrode composed of the first, second, and third conductor layers is exposed. Then, the lower electrode is exposed. A dielectric film layer and a fourth conductor layer are sequentially formed and defined on the surface to complete the fabrication of the capacitor. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: Figure 1 is dynamic A schematic circuit diagram of a memory cell of a random access memory element; and FIGS. 2A to 2H are cross-sectional views illustrating a manufacturing process of a dynamic random access memory according to a preferred embodiment of the present invention. Description of graphical symbols: C: capacitor T, 201: field effect transistor BL: bit line WL: word line 100: lower electrode 101, 226: dielectric film layer 102: upper electrode 200: substrate 202: field oxide layer 6 This paper is compliant with China National Standard (CNS) Λ4 specification (2 丨 0X297 male H ~ (Please read the precautions on the back before filling in this page)

3232twf.doc / 005 A7 V. Description of the invention (Γ) 203: Gate oxide layer 204: Conductor gate 205: Gate cap layer 206: Source / drain region 207: Spacer wall 208: Dielectric layer 210: Etching Stop layers 212, 216, 216a, 222: Insulating layers 214, 220, 220a, 220b, 224, 224a, 224b, 228: Conductor layer 218 Contact window opening 225 Tree-like lower electrode 226 For a dielectric film layer embodiment, please refer to Section 2A FIG. 2 to FIG. 2H are cross-sectional views illustrating a manufacturing process of a capacitor of a dynamic random access memory according to a preferred embodiment of the present invention. Passed by the Ministry of Economic Affairs ^ Consumer Cooperative Association ^ 1 (Please read the precautions on the back before filling this page) Please refer to Figure 2A. First, on the surface of the provided substrate 200, a field isolation zone 202 is formed. In order to define the active area of the device, a field effect transistor 201 of a dynamic random access memory is further formed on the active area of the substrate 200. Next, a dielectric layer 208, an etch stop layer 210, an insulating layer 212, a conductor layer 214, and an insulating layer 216 are sequentially covered on the substrate 200. The material of the substrate 200 is, for example, a p-type silicon substrate; the method for forming the field isolation region 202 is, for example, a local area oxidation method (LOCOS) or a shallow trench isolation method (STI). A typical method for forming the field effect transistor 201 is to first form a thin oxide layer on the substrate 200 by using the thermal oxidation method 3232twf.doc / 005 A7 B7____ five 'invention', and then on the gate oxide layer according to A conductor layer and an insulating layer are sequentially formed, and then the three layers are patterned to form a gate oxide layer 203, a conductor gate 204, and a gate cap layer 205. Then, impurities are doped into the substrate 200 to form a source / drain region 206. Next, the substrate 200 is covered with an insulating layer and etched back to form a gap 207 on the sidewalls of the gate oxide layer 203, the conductor gate 204, and the gate cap layer 205. The material of the conductive gate 204 is, for example, doped polycrystalline silicon, and the method of forming the conductive gate 204 is, for example, chemical vapor deposition (CVD); the material of the gate cap layer 205 and the spacer 207 is, for example, silicon nitride. The method is, for example, a chemical vapor deposition method. The material of the dielectric layer 208 includes silicon oxide or borophosphosilicate glass (BPSG); the material of the etch stop layer 210 is, for example, silicon nitride; the material of the insulating layers 212 and 216 includes silicon oxide; the material of the conductor layer is, for example, doped compound Crystal silicon is formed by, for example, a chemical vapor deposition method. Next, referring to FIG. 2B, the insulating layer 216, the conductor layer 214, the insulating layer 212, the etch stop layer 210, and the dielectric layer 208 are patterned to form a contact window opening 218, and the source / drain region 206 is exposed. A typical method is to cover the insulating layer 216 with a patterned photoresist layer, and then use the photoresist layer as an etching mask to sequentially etch the insulating layer 216, the conductor layer 214, the insulating layer 212, and the etch stop layer. 210 and the dielectric layer 208. Finally, the photoresist layer is stripped to form a contact window opening 218, and the source / drain region 206 is exposed. Then, referring to FIG. 2C, a conductive layer 220 'is formed on the substrate 200 so as to cover the surface of the insulating layer 216, and is inserted into the contact window opening 218 to be electrically coupled to the source / drain region 206. Among them, the material of the conductor layer 220 8 paper size (CNS) A4 size (210 乂 297 mm) (Please read the precautions on the back before filling this page) Pack-

、 1T The Ministry of Economic Affairs and the Ministry of Economic Affairs of the People's Republic of China have a negative decision-T Consumer Cooperatives. Ink 32 32twf. Doc / 〇〇5 A7 B7 V. Description of the invention (7) The substance includes doped polycrystalline silicon, and the formation method is, for example, chemical vapor phase Deposition method. Thereafter, referring to FIG. 2D, the conductor layer 220 is defined to form a patterned mouth body layer 220a, a part of the surface of the insulation layer 216 is exposed, and then an insulation layer 222 is formed on the sidewall of the patterned conductor layer 220a. The material of the insulating layer 222 includes silicon nitride. The method for forming the insulating layer 222 is to first cover a silicon nitride layer on the substrate 200, and then remove a part of the silicon nitride layer by 'etching' to the side wall of the conductor layer 220a. Forming an insulating layer 222 of silicon nitride. Next, referring to FIG. 2E, using the insulating layer 222 as an etching mask, sequentially etching away a part of the insulating layer 216 and a part of the conductor 餍 214 to expose the part. Surface of the insulating layer 212. For example, a portion of the insulating layer 216 is removed by dry etching, and then a portion of the conductor layer 214 is removed by dry etching. Then, a conductive layer 224 conforming to the surface of the element is covered on the substrate 200. The material of the conductive layer 224 is, for example, doped polycrystalline silicon, and the formation method is, for example, chemical vapor deposition. When the material of the conductor layer 220a is the same as the material of the conductor layer 214, during the etching process of removing part of the conductor layer 214, part of the conductor layer 220a will also be etched, so that the thickness of the conductor layer 220a covered on the insulating layer 216 Becomes thinner. Then, referring to FIG. 2F, the insulating layer 222 and a part of the conductive layer 224 covered on the surface of the insulating layer 212 are removed to expose the surfaces of the insulating layer 222 and part of the insulating layer 212, leaving the conductive layers 224a and 224b. A typical method is to etch back the conductor layer 224 by wet etching. For example, a mixed solution of nitrous acid and hydrofluoric acid is used as an etchant, and a part of the conductor layer 214 formed of a polycrystalline silicon material is removed to expose the insulating layer. Table 222 and Partial Insulation 212 Table 9 Standards < CNS) aU See (210 X297) (Please read the precautions on the back before filling this page)-Installation ·

1T printed by the Ministry of Economic Affairs of the Ministry of Economic Affairs and the Consumers' Cooperatives of the Pregnancy Bureau of the Ministry of Justice of the People's Republic of China. The Ministry of iodine of the Ministry of Justice of the People's Republic of China J-Consumer Cooperatives printed the seals 3232twf.doc / 005 A7 ______B7_____ 5. Description of the invention (2). Thereafter, referring to FIG. 2G, the insulating layer 222, the insulating layer 216a, and the insulating layer 212 'are removed to expose the capacitor formed by the conductor layer 224a, the conductor layer 220b, the conductor layer 224b, and the conductor layer 214a (storage). ) The structure of the electrode 22S. A typical method is a wet etching method. For example, a heated phosphoric acid solution is used as an etchant to 'remove the insulating layer 222' formed of a nitrided sand material, and then 'the etching stop layer 21 is used as an etching end point. Hydrogen The hydrofluoric acid solution is an etchant, and the insulating layer 216a and the insulating layer 212 formed of the oxidized sand material are removed at the same time to expose the tree-like lower electrode structure 225. After that, referring to FIG. 2H, a dielectric film layer 226 is formed on the exposed surface of the tree-like lower electrode structure 225. Then, a conductive layer 228 is formed and defined on the substrate 200 to form an electrode on the capacitor. The material of the dielectric film layer 226 is, for example, a sand oxide layer, a silicon nitride layer / sand oxide layer (NO) structure, a silicon oxide layer / silicon nitride layer / silicon oxide layer (όνο) structure, or tantalum pentoxide (Ta205), Pb (Zr, Ti) 〇3, which is PTZ and (Ba, Sr) Ti03, which is a high dielectric constant material such as BST. The material of the conductor layer 228 is, for example, a method of forming doped polycrystalline silicon ', such as a chemical vapor deposition method, and impurities are deposited while depositing the polycrystalline cleaved layer, such as N-type arsenic ions, to improve its conductivity. Therefore, the feature of the present invention is that the formed storage electrode has a tree shape, which can greatly increase the effective surface area of the capacitor, thereby greatly improving the capacity of the capacitor of the dynamic random access memory to store charge. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can apply the Chinese National Standard (CNS) A4 specification (210X297) without departing from the spirit of the present invention. (Mm) -7-·-^-Γ Equipment -------- Order ------ M .-------------, ---- (Please Read the notes on the back before filling in this page) 3232twf .doc / 005 ρ ^ η _ B7 V. Description of the invention (7) and scope, various modifications and retouching can be made, so the scope of protection of the present invention should be considered after The attached application patent shall prevail. -TL—— · —— ^ —— t equipment—I (Please read the precautions on the back before filling this page)

、 1T line Printed by the Ministry of Economic Affairs and Intermediate Standards Bureau-T-Consumer Cooperatives This paper size applies to China National Standard (CNS) Α4 specification (210 × 297 mm)

Claims (1)

3232twf. Doc / OOf VI. Patent application meeting point AS ---- jB8 D8 Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shelley Consumer Cooperatives 1. A method of manufacturing a dynamic random access memory capacitor, the method includes the following Steps: providing a substrate and forming a field effect transistor on the substrate, the transistor including a source / drain region; sequentially forming a dielectric layer, a contact stop layer, and a first on the substrate An insulation layer, a first conductor layer, and a second insulation layer; patterning the second insulation layer, the first conductor layer, the first insulation layer, the etch stop layer, and the dielectric layer to form a contact Window opening, exposing the source / drain region; forming a second conductor layer on the substrate to cover the surface of the second insulating layer, and penetrating into the contact window opening, contacting the source / drain The electrode regions are electrically coupled; the second conductor layer is patterned; a third insulation layer is formed on the sidewall of the patterned second conductor layer; the third insulation layer is used as a cover, and a part of the second insulation layer is removed The marginal layer and the first conductor layer expose the first A portion of the surface of an insulating layer; forming a third conductor layer on the substrate; removing the third conductor layer covering the third insulating layer and covering a portion of the third conductor layer over the first insulating layer , Exposing the third insulating layer and a part of the surface of the first insulating layer; using the etch stop layer as an etching end point, removing the third insulating layer, the second insulating layer, and the first insulating layer, and exposing by A structure of a lower electrode composed of the first, the second, and the third conductor layer; forming a dielectric film layer on the exposed surface of the lower electrode; and 12 n · n I m 1 1 ^ 1 * 1 -m. (Please read the notes on the back before filling in this page) This paper size applies to Chinese National Standard (CNS) A4 size (210X297 cm) 3232twf.doc / 005 Β8 C8 D8 Printed by the Industrial and Consumer Cooperatives 6. A patent application park is formed on the substrate and defines a fourth conductor layer. 2. The method for manufacturing a dynamic random access memory capacitor as described in the first item, wherein the material of the dielectric layer includes silicon oxide. 3. The manufacturing method of dynamic random access memory described in item 1 of the patent scope, wherein the material of the dielectric layer includes borophosphosilicate glass. 4. The method for manufacturing a capacitor of a dynamic random access memory as described in item 1 of the patent, wherein the material of the first insulating layer includes oxidized sand. 5. The method for manufacturing a capacitor of a dynamic random access memory as described in item 4 of the patent, wherein the material of the etch stop layer includes nitrided sand. 6. The method for manufacturing a capacitor of a dynamic random access memory according to item 4 of the scope of patent application, wherein the material of the second insulating layer includes oxidized sand. 7_ The method for manufacturing a capacitor of a dynamic random access memory according to item 6 of the scope of patent application, wherein the material of the third insulating layer includes nitrided sand. 8. The method for manufacturing a capacitor of a dynamic random access memory according to item 1 of the scope of the patent application, wherein the third insulating layer is formed with a silicon nitride layer on the substrate 'and then formed by etching. 9. The method for manufacturing a capacitor of a dynamic random access memory according to item 1 of the scope of the patent application, wherein the material of the first, the second, the third, and the fourth conductor layers includes doped polycrystalline silicon . 13 This paper size applies to China National Standards (CNS) Α4 size (210X297). (Please read the note on the back before filling out this page.) Τ 3232twf.doc / 0〇 Staff Consumer Cooperatives, Central Rubbing Bureau, Ministry of Economic Affairs India «. A8 B8 C8 D8 VI. Patent application park 10. The system of the electric valley of dynamic random access memory described in item 9 of the scope of patent application; method ta, wherein the first, the second, The third and fourth conductive layers include a chemical vapor deposition method. 11. The method for manufacturing a capacitor of a dynamic random access memory according to item 1 of the scope of the patent application, wherein a part of the second insulating layer and the first conductor layer are removed to expose the portion of the first insulating layer. The portion surface is completed by a dry etching process. 12. The method for manufacturing a capacitor of a dynamic random access memory according to item 1 of the scope of patent application, wherein the third insulating layer, the second insulating layer and the first insulating layer are removed by a wet etching method. 13. The method for manufacturing a capacitor of a dynamic random access memory according to item 1 of the scope of patent application, wherein the material of the dielectric film layer includes a silicon nitride layer / silicon oxide layer structure, a silicon oxide layer / silicon nitride Layer / silicon oxide layer structure, one of tantalum pentoxide, PZT and BST. 14. A method for manufacturing a capacitor of a dynamic random access memory, the method comprising the following steps: providing a substrate, and forming a field effect transistor on the substrate, the transistor including a source / drain region; A dielectric layer, a first silicon nitride layer, a first silicon oxide layer, a first polycrystalline silicon layer, and a second silicon oxide layer are sequentially formed on the substrate; the second silicon oxide layer, the first silicon oxide layer, A polycrystalline silicon layer, the first sand oxide layer, the first silicon nitride layer, and the dielectric layer are patterned to form a contact window opening, exposing the source / drain region; this paper size is not used China National Fengfeng (CNS > A4 size (210X297 mm) (Please read the precautions on the back before filling out this page) "Packed., I II. Printed bags of the Consumers' Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs 3232twf.doc / 005 33 C8 D8 6. The scope of the application for a patent forms a second polycrystalline silicon layer on the substrate so that it covers the surface of the second silicon oxide layer and penetrates into the opening of the contact window and the source / drain region Electrically coupled; patterning the second polycrystalline silicon layer; in the figure A second nitrided sand layer is formed on the sidewall of the second compounded silicon layer; using the second silicon nitride layer as a mask, a part of the second silicon oxide layer and the first compound silicon layer are removed and exposed. Part of the surface of the first silicon oxide layer; forming a third polycrystalline silicon layer on the substrate; removing the third polycrystalline silicon layer covering the second silicon nitride layer and covering the first polycrystalline silicon layer Part of the third polycrystalline silicon layer on the insulating layer exposes the surface of the second silicon nitride layer and part of the first silicon oxide layer; using the second silicon oxide layer as an etching end point, removing the second silicon oxide layer A silicon nitride layer; using the first silicon nitride layer as an etching end point, removing the second silicon oxide layer and the first silicon oxide layer, and exposing the first, the second, and the third polycrystalline silicon layer A common structure of a lower electrode; forming a dielectric film layer on the exposed surface of the lower electrode; and forming and defining a fourth polycrystalline silicon layer on the substrate. The method for manufacturing a capacitor of the dynamic random access memory according to item 14, wherein the material of the dielectric layer includes Silicon oxide. 16. The method for manufacturing a capacitor of a dynamic random access memory as described in item 14 of the scope of patent application, wherein the material of the dielectric layer includes borophosphosilicate glass. Π. The dynamic random access memory described above (Please read the precautions on the back before filling this page) This paper standard uses the Chinese national standard (CNS > A4 specification (210 > < 297 mm) A8 3232twf.doc / 005 6. The method for manufacturing a capacitor with a patent scope, in which the first, the first 2. The method of the third and fourth polycrystalline silicon layers includes a chemical vapor deposition method. 18. The method for manufacturing a dynamic random access memory capacitor as described in item 14 of the scope of patent application, wherein the first The silicon dinitride layer is wet-etched. 19. The method for manufacturing a capacitor of a dynamic random access memory as described in item 14 of the patent application scope, wherein the second silicon oxide layer and the first oxide are removed. The silicon layer is wet-etched. JI-Γ ------.------ Order ------% '-*. (Please read the precautions on the back before filling in this page) Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Industrial and Consumer Cooperatives. * This paper size applies to China's National Standard (CNS) A4 specification (210X297 mm)