TW392338B - Method for manufacturing DRAM capacitors - Google Patents
Method for manufacturing DRAM capacitors Download PDFInfo
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- TW392338B TW392338B TW087111100A TW87111100A TW392338B TW 392338 B TW392338 B TW 392338B TW 087111100 A TW087111100 A TW 087111100A TW 87111100 A TW87111100 A TW 87111100A TW 392338 B TW392338 B TW 392338B
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- random access
- access memory
- dynamic random
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- 239000003990 capacitor Substances 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000004020 conductor Substances 0.000 claims description 49
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 27
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 230000005669 field effect Effects 0.000 claims description 12
- 230000002079 cooperative effect Effects 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims description 10
- 239000004576 sand Substances 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 2
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract description 11
- 125000006850 spacer group Chemical group 0.000 abstract description 3
- 238000003860 storage Methods 0.000 description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- IOVCWXUNBOPUCH-UHFFFAOYSA-N Nitrous acid Chemical compound ON=O IOVCWXUNBOPUCH-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000035935 pregnancy Effects 0.000 description 1
- 235000015170 shellfish Nutrition 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
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- Semiconductor Memories (AREA)
Abstract
Description
經淖部中决標準局貝工消贽合作社印«. 3232twf.doc/005 --—__B7^______ 五、發明説明(I ) — 本發明是有關於一種積體電路的製造方法,且特別是 有關於一種製造動態隨機存取記憶體(Dynamic Random Access, Memory ’ DRAM)之電容器的方法。 當電腦微處理器功能逐漸增強、軟體所進行的程式與運 算愈來愈龐大時,記憶體的電容需求也就愈來愈高。而隨 著動態隨機存取記憶體積集度的增加,目前所發展之記憶 胞係由一個轉移場效電晶體與一個儲存電容器所構成。第1 圖是動態隨機存取記憶體元件之記憶胞的電路示意圖。其 中’由半導體基底表面之電容陣列(Array of Capacitors) 中所篩選出的電容器C,可利用其充放電的特性儲存資料。 最常用的作法,是將二進位的單一位元資料儲存在所有的 電容器中,當未充電時其電容爲邏輯0,而充電後其電容則 爲邏輯1。通常,在電容器C的上電極(胞電極)1〇2與下 電極(儲存電極)100間塡入介電質101,以提供電極間所 需的介電常數,並且將電容器C耦合至一位元線(Bit Line) BL ’藉由電容器C的充放電而達到讀寫的目的。而電容器 C其充放電之間的切換工作是透過轉移場效電晶體 (Transfer Field Effect Transistor,TFET) T 以執行之。其 方法是將位元線BL與轉移場效電晶體T的汲極相連,電容 器C與轉移場效電晶體T的源極相接,而字元線(Word Line) WL的信號則餽入轉移場效電晶體T之閘極,以決定 電容器C是否與位元線BL相連接。 在傳統DRAM的儲存電容量少於1M ( Mega=百萬)位 元時,於積體電路製程中,主要是利用二度空間的電容器 3 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210X297公釐) (請先閱讀背面之注意事項存填寫本頁) -裝. ,ιτ d· 3232twf.doc/005 A7 B7 經洸部中央樣準局員J.消費合作社印製 五、發明説明(>) 來實現,亦即泛稱的平坦型電容器(Planar Type Capacitor)。由於平坦型電容器需佔用半導體基底相當大 的面積來儲存電荷,故並不適合應用於高度的積集化。高 度積集化的DRAM,例如大於4M位元的儲存電容量者’ 需要利用三度空間的電容器來實現,例如所謂的堆疊型 (Stacked Type)或溝槽型(Trench Type)電容器。 與平坦型電容器比較,堆疊型或溝槽型電容器可以在記 憶單元的尺寸進一步縮小的情況下,仍能獲得相當大的電 容量。雖然如此,當記憶體元件再進入更高度積集化時, 例如,具有64M位元容量的DRAM,單純的三度空間電容 器結構已不再適用。 解決的方法之一是將電容器的電極與介電膜層向水平 延伸,並且向上堆疊而形成所謂的鰭型(Fin Type)的堆疊 電容器,使電容器可藉由表面積的增加以增加儲存的電容 量。其相關技術可參考Ema等人的論文“3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs" international Electron Devices Meeting, pp592-595, Dec. 1988。或參考美國專利第5,071,783號、第 5,126,810 號以及第 5,206,787 號。 另一種解決之道則是使電容器的電極與介電膜層延伸 成一垂直狀結構而形成一所謂的柱型(Cylindrical Type) 堆疊電容器,使電容器可藉由表面積的增加以增加其所能 儲存的電容量。其相關技術可參考Wakamiya等人的論文 “Novel Stacked Capacitor Cell for 64Mb DRAM”,1989 4 本紙張尺度適用中國國家標卑(CNS ) A4規格(2丨0X297公釐) (請先閱讀背面之注意事項再填寫本頁) '裝.3232twf.doc / 005 ---__ B7 ^ ______ V. Description of the invention (I) — The present invention relates to a method for manufacturing integrated circuits, and in particular The invention relates to a method for manufacturing a capacitor of Dynamic Random Access Memory (Memory 'DRAM). As the functions of computer microprocessors are gradually enhanced and the programs and calculations performed by the software are becoming larger and larger, the capacitance requirements of memory are also increasing. With the increase of the dynamic random access memory volume concentration, the currently developed memory cell system consists of a transfer field effect transistor and a storage capacitor. FIG. 1 is a schematic circuit diagram of a memory cell of a dynamic random access memory element. Among them, capacitor C, which is selected from the array of capacitors on the surface of the semiconductor substrate, can use its charge and discharge characteristics to store data. The most common method is to store a single bit of binary data in all capacitors. When not charged, the capacitance is logic 0, and when charged, the capacitance is logic 1. Generally, a dielectric 101 is inserted between the upper electrode (cell electrode) 102 and the lower electrode (storage electrode) 100 of the capacitor C to provide the required dielectric constant between the electrodes, and the capacitor C is coupled to one bit. The bit line BL 'achieves the purpose of reading and writing by charging and discharging the capacitor C. The switching operation between the charge and discharge of the capacitor C is performed by a transfer field effect transistor (TFET) T. The method is to connect the bit line BL to the drain of the transfer field effect transistor T, the capacitor C is connected to the source of the transfer field effect transistor T, and the signal of the word line WL is fed into the transfer The gate of the field effect transistor T determines whether the capacitor C is connected to the bit line BL. When the storage capacity of traditional DRAM is less than 1M (Mega = million) bits, in the integrated circuit manufacturing process, the capacitor of the second space is mainly used. 3 The paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297). (Mm) (Please read the precautions on the back and fill in this page first)-Pack., Ιτ d · 3232twf.doc / 005 A7 B7 Printed by the Central Bureau of Procurement of the Ministry of Economic Affairs J. Consumer Cooperatives V. Invention Description (> ) To achieve, also known as the Planar Type Capacitor. Since a flat capacitor requires a relatively large area of a semiconductor substrate to store charges, it is not suitable for high accumulation. Highly integrated DRAMs, such as those with a storage capacity of more than 4M bits, need to be realized using a three-dimensional capacitor, such as a so-called stacked type or trench type capacitor. Compared with flat type capacitors, stacked or trench type capacitors can still obtain a considerable capacitance even when the size of the memory cell is further reduced. Nonetheless, when the memory elements are further integrated, for example, a DRAM with a capacity of 64M bits, the simple three-dimensional capacitor structure is no longer applicable. One of the solutions is to extend the capacitor's electrodes and dielectric film layers horizontally and stack them up to form a so-called Fin Type stacked capacitor, so that the capacitor can increase the stored capacitance by increasing the surface area. . For related technologies, please refer to the paper "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs" by Ema et al. &Quot; international Electron Devices Meeting, pp592-595, Dec. 1988. Or refer to US Patent Nos. 5,071,783, 5,126,810 No. and No. 5,206,787. Another solution is to extend the capacitor's electrodes and the dielectric film into a vertical structure to form a so-called cylindrical type capacitor, which can increase the surface area of the capacitor. The electric capacity that can be stored. For related technology, please refer to the paper "Novel Stacked Capacitor Cell for 64Mb DRAM" by Wakamiya et al., 1989 4 This paper size is applicable to China National Standard (CNS) A4 specification (2 丨 0X297 mm) (Please read the notes on the back before filling this page)
,1T 經鴻部中央標準局貝工消费合作社印製 3232twf.doc/005 A7 _B7 五 '發明説明(今), 1T Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Hong Kong 3232twf.doc / 005 A7 _B7 Five 'Explanation of Invention (Today)
Symposium on VLSI Technology Digest of Technical Papers, pp 69-70。或參考美國專利第5,077,688號。 隨=著積集度不斷地增加,DRAM記憶胞的尺寸仍會繼 續縮小。如熟悉此技藝者所知,記憶胞尺寸的縮小,儲存 電容値亦將減少。而電容値的減少又將造成α射線入射所引 起的軟錯誤(Soft Error)機會的增加。因此,此技藝者仍 不斷在找尋新的儲存電容器結構及其製造方法,藉以使得 在儲存電容所佔的平面縮小的情況下,仍能維持所需之電 容値》 緣此,本發明的主要目的就是在提供一種電容器的製造 方法,藉以使得在儲存電容所佔的平面縮小的情況下,仍 能維持所需之電容値,並能增加製程的容忍度 (Tolerance),以提昇產品之良率,減少製造的成本。 根據本發明的目的,提出一種動態隨機存取記憶體之電 容器的製造方法,此方法係在所提供的基底上形成場效電 晶體之後,依序於基底上形成並定義介電層、氮化矽蝕刻 終止層、第一絕緣層、第一導體層與一第二絕緣層,以形 成接觸窗開口,裸露出場效電晶體的源極/汲極區。然後, 在基底上形成第二導體層,使其覆蓋第二絕緣層之表面, 並且塡入接觸窗開口,與源極/汲極區電性耦接。接著,將 第二導體層圖案化,並在其側壁形成第二層氮化矽層,然 後,以第二層氮化矽層爲罩幕,去除部份第二絕緣層與第 一導體層,裸露出第一絕緣層的部份表面。其後,再於基 底上形成與元件表面共形的第三導體層,並將覆蓋於第二 5 本尺度適用中國國家^M CNS ) Λ4規格(210X297公漦) " 1.1_--1---:--Γ 裝-- (請先閱讀背面之注意事項再填寫本頁) 訂 經肩部中夾櫺卑扃負J-消費合竹社印紫 3232twf.doc/005 A7 __B7_ 五、發明説明(+ ) 氮化矽層之第三導體層與部份覆蓋於第一絕緣層上之第三 導體層去除,以裸露出第二氮化矽層與部份第一絕緣層之 表面。然後,依序去除第二氮化矽層、第二絕緣層與第一 絕緣層,裸露出由第一、第二與第三導體層所共同組成之 下電極的架構,接著,在下電極所裸露出的表面上依序形 成並定義介電膜層與第四導體層,以完成電容器之製作。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂, 下文特舉一較佳實施例,並配合所附圖式,作詳細說明如 下: 圖式之簡單說明: 第1圖是動態隨機存取記憶體元件之記憶胞的電路示 意圖;以及 第2A圖至第2H圖,其繪示依照本發明一較佳實施例 的一種動態隨機存取記憶體的製造流程剖面圖。 圖式標記說明: C :電容器 T,201 :場效電晶體 BL :位元線 WL :字元線 100 :下電極 101, 226 :介電膜層 102 :上電極 200 :基底 202 :場氧化層 6 本紙張尺度適州中國國家標準(CNS ) Λ4規格(2丨0X297公H ~ (請先閲讀背面之注意事項再填寫本頁)Symposium on VLSI Technology Digest of Technical Papers, pp 69-70. Or refer to US Patent No. 5,077,688. As the degree of accumulation continues to increase, the size of the DRAM memory cell will continue to shrink. As those skilled in the art know, the shrinking memory cell size will also reduce the storage capacitance. The decrease of the capacitance chirp will increase the chance of soft errors caused by the incidence of alpha rays. Therefore, this artist is still looking for a new storage capacitor structure and manufacturing method, so that the required capacitance can be maintained even when the plane occupied by the storage capacitor is reduced. Therefore, the main purpose of the present invention It is to provide a method for manufacturing a capacitor, so that the required capacitance can be maintained while the plane occupied by the storage capacitor is reduced, and the tolerance of the process can be increased to improve the yield of the product. Reduce manufacturing costs. According to the purpose of the present invention, a method for manufacturing a capacitor of a dynamic random access memory is proposed. After forming a field-effect transistor on a provided substrate, a dielectric layer and a nitride are sequentially formed and defined on the substrate. The silicon etching stop layer, the first insulating layer, the first conductor layer and a second insulating layer form a contact window opening, exposing the source / drain regions of the field effect transistor. Then, a second conductor layer is formed on the substrate so as to cover the surface of the second insulating layer, and is inserted into the contact window opening to be electrically coupled to the source / drain region. Next, the second conductor layer is patterned, and a second silicon nitride layer is formed on the sidewall. Then, the second silicon nitride layer is used as a mask to remove a portion of the second insulating layer and the first conductor layer. A part of the surface of the first insulating layer is exposed. After that, a third conductor layer conforming to the surface of the element is formed on the substrate, and it will cover the second 5 This standard applies to the Chinese national standard ^ M CNS) 4 specifications (210X297 cm) " 1.1 _-- 1- -: --Γ outfit-(Please read the precautions on the back before filling this page) Stitching in the Shoulder J-Consumer Hezhu Society Printing Purple 3232twf.doc / 005 A7 __B7_ V. Invention Explanation (+) The third conductor layer of the silicon nitride layer and the third conductor layer partially covering the first insulating layer are removed to expose the surfaces of the second silicon nitride layer and part of the first insulating layer. Then, the second silicon nitride layer, the second insulating layer, and the first insulating layer are sequentially removed, and the structure of the lower electrode composed of the first, second, and third conductor layers is exposed. Then, the lower electrode is exposed. A dielectric film layer and a fourth conductor layer are sequentially formed and defined on the surface to complete the fabrication of the capacitor. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: Figure 1 is dynamic A schematic circuit diagram of a memory cell of a random access memory element; and FIGS. 2A to 2H are cross-sectional views illustrating a manufacturing process of a dynamic random access memory according to a preferred embodiment of the present invention. Description of graphical symbols: C: capacitor T, 201: field effect transistor BL: bit line WL: word line 100: lower electrode 101, 226: dielectric film layer 102: upper electrode 200: substrate 202: field oxide layer 6 This paper is compliant with China National Standard (CNS) Λ4 specification (2 丨 0X297 male H ~ (Please read the precautions on the back before filling in this page)
3232twf.doc/005 A7 五、發明説明(Γ) 203 :閘極氧化層 204 :導體閘極 205 :閘極頂蓋層 206 :源極/汲極區 207 :間隙壁 208 :介電層 210 :蝕刻終止層 212, 216,216a,222 :絕緣層 214, 220, 220a, 220b,224, 224a,224b,228 :導體層 218 接觸窗開口 225 樹狀下電極 226 介電膜層 實施例 請參照第2A圖至第2H圖,其繪示依照本發明一較佳 實施例的一種動態隨機存取記憶體之電容器的製造流程剖 面圖。 經满部屮次標卑局貝^消費合作社印^1 (請先閲讀背面之注意事項再填寫本頁) 請參照第2A圖,首先,在所提供的基底200表面上, 形成場隔離區202以定義元件之主動區,續再於基底200 的主動區上形成動態隨機存取記憶體的場效電晶體201。接 著,於基底200上依序覆蓋一層介電層208、蝕刻終止層 210、絕緣層212、導體層214與絕緣層216。 其中,基底200的材質例如爲p型矽基底;場隔離區 202的形成方法例如爲局部區域氧化法(LOCOS)或淺溝 渠隔離法(STI)。典型形成場效電晶體201的方法係先以 3232twf.doc/005 A7 B7____ 五'發明説明(& ) 熱氧化法於基底200上形成一層薄氧化層’然後,再於閘 極氧化層上依序形一層導體層與一層絕緣層’接著’將此 三層圖案化,以形成閘極氧化層203、導體閘極204與閘極 頂蓋層205。然後,再於基底200中摻入雜質,以形成源極 /汲極區206。接著,在基底200上覆蓋一層絕緣層並進行 回蝕刻,以在閘極氧化層203、導體閘極204與閘極頂蓋層 205之側壁形成間隙壁207。其中,導體閘極204之材質例 如爲摻雜的複晶矽,形成的方法例如爲化學氣相沈積法 (CVD);閘極頂蓋層205與間隙壁207之材質例如爲氮 化矽,形成的方法例如爲化學氣相沈積法。介電層208之 材質包括氧化矽或硼磷矽玻璃(BPSG);蝕刻終止層210 之材質例如爲氮化矽;絕緣層212與216之材質包括氧化 矽;導體層之材質例如爲摻雜複晶矽,形成的方法例如爲 化學氣相沈積法。 接著,請參照第2B圖,將絕緣層216、導體層214、 絕緣層212、蝕刻終止層210與介電層208圖案化,以形成 接觸窗開口 218,裸露出源極/汲極區206。典型的方法,係 在絕緣層216上先覆蓋一層圖案化的光阻層,然後再以此 光阻層爲蝕刻罩幕,依序蝕刻絕緣層216、導體層214、絕 緣層212、蝕刻終止層210與介電層2〇8,最後,再將光阻 層剝除’以形成接觸窗開口 218,裸露出源極/汲極區206。 然後,請參照第2C圖,在基底200上形成一層導體層 220’使其覆蓋絕緣層216的表面,並且塡入接觸窗開口 218 中,與源極/汲極區206電性耦接。其中,導體層220之材 8 本紙張尺绛(CNS ) A4規格(210乂297公釐] (請先閲讀背面之注意事項再填寫本頁) 裝-3232twf.doc / 005 A7 V. Description of the invention (Γ) 203: Gate oxide layer 204: Conductor gate 205: Gate cap layer 206: Source / drain region 207: Spacer wall 208: Dielectric layer 210: Etching Stop layers 212, 216, 216a, 222: Insulating layers 214, 220, 220a, 220b, 224, 224a, 224b, 228: Conductor layer 218 Contact window opening 225 Tree-like lower electrode 226 For a dielectric film layer embodiment, please refer to Section 2A FIG. 2 to FIG. 2H are cross-sectional views illustrating a manufacturing process of a capacitor of a dynamic random access memory according to a preferred embodiment of the present invention. Passed by the Ministry of Economic Affairs ^ Consumer Cooperative Association ^ 1 (Please read the precautions on the back before filling this page) Please refer to Figure 2A. First, on the surface of the provided substrate 200, a field isolation zone 202 is formed. In order to define the active area of the device, a field effect transistor 201 of a dynamic random access memory is further formed on the active area of the substrate 200. Next, a dielectric layer 208, an etch stop layer 210, an insulating layer 212, a conductor layer 214, and an insulating layer 216 are sequentially covered on the substrate 200. The material of the substrate 200 is, for example, a p-type silicon substrate; the method for forming the field isolation region 202 is, for example, a local area oxidation method (LOCOS) or a shallow trench isolation method (STI). A typical method for forming the field effect transistor 201 is to first form a thin oxide layer on the substrate 200 by using the thermal oxidation method 3232twf.doc / 005 A7 B7____ five 'invention', and then on the gate oxide layer according to A conductor layer and an insulating layer are sequentially formed, and then the three layers are patterned to form a gate oxide layer 203, a conductor gate 204, and a gate cap layer 205. Then, impurities are doped into the substrate 200 to form a source / drain region 206. Next, the substrate 200 is covered with an insulating layer and etched back to form a gap 207 on the sidewalls of the gate oxide layer 203, the conductor gate 204, and the gate cap layer 205. The material of the conductive gate 204 is, for example, doped polycrystalline silicon, and the method of forming the conductive gate 204 is, for example, chemical vapor deposition (CVD); the material of the gate cap layer 205 and the spacer 207 is, for example, silicon nitride. The method is, for example, a chemical vapor deposition method. The material of the dielectric layer 208 includes silicon oxide or borophosphosilicate glass (BPSG); the material of the etch stop layer 210 is, for example, silicon nitride; the material of the insulating layers 212 and 216 includes silicon oxide; the material of the conductor layer is, for example, doped compound Crystal silicon is formed by, for example, a chemical vapor deposition method. Next, referring to FIG. 2B, the insulating layer 216, the conductor layer 214, the insulating layer 212, the etch stop layer 210, and the dielectric layer 208 are patterned to form a contact window opening 218, and the source / drain region 206 is exposed. A typical method is to cover the insulating layer 216 with a patterned photoresist layer, and then use the photoresist layer as an etching mask to sequentially etch the insulating layer 216, the conductor layer 214, the insulating layer 212, and the etch stop layer. 210 and the dielectric layer 208. Finally, the photoresist layer is stripped to form a contact window opening 218, and the source / drain region 206 is exposed. Then, referring to FIG. 2C, a conductive layer 220 'is formed on the substrate 200 so as to cover the surface of the insulating layer 216, and is inserted into the contact window opening 218 to be electrically coupled to the source / drain region 206. Among them, the material of the conductor layer 220 8 paper size (CNS) A4 size (210 乂 297 mm) (Please read the precautions on the back before filling this page) Pack-
、1T 經消部中决枒率局負-T消费合作社印繁 32 32twf. doc/〇 〇 5 A7 B7 五、發明説明(7 ) 質包括摻雜複晶矽,形成的方法例如爲化學氣相沈積法。 其後,請參照第2D圖,定義導體層220,以形成圖案 化之嘴體層220a,裸露出部份的絕緣層216表面,然後再 於圖案化之導體層220a之側壁形成絕緣層222。其中,絕 緣層222之材質包括氮化矽,形成的方法係在基底200上 先覆蓋一層氮化矽層,然後’再經由蝕刻’去除部份的氮 化矽層,以在導體層220a之側壁形成氮化矽材質之絕緣層 222 ° 接著,請參照第2E圖,以絕緣層222爲蝕刻罩幕,依 序蝕刻去除部份的絕緣層216與部份的導體餍214,以裸露 出部份的絕緣層212表面。例如,以乾式蝕刻法,先去除 部份的絕緣層216,接著,再以乾式蝕刻法去除部份的導體 層214。然後,再於基底200上覆蓋一層與元件表面共形的 導體層224,其材質例如爲摻雜複晶矽,形成的方法例如爲 化學氣相沈積法。當導體層220a之材質與導體層214之材 質相同時,在去除部份導體層214的蝕刻過程中,部份的 導體層220a亦會遭受蝕刻,而使其在絕緣層216上所覆蓋 的厚度變得較薄。 然後,請參照第2F圖,去除絕緣層222以及部份絕緣 層212表面上所覆蓋的導體層224,以裸露出絕緣層222 與部份絕緣層212之表面,留下導體層224a與224b。典型 的方法係以濕式蝕刻法回蝕導體層224 ’例如以亞硝酸與氫 氟酸的混合溶液爲蝕刻劑,去除部份由複晶矽材質所形成 之導體層214,以裸露出絕緣層222與部份絕緣層212之表 9 家摞準 < CNS ) aU見輅(210 X297公 (請先閲讀背面之注意事項再填寫本頁) -裝·、 1T The Ministry of Economic Affairs and the Ministry of Economic Affairs of the People's Republic of China have a negative decision-T Consumer Cooperatives. Ink 32 32twf. Doc / 〇〇5 A7 B7 V. Description of the invention (7) The substance includes doped polycrystalline silicon, and the formation method is, for example, chemical vapor phase Deposition method. Thereafter, referring to FIG. 2D, the conductor layer 220 is defined to form a patterned mouth body layer 220a, a part of the surface of the insulation layer 216 is exposed, and then an insulation layer 222 is formed on the sidewall of the patterned conductor layer 220a. The material of the insulating layer 222 includes silicon nitride. The method for forming the insulating layer 222 is to first cover a silicon nitride layer on the substrate 200, and then remove a part of the silicon nitride layer by 'etching' to the side wall of the conductor layer 220a. Forming an insulating layer 222 of silicon nitride. Next, referring to FIG. 2E, using the insulating layer 222 as an etching mask, sequentially etching away a part of the insulating layer 216 and a part of the conductor 餍 214 to expose the part. Surface of the insulating layer 212. For example, a portion of the insulating layer 216 is removed by dry etching, and then a portion of the conductor layer 214 is removed by dry etching. Then, a conductive layer 224 conforming to the surface of the element is covered on the substrate 200. The material of the conductive layer 224 is, for example, doped polycrystalline silicon, and the formation method is, for example, chemical vapor deposition. When the material of the conductor layer 220a is the same as the material of the conductor layer 214, during the etching process of removing part of the conductor layer 214, part of the conductor layer 220a will also be etched, so that the thickness of the conductor layer 220a covered on the insulating layer 216 Becomes thinner. Then, referring to FIG. 2F, the insulating layer 222 and a part of the conductive layer 224 covered on the surface of the insulating layer 212 are removed to expose the surfaces of the insulating layer 222 and part of the insulating layer 212, leaving the conductive layers 224a and 224b. A typical method is to etch back the conductor layer 224 by wet etching. For example, a mixed solution of nitrous acid and hydrofluoric acid is used as an etchant, and a part of the conductor layer 214 formed of a polycrystalline silicon material is removed to expose the insulating layer. Table 222 and Partial Insulation 212 Table 9 Standards < CNS) aU See (210 X297) (Please read the precautions on the back before filling this page)-Installation ·
、1T 經漓部中决樣孕局員工消费合作社印挈 經碘部中决榡準局貝J-消费合作社印掣 3232twf.doc/005 A7 ______B7_____ 五、發明説明(2 ) ' 面。 其後,請參照第2G圖,去除絕緣層222、絕緣層216a 與絕緣層212 ’以裸露出由導體層224a、導體層220b、導 體層224b以及導體層214a所共同成之電容器其下(儲存) 電極之架構22S。典型的方法,係以濕式蝕刻法,例如,先 以加熱的磷酸溶液爲蝕刻劑’去除由氮化砂材質所形成之 絕緣層222 ’然後’再以蝕刻終止層21〇爲蝕刻終點,氫氟 酸溶液爲蝕刻劑’同時去除由氧化砂材質所形成之絕緣層 216a與絕緣層212,以裸露出樹狀下電極之架構225。 之後,請參照第2H圖,在樹狀下電極架構225所裸露 的表面上形成一層介電膜層226。然後,再於基底2〇〇上形 成、並定義一層導體層228,以形成電容器之上電極。介電 膜層226之材質例如爲氧化砂層、氮化矽層/氧化砂層 (NO)結構、氧化矽層/氮化矽層/氧化矽層(όνο)結構 或五氧化二钽(Ta205)、Pb ( Zr, Ti) 〇3,即 ΡΖΤ 以及(Ba, Sr) Ti03,即BST等高介電常數的材料。導體層228之材 質例如爲摻雜複晶矽’形成的方法例如爲化學氣相沈積 法,在沈積複晶砍層的同時摻入雜質,例如,N型的砷離 子,以提高其導電性。 因此,本發明之特徵是所形成之儲存電極呈樹狀,可以 使電容器之有效表面積大大地增加,以大幅提昇動態隨機 存取記憶體之電容器其儲存電荷的能力。 雖然本發明已以一較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 本紙張尺度適用中國國家標绛(CNS ) A4規格(210X297公釐) -7 --·--^--Γ 裝------訂------M.-------------,---- (請先閲讀背面之注意事項再填寫本頁) 3232twf . doc/005 ρ^η _ B7 五、發明説明(7 ) 和範圍內,當可作各種之更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 -TL——·——^——t裝—I (請先閲讀背面之注意事項再填寫本頁)1T printed by the Ministry of Economic Affairs of the Ministry of Economic Affairs and the Consumers' Cooperatives of the Pregnancy Bureau of the Ministry of Justice of the People's Republic of China. The Ministry of iodine of the Ministry of Justice of the People's Republic of China J-Consumer Cooperatives printed the seals 3232twf.doc / 005 A7 ______B7_____ 5. Description of the invention (2). Thereafter, referring to FIG. 2G, the insulating layer 222, the insulating layer 216a, and the insulating layer 212 'are removed to expose the capacitor formed by the conductor layer 224a, the conductor layer 220b, the conductor layer 224b, and the conductor layer 214a (storage). ) The structure of the electrode 22S. A typical method is a wet etching method. For example, a heated phosphoric acid solution is used as an etchant to 'remove the insulating layer 222' formed of a nitrided sand material, and then 'the etching stop layer 21 is used as an etching end point. Hydrogen The hydrofluoric acid solution is an etchant, and the insulating layer 216a and the insulating layer 212 formed of the oxidized sand material are removed at the same time to expose the tree-like lower electrode structure 225. After that, referring to FIG. 2H, a dielectric film layer 226 is formed on the exposed surface of the tree-like lower electrode structure 225. Then, a conductive layer 228 is formed and defined on the substrate 200 to form an electrode on the capacitor. The material of the dielectric film layer 226 is, for example, a sand oxide layer, a silicon nitride layer / sand oxide layer (NO) structure, a silicon oxide layer / silicon nitride layer / silicon oxide layer (όνο) structure, or tantalum pentoxide (Ta205), Pb (Zr, Ti) 〇3, which is PTZ and (Ba, Sr) Ti03, which is a high dielectric constant material such as BST. The material of the conductor layer 228 is, for example, a method of forming doped polycrystalline silicon ', such as a chemical vapor deposition method, and impurities are deposited while depositing the polycrystalline cleaved layer, such as N-type arsenic ions, to improve its conductivity. Therefore, the feature of the present invention is that the formed storage electrode has a tree shape, which can greatly increase the effective surface area of the capacitor, thereby greatly improving the capacity of the capacitor of the dynamic random access memory to store charge. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can apply the Chinese National Standard (CNS) A4 specification (210X297) without departing from the spirit of the present invention. (Mm) -7-·-^-Γ Equipment -------- Order ------ M .-------------, ---- (Please Read the notes on the back before filling in this page) 3232twf .doc / 005 ρ ^ η _ B7 V. Description of the invention (7) and scope, various modifications and retouching can be made, so the scope of protection of the present invention should be considered after The attached application patent shall prevail. -TL—— · —— ^ —— t equipment—I (Please read the precautions on the back before filling this page)
、1T 線 經滅部中决標準局貝-Τ-消費合作社印裝 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐)、 1T line Printed by the Ministry of Economic Affairs and Intermediate Standards Bureau-T-Consumer Cooperatives This paper size applies to China National Standard (CNS) Α4 specification (210 × 297 mm)
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