TW554479B - Manufacturing method of crown-shape capacitor - Google Patents

Abstract

The present invention provides a manufacturing method of crown-shape capacitor, and is suitable for use as a manufacturing method of crown-shape capacitor. The invention includes the followings: providing a semiconductor substrate that is coated with an insulation layer; etching the insulation layer to form an opening; forming a conformal first electrode layer attached to the insulation layer and in the opening region; forming a sacrificial layer; stripping the sacrificial layer part outside the opening region; removing the first electrode layer on the insulation layer and the upper part of the opening region so as to form a recess on the first electrode layer of the opening; removing the sacrificial layer; forming a capacitive dielectric layer on the first electrode layer; and forming the a second electrode layer on the capacitive dielectric layer to finally form the crown-shape capacitor.

Description

554479

The present invention relates to a method for manufacturing a crown capacitor, and more particularly, to a method for manufacturing a crown-metal-insulator-metal (MiM) capacitor. In Dynamic Random Access Memory (DRAM), a capacitor is the heart part of a cell to access a signal. The more charge it stores, the less it is affected by noise when reading data. The methods used to increase the capacitor's ability to store charges are: ()) increasing the dielectric constant of the capacitor dielectric layer to increase the number of charges stored per unit area of the capacitor; (2) increasing the area of the capacitor so that the entire storage is stored in the capacitor The amount of charge increases. Therefore, in the manufacture of advanced DRAMs, small-sized, crown- or trench-shaped structures with 3D forms, and capacitors using high-k dielectric materials have been widely used. Applied. Among the constituent capacitor materials, most are polycrystalline silicon capacitors formed by the structure of polycrystalline silicon-insulator-multicrystalline silicon; or the structure of polycrystalline silicon-insulator-metalized polycrystalline spar (or metal) is called a so-called M i $ capacitor; and a metal-insulator-metal structure is formed with a metal-insulator-metal structure. In order to understand the background of the present invention, the manufacturing method of the conventional coronal M i M capacitor will be further described below. Fig. 1a shows a partial cross-sectional structure diagram of a crown M i M capacitor in the conventional DR AM technology. Please refer to Fig. 1a. A semiconductor substrate 1 10 is formed with a number of memory elements such as A and Mg. The detailed structure of the memory element is formed by a field effect transistor (FET). Zen is not in the picture 'to simplify the description of the picture and the subsequent ones;

0503-7970TWf (N); TSMC2002-0047; Shawn.ptd Page 4 554479 5. Description of the invention (3) = contact plug (plug) U2 is formed in the above-mentioned insulating layer ^ 1 for summing up, $ 忆 $ The element A and the electrode form an electrical contact, and serve as a node contact for the DRAM storage valley. An etching stop layer 11 3 is formed on the above-mentioned insulating layer 11 1 and the contact plug 112, and a second insulating layer 114 is formed on the above-mentioned etching stop layer 丨 3. "It is stated that an opening area 0P (used to define a storage valley device) is formed in the second insulating layer 114 to route out the above-mentioned contact plug 1 1 2. A compliance (c ο nf 〇rma 1) first (metal ) An electrode layer 115 is formed in the above-mentioned opening region oop and on the second insulating layer 114, and a first electrode layer on the second insulating layer 114 outside the opening region is removed by an etch back process and further The first electrode layer 115 at the upper end of the sidewall of the above-mentioned open area OP is etched back to an appropriate depth; a capacitor dielectric layer 116 is formed on the first electrode layer 115 and an etch back process is performed to remove the second insulation. The capacitor dielectric layer 116 on the surface portion of the layer 114 is followed by a second (metal) electrode layer 117 formed on the capacitor dielectric layer 116 and the second insulating layer 114 and the second insulating layer 11 is removed through a planarization process 4 The second electrode layer on the surface part 丨 7. In this way, the first electrode layer 115 (lower electrode layer), the valley dielectric layer 116 (dielectric material layer) and The second electrode layer 117 (upper electrode layer) constitutes a crown-shaped storage of electricity of the DRAM cell. The crown-shaped MiM capacitor structure shown in Figure 1a is due to its large size and the need for an additional photomask to define the crown-shaped capacitor structure, which in turn affects DRAM memory cells (ceU). And increase the complexity of the DRAM manufacturing process. The crown-shaped MiM capacitor structure shown in FIG.

554479 V. Description of the invention (4): The manufacturing process reduces a photomask and is easier to combine with the rear section (for example, copper wire); however, the system made here: the first electrode belonging to the surface portion of the wire u2 insulation layer is more = = ml · ^ ^ ^ &. — < $ A step in the etched opening area 0P on the upper side of the side wall of a PW private 私 1. In the process of the first electrode layer 115, it is more difficult to make the wide electrode layer 丨 5 in the opening area. It is difficult to etch back the uniformity, so the county and the county think it is a depression. The depth of the money and the depth of the first electrode layer are formed due to the failure described above. The unsuitable degree or shape of the capacitor further leads to the function of the capacitor. In order to solve the above problem, the main purpose of the present invention is to clean the electrode and to make the depth of the lower electrode etched down effectively. Reliability of the dram crown storage capacitor after the subsequent struc- ture formation. In order to achieve the above-mentioned object, the present invention proposes a method for manufacturing a crown capacitor, which includes the following steps: providing a semiconductor substrate covered with an insulating layer; etching the insulating layer to form an opening region; forming a compliance ( c ο nf 〇rma 1) the first electrode layer is pasted on the insulating layer and in the opening area oop; then a sacrificial layer is formed; the sacrificial layer outside the opening area 〇P is removed; the insulation layer is removed A first electrode layer above and above the opening portion of the opening region to form a first electrode layer recessed in the opening; removing the sacrificial layer; forming a capacitor dielectric layer on the first electrode layer; and forming a A second electrode layer is formed on the capacitor dielectric layer to form the crown capacitor. Embodiment 1: Figures 2a to 2g show the flow of the first embodiment of the method of the present invention.

0503-7970TWf (N); TSMC2002-0047; Shawn.ptd Page 7 554479 V. Description of the invention (5) ------ Sectional view. First referring to FIG. 2a, a number of physical components (eg, Z1, M1,) are formed on a semiconductor substrate 21, and the detailed structure of the memory element is composed of a Field Effect Transistor (FET). The 'formation formed' is not shown in the drawing in detail to simplify the illustration and the subsequent description; a first insulating layer 211 (for example, silicon dioxide) is then covered on the memory element (for example, M /, M2 '). . A contact plug 212 (for example, tungsten) is formed in the above-mentioned insulating layer 21 to form an electrical contact with the above-mentioned memory element (&, 屺), and serves as a node of the DRAM storage capacitor. Contact 1 (node contact). On the above-mentioned insulating layer 211 and the contact plug 212, a stop layer 2 1 3 (for example, nitride nitride) is formed, and a second insulating layer 2 1 4 (for example, silicon dioxide) is formed on the etching. Above the stop layer 2 丨 3, please refer to FIG. 2b. An opening area 0P is formed in the second insulating layer 2 丨 4 to expose the contact plug 212. Referring to FIG. 2c, a conformal first (metal such as titanium nitride, nitride group, or nitride nitride) electrode layer 215 is deposited using the cVD method to obtain a second insulating layer within the opening region oop. The opening area OP is still filled with the material of the sacrificial layer 21 6. Please refer to Figure 2f, and then use plasma etching gas with gas ((: ") as the main gas,

0503-7970TlVf (N); TSMC2002-0047; Shawn.ptd 1 14. Please refer to FIG. 2d, and then apply a spin coating method to a sacrificial layer material 2 丨 6 such as a photoresist material (PR) or an anti-reflective layer material (BARC ·) to cover the first electrode layer. 215 is filled with the above-mentioned opening area OP. Please refer to FIG. 2e, and then use a planarization technique (such as chemical mechanical polishing method-CMP) to remove the sacrificial layer 216 material outside the opening region 0P, so that 554479 V. Description of the invention (6) rate u〇w bias p〇wer) conditions The first electrode layer 21 5 ′ is described below (between 15 and 5 ° w) with two pins and two j jst, and the above-mentioned etching gas m a gate λ 5 and a second insulating layer 216 material (here, for example, IΓΓ ": 1) 5 The first electrode layer 215 on the top is etched back, and the first layer 216 material (here, for example, 1) has a good selection ratio of about 10 (about 04: 0, and further recesses the opening area 0ρ). The first electrode layer US at the upper end forms a first electrode layer 215 recessed in the opening area ο. According to FIG. 2g, #the remaining sacrifice of the opening area 2 is removed by wet etching or a solvent. Layer 21 6 material, followed by a CVD method to deposit a capacitor layer 217 material (such as oxide button 1 ^ 205, gillium titanate 63 > 1 or hafnium dioxide Hf02), and then deposited by CVD method-second (metal (Such as nitride, tantalum nitride or tungsten nitride) electrode layer 218 material and use a planarization process (such as cMp method) The capacitor dielectric layer 217 and the second electrode layer 218 on the surface of the second insulating layer 215 are removed, and finally the crown capacitor is formed in the opening area OP. The second embodiment is structured: Figures 3a to 3g show the method of the present invention. Sectional view of the second embodiment. 1 'First, referring to FIG. 3a, a detailed structure of the memory element is formed on a semiconductor substrate 31, such as a memory element (e.g.,', M2 '). Formed by a Field Effect Transistor (FET), but not shown in detail in the figure to simplify the illustration and the following description; a first insulating layer 3 1 1 (for example, silicon dioxide) ) Covering the above memory elements (such as M / ,, M2 ,,). A contact plug 312 (example: tungsten)

554479 V. Description of the invention (7) It is formed in the above-mentioned insulating layer 3 1 1 to form electrical contact with the above-mentioned memory element (Mm ,, M / '), and serves as the node contact (node) of the DRAM storage capacitor. contact). An etching stop layer 3 1 3 (for example, silicon nitride) is formed on the first insulating layer 311 and the contact plug 312, and a second insulating layer 3 1 4 (for example, silicon dioxide) is formed on the above. Above the etch stop layer 3 1 3.

Referring to FIG. 3b, an opening region 0 P ′ is formed in the second insulating layer 3 1 4 to route the contact plug 3 1 2. Referring to FIG. 3c, a conformal first (metal such as titanium nitride, nitride button, or tungsten nitride) electrode layer 3 1 5 is deposited using the c VD method in the above-mentioned opening area oop, above The sidewall of the opening region oop is on the second insulating layer 3 1 4. Please refer to Figure 3d, and then use chemical vapor deposition (CVD) to deposit a conformable (conf orma 丨) sacrificial layer 316 (polymer) formed by c4F8 and C0 as reactive gases and according to an appropriate flow ratio. (Polymer) is formed on the second insulating layer 314 and inside the above-mentioned opening region, and a overhang structure (overhang) is formed above the opening region oop to protect the planar portion of the above-mentioned opening region OP from later flattening. The procedure (such as etch back) is free from injury, in which the gas flow rate is between 6 ~ 8 sccm, and the CO gas flow rate is between 360 ~ 480 sccm. Please refer to Figure 3e,

The planarization technique (for example, chemical mechanical polishing (CMP) or etch back) is used to remove the sacrificial layer 3 丨 6 outside the opening area 0p, so that a part of the sacrificial layer 3 1 6 still exists in the opening area 0p. Inside. Next, please refer to Figure 3f, and then use a plasma etching gas with chlorine (C 12) as the main gas, and etch back under low bias power (between 15 ~ 50W). back) the first electrode layer 315, and using the etching gas

0503-7970 Seoul (N); TSMC2002-0047; Shawn.ptd Page 10 554479

Case No. 91112702 V. Description of the invention (8) In the first electrode layer 315: the second insulating layer 314 has a good selection ratio (approximately 10: 1), and the second insulating layer is made of stone. Use the first electrode layer 315: sacrificial layer 3 cores: (here, Polymer) a good selection ratio (about 3: ㈠, ς — only the first electrode layer 315 in the upper end of the opening area OP to reduce, to The first electrode layer 315 recessed in the opening area 0P. Please refer to the first center and then use plasma etching to remove the remaining sacrificial ° reed in the opening area op, 316 material, and then deposit the capacitor dielectric layer M by CVD method. (For example, ^ TaA, Barium Titanate BST, or Dioxide, please refer to: Oxygen :: Second, and then, CVD method to deposit the second electrode layer 318 (for example, nitride, nitride button or tungsten nitride) The planarization process (for example, the cMp method) is used to remove the capacitor dielectric layer 317 and the second electrodes ′, 31 8 on the surface of the second insulating layer 315, and finally form the crown-shaped capacitor structure in the opening area oop. Although the above is disclosed in the preferred embodiment, it is not intended to limit the scope of the present invention. Those skilled in the art can do some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

554479 Brief description of the drawings In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments and the accompanying drawings in detail, as follows: Figures 1a and 1b Schematic diagram showing a partial cross-sectional structure of a conventional crown-shaped MiM capacitor in a DRAM structure; Figures 2a to 2g are cross-sectional views showing the flow of the first embodiment of the method of the present invention; and Figures 3a to 3g are the second views of the method of the present invention Sectional flow chart of the embodiment. Explanation of symbols: 110, 210, 310 ~ semiconductor substrate; 111, 2 11, 3 11 ~ first insulating layer; 11 2, 2 1 2, 3 1 2 ~ contact plug; 11 3, 2 1 3, 3 1 3 ~ Etch stop layer;

Mi, ', Mi', M2, M2 ', M2, ~~ memory elements; 11 4, 2 1 4, 3 1 4 ~ second insulation layer; 115, 215, 315 ~ first electrode layer; 2 1 6, 3 1 6 ~ sacrificial layer; 116, 217, 317 ~ capacitor dielectric layer; 117, 218, 318 ~ second electrode layer; 11 8 ~ crown capacitor area; OP ~ open area.

0503-7970TWf (N); TSMC2002-0047; Shawn.ptd page 12

Claims (1)

554479 6. Scope of patent application 1. A method for manufacturing a crown capacitor, comprising: providing a semiconductor substrate covered with an insulating layer; etching the insulating layer to form an open area; forming a conformable (c ο nf 〇rma 1) The first electrode layer is covered on the insulating layer and in the opening area; a sacrificial layer is formed on the first electrode layer and filled in the opening area; the sacrificial layer outside the opening area is removed; the insulating layer is removed A first electrode layer on top of the opening region to form a first electrode layer recessed in the opening; removing the sacrificial layer; forming a capacitive dielectric layer on the first electrode layer; and forming a second electrode Layer on the capacitor dielectric layer. 2. The method for manufacturing a crown capacitor according to item 1 of the scope of patent application, wherein the semiconductor substrate covered with an insulating layer has at least one memory element, a first insulating layer covers the memory element, and a contact plug A plug is formed in the first insulation layer, an etch stop layer is formed on the first insulation layer, and a second insulation layer is formed on the etch stop layer. 3. The method for manufacturing a crown capacitor according to item 2 of the scope of the patent application, wherein the second insulation layer is selected from one of silicon dioxide, borophospho glass, and fluorosilicon glass. 4. The method for manufacturing a crown capacitor as described in item 1 of the scope of patent application, wherein the first and second electrode layers are selected from one of titanium nitride, tantalum nitride, and nitride nitride. 5. The manufacturing method of the crown capacitor as described in item 1 of the scope of patent application 0503-7970TWf (N); TSMC2002-0047; Shawn.ptd Page 13 554479 6. Scope of patent application The first and second electrode layers are chemical vapor deposition method®. 6 · Shen He Zhicha Qin ㈤ formed from uw 'er accumulation ^^ ^ The crown electricity described in item 1 of the special spear capricorn encirclement | 5§ The ancient method of making i, the ancient Xuan dielectric valley state manufacturing method ° Electrical θ is selected from one of tantalum oxide (τ ~ 〇5), titanate 4 mesh 4 mesh η ^ ςτη, or hafnium dioxide (Hf02). Iridium gill barium (BST) • As described in the crown of the patent application, the material of the sacrificial layer is a photoresist material (pR p Ge Electric Method (BARC)). Τ J 和 辰 邛 杬 Reflective Layer material method tt :: ί: The method of forming the sacrificial layer material in the eighth step of the crown capacitor manufacturing method described in item 7 is spin coating 9 · The crown capacitor described in item 1 of the scope of patent application Manufacturing square grinding method (H '. The method of removing a part of the sacrificial layer outside the opening area is chemical mechanical research, 10 · The method of manufacturing a crown capacitor as described in item 1 of the scope of the patent application, where' the 'removes the insulating layer and the opening area The first electrode layer method in the upper part is a plasma etching method using a low bias power (10wbi as power). 11 · The method for manufacturing a crown capacitor as described in item 10 of the scope of patent application 'wherein the first electrode is removed The low-bias power plasma etching method used in the layer has a bias power range between 15W and 50W. 1 2. The method for manufacturing a crown capacitor as described in item 10 of the patent application scope, wherein the first Used by the electrode layer Bias power plasma etching method money 'is used to etch gas of chlorine (Π2) for primary gas. 3. As an application of the eye coronary electrical valley in item 1 of the scope of patent producing 554479 14. A method for manufacturing a crown capacitor includes: providing a semiconductor substrate covered with an insulating layer; etching the insulating layer to form an open region; and forming a A conformable first electrode layer is pasted on the insulating layer and in the opening area; '~ a conformal sacrificial layer is formed on the first electrode layer and the opening Removing the sacrificial layer outside the opening area; removing the first electrode layer on the insulating layer and the upper end portion of the opening area to form a first electrode layer recessed in the opening area; removing the sacrificial layer; forming a A capacitor dielectric layer is formed on the first electrode layer; and a second electrode layer is formed on the capacitor dielectric layer. 15 · The method for manufacturing a crown capacitor as described in item 14 of the scope of patent application, wherein the semiconductor substrate covered with an insulating layer has at least one memory element, a first insulating layer covers the memory element, and A contact plug is formed in the first insulation layer, an etch stop layer is formed on the first insulation layer, and a second insulation layer is formed on the etch stop layer. [16] The method for manufacturing a corrugated valley device according to item 15 of the scope of patent application, wherein the second insulating layer is selected from one of > silicon oxide, borophospho glass, and fluorine glass. Square Nitrogen 17 tb Coronary Capacitor Manufacturing '1 7 · As described in item 丨 4 of the scope of patent application ^-Gan tb — β θ emulsified titanium, nitriding boat method, wherein the first and second electrode layers are selected from Kill 0503-7970TWf (N); TSMC2002-0047; Shawn.ptd Page 15 554479 6. Scope of patent application One of the chemical cranes. 18. The method for manufacturing a crown capacitor as described in item 14 of the patent application, wherein 3 the first and second electrode layers are formed by a chemical vapor deposition method or a sputtering method. 1 9 · The method for manufacturing a crown capacitor as described in item 14 of the scope of the patent application, wherein the capacitor dielectric layer is selected from an oxide button (Ta205), lithium barium titanate (BST), or hafnium dioxide (Hf 〇2) One of them. Method 20 · The manufacturing method of the crown capacitor as described in item 4 of Shenyang Patent Fanyuan, wherein the material of the sacrificial layer is a polymer. Method 21. The method for manufacturing a crown capacitor as described in item 20 of the scope of patent application, wherein the method of forming the sacrificial layer is a chemical vapor deposition (CVD) method. Method 22 · The crown capacitor manufacturing method as described in item 20 of the Shenjing patent scope, wherein 'the southern molecular polymer (polymer) is formed by reacting gas and (3). 2 3 · A method for manufacturing a crown capacitor as described in item 22 of Shen Qing's patent scope, wherein the sacrificial layer forms a gas flow, where q F8 is between 6 and 8 s c cm and C0 is between 360 and 480 sccm. 24. A method for manufacturing a crown capacitor as described in item 22 of the scope of patent application, wherein the sacrificial layer forms an overhang on the opening area. 2 5 A method for manufacturing a crown capacitor according to the above item, wherein the method of the sacrificial layer outside the opening region is a chemical mechanical polishing method (CMP) or an etch back method. 2 6 · A crown capacitor system as described in item 4 of the patent application 0503-7970TWf (N); TSMC2002-0047; Shawn.ptd page 16 554479 6. Method of applying for patent scope, wherein the method of removing the first electrode layer on the insulating layer and the upper end of the opening area uses low bias power (Low bias power) plasma etching method. 2 7 · A method for manufacturing a crown capacitor as described in item 14 of the scope of the patent application 'wherein the low-bias power plasma method used to remove the first electrode layer' has a bias power range of 15W ~ 5. w. 28. A method for manufacturing a crown capacitor as described in item 27 of the scope of the patent application, wherein the etching gas used in the low-bias power plasma coining method used to remove the first electrode layer is chlorine gas (C丨 2) is its main gas. 2 9 · A method for manufacturing a crown capacitor as described in item 14 of the patent scope of Shenyan ’, wherein the material of the sacrificial layer remaining in the opening area is removed by electrical destruction engraving method. for 0503-7970TWf (N); TSMC2002-0047; Shawn.ptd page 17