TW441035B - Fabrication method of bitline contact for capacitor under bitline embedded DRAM - Google Patents

Abstract

The present invention comprises etching the first dielectric layer to form a through hole followed by depositing silicon material on the surface of the through hole, polished by chemical mechanical polishing so that the silicon material in the through hole is remained. Then form a photoresist pattern to protect the dielectric layer region of the predetermined memory cell electrode plate, etch the first dielectric layer unprotected by the photoresist pattern, and remove the photoresist pattern, the next step is to form a capacitive dielectric layer on the surface of the silicon material, form a polysilicon layer covering the capacitive dielectric layer, then form the second dielectric layer on the surface of the polysilicon layer, coat photoresist on the polysilicon layer, etch part of the photoresist to expose the second dielectric layer on the upper surface of the polysilicon layer, then remove the exposed second dielectric layer, oxidize the upper surface of the polysilicon layer to form an oxide layer on it, etch anisotropically the second dielectric layer and the polysilicon layer to define the capacitor, form the third dielectric layer to cover the capacitor, form the bitline contact through hole and memory cell electrode plate in the third dielectric layer, the conductive pattern is formed on the third dielectric layer and is aligned to the bitline contact through hole and memory cell electrode plate through hole.

Description

V. Description of the invention (1) Field of the invention: The present invention relates to a dynamic random access memory (DRA M) of a semiconductor process. In particular, it is a type of embedded capacitor under the bit line (CUB) Manufacturing method of dynamic random access memory (embedded DR AM). BACKGROUND OF THE INVENTION: Dynamic random access memory (DR AM) is a main volatile memory. High-density dynamic random access memory (DRAM) has made significant progress in integrated circuit technology. The memory cell is usually composed of a capacitor and a transistor. The replacement region of the transistor is connected to one end of the capacitor. One end is connected to the reference potential, so the process of manufacturing DRAM memory cells includes transistors and capacitors. 'Electrical contact between the capacitor and the source region, digital information is stored in the capacitor, and metal-oxygen half field effect transistors and bit lines are used. (Bit line), word line (word 1 ine) array to obtain the digital data of the capacitor. Under the shrinkage of the components, the surface area of the capacitor is reduced in order to increase the degree of accumulation. The method and structure of the capacitor manufacturing process so that the capacitive performance does not decrease is the development direction of the capacitor technology. Generally, a typical dynamic random access memory is to fabricate a metal-oxide-semiconductor field-effect transistor (MOSFET) and a capacitor on a semiconductor substrate. A contact window is used to connect the capacitor's storage node (storage node) and the gold field half-field.

Page 5 441 03 5 V. Description of the invention (2) The source of Z ί makes electrical contact. By the electrical properties of the capacitor and the source region, touch :::: The information is stored in the capacitor and the etched + DRAM array is used to obtain the etched + DRAM to store the signal heart = shell material. The above capacitors are female ^, that is, the more mechanical charges stored in capacitors, the more soft errors generated by particles (such as mules) will cause the amplifier to read data. It can be greatly reduced, and it can be reduced, and then add ", the frequency-generally increase the capacitor's charge storage capacity methods are (1) seeking high dielectric materials' to increase the number of stored charges per unit area of the capacitor; 2 reduce the v dielectric layer (3) increase the surface area of the capacitor, so that the number of charges stored in the valley device is increased. Generally, the flat capacitor is the most commonly used valley structure. In order to increase the density of components, DRAM technology tends to reduce the size. Because the reduction in size also reduces the capacitance area, the capacitance storage capacity is reduced, and the capacitance is replenished (refresh ) The frequency will also increase. In order to solve the above problems, trench capacitors (such as us

Patent No. 5'374'580) and stacked capacitors, trench capacitors sometimes have the phenomenon of leakage current. 'Secondly reducing the thickness of the dielectric layer of the capacitor can also increase the capacity of the capacitor' but based on yield and stability considerations This method also has its limitations. Secondly, 'a crown shape capacitor or a hollow cylindrical structure (cylindrical structure) capacitor has also been published' another capacitor_over-bit-capacitor structure of polycrystalline silicon with hemispherical grains line [COB] cell with a hemispherical-grain (HSG) polysilicon storage

Page 6 44103 5 V. Description of invention (3) node) has also been published in the literature, such as " A Capacitor-Over-Bit-Line Cell With Hemispherical-Grain Storge Node For 64Mb Drams ", M. Sakao etc. microelectr research laboratories, NECC orporati ο n). The hemispherical grains of polycrystalline silicon are deposited by chemical vapor deposition at the transition temperature from amorphous-Si to polycrystalline-Si. The other is a cylindrical capacitor using Hemispherical-Grained Si. Please refer to " A New Cylindrical Capacitor Using Hemispherical Grained Si For 256 Mb Drains ", H. Watanabe et al ., Tech Dig, Dec. 1992, pp.259-262. Figure 1 shows the traditional bit-on-line capacitor (COB) structure. It has a plurality of insulating regions 3 in the crystal garden 1, and is divided into a logic element region and a DRAM region in the wafer 1. There are a plurality of transistors 9 in the logic. The device region has a transistor U in the DRAM region. A polycrystalline silicon plug 13 is located in the insulating layer 15 and a crown type capacitor 19 is formed on which a bit line 17 is formed and connected to the bit line. To form a bit line, a contact area must be defined by a lithography process in the insulating layer 21, and then a metal, deep ultraviolet lithography, and etching process can be used to define the bit line. However, the conditions of the above key processes are not easy to control. Will cause short circuit with subsequent capacitors. Capacitor (COB) structures based on bit lines are difficult and complex to make. So there is another kind of bit line capacitor

V. Description of the invention (4) Structural development of (CUB). In order to reduce the manufacturing cost of embedded DRAM, logic circuits and DRAM manufacturing processes are usually integrated. (Designru 1 e). Figure 2 shows a CUB structure with elements as large as COB. As can be seen from the figure, the difference is that the capacitor 25 is located below bit line 27. If the CUB embedded DRAM process uses metal bit lines , Can save the polycrystalline silicon bit line and CIC (contact of bit line to SAC) module 9 However, in the CUB embedded DR AM process, 'memory_1 孓 polycrystalline silicon plate see the side of the window ^^ Remove before etching. Otherwise, the metal bit line will be short-circuited with the electrode plate. The above steps are the key and difficult steps in the CUB embedded DRAM process. Therefore, the present invention proposes a simpler bit-line capacitor embedded dynamic random access memory. Method for making bit line contact. OBJECTS AND SUMMARY OF THE INVENTION The object of the present invention is a method for manufacturing a bit-line capacitor embedded type dynamic random access memory bit line contact manufacturing method. t. Another object of the present invention is to expose the capacitor plate by using silicon nitride on the side wall to etch the upper surface of the plate. ′ Use silicon nitride, polycrystalline silicon, and hafnium oxide to selectively define the capacitor. Another object of the present invention is to simplify the manufacturing process by using the CUB process to omit the steps of defining bit lines and defining the contact area. The steps of the present invention include coating a thin oxide oxide liner on the gate structure and the surface of the wafer to reduce stress, and then an etch barrier

Page 8 V. Description of the invention (5) The layer is re-deposited on the above-mentioned liner. In order to achieve a good etching selection ratio, a dielectric layer as an insulating layer is formed on the above-mentioned gate structure and wafer. 'An etch barrier layer is then deposited on the film layer. Then, a self-aligned contact (SAC) conductive plug is formed. An insulating material such as an oxide layer is successively deposited on the dielectric layer, and a contact via is formed on the oxide layer by lithography and etching processes to form a hemispherical grains silicon (HSG-Si) layer in the oxide layer. On top of that, a photoresist is applied in the contact hole to protect the required HSG-Si area. Then the etch-back or chemical mechanical polishing technology is used to remove the HSG-Si on the oxide layer and the photoresist is removed. The next step is to apply a photoresist pattern to protect the memory cell oxide ('node oxide'). Wet etching is used to remove the exposed oxide layer, and then the photoresist pattern is removed to form the lower electrode of the crown type capacitor. A dielectric film is deposited on the surface of the HSG-Si structure as the capacitor's dielectric layer. Generally, this dielectric layer can be a composite film of N / 〇, 〇 / “〇 or a high dielectric film. The conductive layer is The LPCVD method is deposited on the above dielectric film to be used as the electrode plate of the capacitor. Subsequently, a silicon nitride film is deposited along the surface of the silicon plate. After the capacitor is fabricated, a photoresist is applied to cover the sun circle. The silicon nitride layer on the surface is exposed. The exposed silicon nitride layer is removed by hot glacial acid, and then the coated photoresist is removed. Since the silicon nitride on the surface of the polycrystalline silicon electrode plate is removed, so The upper surface of the polycrystalline silicon is also exposed. The upper surface of the polycrystalline silicon is oxidized by an oxidation process to form an oxide layer as an insulation thereon. The silicon nitride layer and the polycrystalline silicon layer are etched by self-alignment.

China Page 9 V. Description of the invention (6) The process is etched to separate the capacitor, and then an insulating layer is deposited on the capacitor as the insulating layer. Lithography and etching techniques are used to etch the above-mentioned insulation layer to form bit line contact holes and contact holes of the memory cell plate to penetrate the above-mentioned insulation layer. After that, a conductive plug such as polycrystalline silicon is tied to the contact hole of the bit line and the contact hole of the memory cell plate is used as a conductive connection. The interconnection pattern is defined on it. Detailed description of the invention: The present invention discloses a method for manufacturing a high-density dynamic random access memory. The present invention proposes a simple bit-line contact of a bit-line capacitance-embedded dynamic random-access memory. Production Method. In addition, in the present invention, hemispherical grains are used to increase the surface area of the capacitor. Furthermore, the present invention can simplify the CUB process and does not require a key lithographic process. The method of the present invention will be referred to as a below. Figure 3. The semiconductor material is used as a substrate or a wafer 2. For example, a single crystal silicon with a direction of < 1 00 > may be used as the wafer of the embodiment of the present invention. Then, an isolation region such as a shallow trench isolation region is used. (Shallow trench 1 sol at ι〇η; ST I) 4 was first fabricated on wafer 2 using known techniques

On page 10. Generally, shallow trenches are formed in the wafer t by lithography and etching, and then backfilled into the shallow trenches with an oxide layer deposited by chemical vapor deposition. This \ can also use other isolation technology to make isolated areas, such as a field can use LOCOS or other related field oxidation insulation area 4 4103 5 V. Description of the invention (7) ------ Technology is formed on the crystal Above the circle 2 is used as the insulation between the components. In a word, 'lithography and etching technology can be used to etch silicon nitride and then use the oxidation process to form a field oxidation region on the wafer 2 and to emulsify the two composite layers on the hot disc. The above-mentioned cutting layer is removed by acid, followed by a layer of hydrogen 1 acid to remove oxygen, followed by a silicon dioxide layer 6 formed on wafer 2 as a gate oxygen layer. This silicon dioxide layer is generally used for thermal oxidation Method, the temperature of the process is 70 to 1 loot: the thickness of between about 50 to 200 angstroms, of course, generally = chemistries such as chemical vapor deposition method with 7 £; 〇5 as a reactant can also form two The silicon oxide layer 6 is still shown in FIG. 1. The gate structure is patterned on the wafer using conventional techniques. The gate structure may include a polycrystalline silicon layer 8 deposited on the silicon dioxide layer 6. The polycrystalline silicon layer 8 is formed by chemical vapor deposition (C VD), and the thickness is about Between 00 angstroms, a metal silicide such as a tungsten silicide layer 10 is formed on the polycrystalline silicon layer 8 described above, and then a silicon nitride U cap layer is deposited and formed on the gate structure, and then a The shadow and etching technology forms the idle electrode structure and the interconnects in the area such as bit lines. Then, doped regions or lightly doped drains (LDD) 12 are formed by ion implantation. The above process is made by a known technology and is not the focus of the present invention. Therefore, it will not be described in detail. A liner layer, such as a thin oxide layer 1 4, covers the inter-electrode structure and the surface of the wafer 2 to reduce the stress, and then a barrier layer 16 is etched and then deposited on the liner layer 4. In order to achieve a good name, choose a material that can use silicon nitride, silicon oxynitride, or similar materials.

Page Π 4 4 彳 03 5 V. Description of the invention (8)-~ ^ The material is used as the etching barrier layer Ifi. — X, ^ lb The dielectric layer 18 as the insulating layer is formed on the above gate structure and F *, I, / bk of the wafer 2. _ Into the bright circle ^ on the above, the preferred embodiment of the dielectric Electrocution 18 is an oxide or silicon dioxide formed with TEOS. An etch barrier layer 18a is then deposited on the TEOS as a barrier layer for subsequent oxide removal. The etch barrier layer 18a can be made of silicon oxynitride. After that, a self-aligned contact (SAC) conductive plug 2 is formed using the etching and deposition technology in the dielectric layer 18 described above. For this embodiment, a polycrystalline silicon plug (p. ly plug), in this preferred embodiment, 'the CVD can be deposited on the polycrystalline silicon backfill into the contact perforations' and then etched or ground to form the aforementioned polycrystalline silicon plug. In the best embodiment, the polycrystalline silicon of the present invention is doped polysi 1 icon or synchronously doped polysi 1 icon. An insulating material such as an oxide layer 22 is successively deposited on the dielectric layer 18a. Referring to FIG. 3, for subsequent performance, the capacitor can be in electrical contact with the transistor. One of the methods is to use a contact hole 2 4 is used as a connection, a contact hole 2 4 is formed in the oxide layer 22 using a lithography and etching process. A hemispherical grain layer (hemispherical grains si 1 icon; HSG-Si) 26 is deposited on the oxide layer 22. Next, a selective step is used to apply a photoresist (not shown) in the contact holes 24 to protect the desired HSG-Si 26 '. Then, the etch-back or chemical mechanical polishing technology is used to remove the HSG- on the oxide layer 22- Si 26. The photoresist is subsequently removed so as to remain on the surface of the contact hole 24. In a preferred embodiment, it is selected to have hemispherical hair

Page 12 5. Description of the invention (9)-Grain (Hemi-Spherical Grain; HSG) can effectively increase the surface area of the storage electrode. The step of forming a silicon layer with hemispherical silicon grains is to first deposit a silicon thin film, and then form a silicon seed (nuc 丨 e 丨) on the silicon thin film. For example, a silicon-containing gas such as SiH ^ sizH 舁 can be used to form The temperature of the process is about 500 C to 60 Ot: between, the pressure is about 10-3 to 10-5 Torr, and then a thermal tempering process is performed in a high vacuum environment to form Hemispherical silicon grains. The process temperature is about 500 ° C to 600 (and the pressure is about 1E (-7) to 1EC-9) Torr. 'See Figure 4' Apply a photoresist pattern 2 8 to protect the memory cell plate oxide (node oxide), and then use wet etching to remove the exposed oxide layer 2 2. Generally, the above can be etched with B0E or HF solution. Oxidized layer 22. Subsequently, the photoresist pattern 28 'is removed to form a lower electrode of a crown type capacitor, and silicon oxide 18a serves as an etching barrier layer in this step. As shown in Figure 5, the next step is to deposit a dielectric film 30 as a dielectric layer of the capacitor along the surface of the HSG-Si 26 structure. Generally, this dielectric layer 30 can use N / 0, 0 / N / 0 The composite film is also made of a high dielectric film such as Ta 20 5, TiO. The conductive layer 32 is deposited by LPCVD on the above-mentioned dielectric film 30 as an electrode plate for the capacitor. The conductive layer 32 can be doped polysilicon and synchronously doped polysilicon. The evening (in-situ doped polysil icon) is formed. A silicon nitride film 34 is then deposited along the surface of the polycrystalline silicon plate 32. After the capacitor is manufactured, photoresist 3 6 is coated to cover the surface of wafer 2 and the photoresist 36 is etched to make the silicon nitride lower than the uppermost surface of the polycrystalline silicon plate 32. The layer 34 is exposed. OK in this law

Page 13 441035 V. Description of the Invention (ίο) Use the amount of etch-back photoresist to control the size of the crown type capacitor. Referring to FIG. 6, the exposed silicon nitride layer 34 is removed, and then the photoresist of the coating is removed. Generally, the silicon nitride layer 34 can be removed by etching with a hot phosphoric acid solution. The above-mentioned silicon nitride layer 34 is made of low pressure chemical vapor deposition (LPCVD) '' Plasma Enhance Chemical Vapor Deposition (PECVD) or high-density plasma chemistry Vapor deposition (High Density Plasma Chemical Vapor Deposition; HDPCVD). The reaction gas can be SiH4, NH3, N2, N20 or SiH2Cl2, NH3, N2, N20. Since the silicon nitride on the upper surface of the polycrystalline silicon plate 32 is removed, the upper surface of the polycrystalline silicon 32 is also exposed. As shown in Figure 7, the oxidation process is used to oxidize the upper surface of the polycrystalline silicon 32 to form an oxide layer 38 as an insulation thereon. Generally, a wet oxygen process can be used, and the oxidation temperature is between 70 ° C and 900 ° C. . In a preferred embodiment, the thickness of the oxide layer 38 is about 100 to 300 angstroms, preferably about 200 angstroms. The above-mentioned oxidation temperature is about 6500 to 700 degrees Celsius. As shown in FIG. 8, the silicon nitride layer 34 and the polycrystalline silicon layer 32 are etched using a self-aligned etching process to separate the capacitors. In this step, an anisotropic etching technique is used to etch a highly selective etchant between oxide and polycrystalline silicon. Subsequently, an insulating layer 40, such as an oxide layer, BPSG, PSG, or other equivalent functional material, is deposited on the capacitor as an insulating layer 'as shown in FIG. The above-mentioned insulating layer 40 is etched by lithography and etching techniques to form bit lines

Page 14 4 4 103 5 V. Description of the invention (11) The contact hole 4 2 and the contact hole 4 4 of the memory cell plate penetrate the aforementioned insulating layer 40. Then, a conductive plug such as polycrystalline silicon is tethered into the bit line contact hole 4 2 and the contact hole 44 of the memory cell plate as a conductive connection. The interconnect pattern 46 is formed on the insulating layer 40 by sputtering or other related methods, and then it is defined by the pattern-related processes such as lithography and etching at the bit line contact hole 4 2 and the memory cell. The contact holes of the board are above 4 4. In the present invention, in order to consider the degree of accumulation, the present invention is more flexible in process because it can reduce the distance between the bit line contact and the memory cell plate. In the absence of a critical lithography process, the present invention utilizes the immersion etch-back of the entire crown-type electrode to enhance the reduced space (the size and height of the crown-type). In addition, in the method, for the bit line, the sidewall of the memory cell polycrystalline silicon is protected by a silicon nitride layer. The present invention has been described above with reference to the preferred embodiments, and those skilled in the art will be able to make some minor modifications without departing from the spirit of the present invention. For example, the combination of materials for highly selective etching is not limited to the embodiments of the present invention. The dielectric material and the crown type of the conductive material are not limited to the HSG-Si of the present invention. The scope of patent protection depends on the scope of the attached patent application and its equivalent fields.

Page 15 Brief Description of Drawings Schematic description: The preferred embodiment of the present invention will be explained in more detail in the following explanatory texts with the following figures: Figure 1 is a cross-sectional view of the COB structure. Figure 2 is a cross-sectional view of the CUB structure. FIG. 3 is a cross-sectional view of a semiconductor wafer in a step of forming a lower electrode of a crown type capacitor according to the present invention. FIG. 4 is a cross-sectional view of a semiconductor wafer in the step of removing an oxide layer according to the present invention. FIG. 5 is a cross-sectional view of a semiconductor wafer in the step of forming a crown-type capacitor dielectric layer and an upper electrode according to the present invention. FIG. 6 is a cross-sectional view of a semiconductor wafer in the step of etching silicon nitride to expose a capacitor plate according to the present invention. FIG. 7 is a cross-sectional view of a semiconductor wafer on the surface step of an oxidizing capacitor plate according to the present invention. FIG. 8 is a cross-sectional view of a semiconductor wafer according to the present invention using a highly selective etching to separate capacitor steps. FIG. 9 is a cross-sectional view of a semiconductor wafer in the step of forming a bit line according to the present invention.

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Claims (1)

441035 VI. Application Patent Scope 1. A method for manufacturing bit line contact of a capacitor embedded in a bit line dynamic random access memory, the method comprising: forming a first dielectric layer on a wafer; and etching the first dielectric layer A dielectric layer is formed to form a perforation in the first dielectric layer; a silicon material is deposited on the surface of the perforation; a photoresist pattern is formed to protect a predetermined area of the dielectric layer of the memory cell plate; the etching is not protected by the photoresist pattern The first dielectric layer; removing the photoresist pattern; forming a capacitor dielectric layer on the surface of the silicon material; forming a polycrystalline silicon layer to cover the capacitor dielectric layer: forming a second dielectric layer on the polycrystalline silicon layer Coating the photoresist on the polycrystalline silicon layer; etching the part of the photoresist to expose the second dielectric layer on the upper surface of the polycrystalline silicon layer; removing the exposed second dielectric Layer; removing the photoresist, the remaining second dielectric layer is located on the side of the polycrystalline silicon layer to expose the upper surface of the polycrystalline silicon; oxidizing the upper surface of the polycrystalline silicon to form an oxide layer on the layer On; the second dielectric is anisotropically etched Layer and the polycrystalline silicon layer to define a capacitor; forming a third dielectric layer to cover the capacitor; forming a bit line contact via and a memory cell plate perforating in the third dielectric layer; forming a first conductive plug on the Bit line contact perforations and perforations of the memory cell plate; and Page 17 6. Scope of patent application: A conductive pattern is formed on the third dielectric layer and is aligned with the bit line contact hole and the memory cell plate through hole. 2. According to the method for making bit line embedded capacitors of dynamic line random access memory for bit line under item 1 of the scope of patent application, before forming the above first dielectric layer, the method further includes the following steps: A crystal is formed on the wafer to form a fourth dielectric layer on the plurality of transistors; and a second conductive plug is formed in the fourth dielectric layer, wherein the perforation corresponds to the second conductive plug. 3. For the manufacturing method of bit line contact for embedded bit-line dynamic random access memory of bit-line capacitor in item 1 of the patent application, the above-mentioned silicon material includes hemispherical grain silicon. 4. The manufacturing method of bit line contact of embedded bit-type dynamic random access memory for bit line under item 1 of the scope of patent application, wherein said first dielectric layer includes an oxide layer. 5. For the manufacturing method of bit line contact of embedded bit-type dynamic random access memory for bit-line capacitors under item 4 of the patent application, wherein the above-mentioned first dielectric layer is removed using a BOE solution. 6. If the bit-line capacitor embedded dynamic random is applied for item 4 in the scope of patent application Page 18 6. Scope of Patent Application The manufacturing method of bit line contact of access memory, in which the first dielectric layer is removed by HF solution. 7. The manufacturing method of bit line contact of embedded bit-line dynamic random access memory for bit line capacitors under item 1 of the scope of patent application, wherein said second dielectric layer includes a vaporized layer. 8. For the manufacturing method of bit line contact of embedded bit-type dynamic random access memory for bit line under item 7 of the scope of patent application, wherein the second dielectric layer strip is removed by using hot phosphoric acid solution. 9. The manufacturing method of bit line contact of embedded bit-type dynamic random access memory for bit line under item 1 of the scope of patent application, wherein said third dielectric layer includes an oxide layer. 10. The manufacturing method of bit line contact of embedded bit-type dynamic random access memory of bit-line capacitor according to item 2 of the patent application, wherein said fourth dielectric layer includes an oxide layer. 11. The manufacturing method for bit line contact of embedded bit-type dynamic random access memory bit line capacitors under item 4 of the scope of patent application, wherein the etchant of the above anisotropic etching is an oxide with polycrystalline silicon High etch selectivity. 1 2. If the bit-line offline capacitor is embedded in the patent application, the item is dynamic and random. Page 19 4 41 03 5 VI. Scope of patent application Manufacturing method for accessing memory bit lines, wherein the thickness of the above oxide layer is about 100 to 300 angstroms. 13. The manufacturing method of bit line contact for embedded bit-line dynamic random access memory of bit-line capacitors according to item 12 of the patent application, wherein the thickness of the above oxide layer is about 200 angstroms. 14. The method according to item 1 of the scope of patent application, wherein the above-mentioned oxidation temperature is about 650-70 ° C. 15. The method according to item 1 of the scope of patent application, wherein the silicon nitride layer is a low pressure chemical vapor deposition (LPCVD) method or a plasma enhanced chemical vapor deposition method (Plasma Enhance). Chemical Vapor Deposition (PECVD) or High Density Plasma Chemical Vapor Deposition (HDPCVD). 16. The method according to item 15 of the scope of patent application, wherein the above-mentioned reaction gas is SiH4 'Ν3, Ν2, Μ. 17. The method according to item 15 of the scope of patent application, wherein the above-mentioned reaction gas is SiH2Cl2, Ν3, Ν2, Μ. Page 20