CN108766899A - The manufacturing method and its structure of integrated circuit - Google Patents
The manufacturing method and its structure of integrated circuit Download PDFInfo
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- CN108766899A CN108766899A CN201810536752.8A CN201810536752A CN108766899A CN 108766899 A CN108766899 A CN 108766899A CN 201810536752 A CN201810536752 A CN 201810536752A CN 108766899 A CN108766899 A CN 108766899A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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Abstract
The present invention relates to a kind of method for manufacturing integrated circuit, are related to integrated circuit technique, including：Step S1 provides wafer, and wafer includes substrate and the first layer insulating, and the first layer insulating is located on substrate；Step S2 forms drain electrode and the source electrode of a transistor on the first layer insulating；Step S3 forms the grid of transistor and an at least metal line for passive device on the first layer insulating；Step S4, forms the second layer insulating, and the second layer insulating surrounds at least metal line on transistor and the first layer insulating；Step S5, forms multiple connecting holes in the second layer insulating, and one end of multiple connecting holes connects at least metal line on the first layer insulating；And step S6, an at least metal line for passive device is formed on the second layer insulating, the other end of multiple connecting holes connects at least metal line on the second layer insulating, to form an at least passive device, to improve the performance of passive device.
Description
Technical field
The present invention relates to a kind of ic manufacturing technology more particularly to a kind of integrated circuits improving passive device performance
Manufacturing method.
Background technology
In semiconductor integrated circuit, active member and passive device are needed to complete certain function.Common active
Element is just like transistor etc., and common passive device is just like capacitance and inductance etc..For passive device, it is desirable to capacitance and inductance
Characteristic is become better and better, and the capacitance that can be realized is increasing；And in semiconductor integrated circuit manufacturing process, it is desirable to which step is more next
Fewer, manufacture is more and more simpler.
Invention content
The purpose of the present invention is to provide a kind of manufacturing methods of integrated circuit, to improve passive device performance or increase electricity
The capacitance of appearance.
The manufacturing method of integrated circuit provided by the invention, including：Step S1, provides a wafer, wafer include substrate and
First layer insulating, wherein the first layer insulating layer is located on the substrate；Step S2, on first layer insulating
Form drain electrode and the source electrode of a transistor；Step S3, formed on first layer insulating transistor grid and
An at least metal line for passive device；Step S4, forms the second layer insulating, and second layer insulating surrounds the crystal
An at least metal line on pipe and the first layer insulating；Step S5 is formed multiple in second layer insulating
Connecting hole, wherein one end of the multiple connecting hole connects at least metal line on the first layer insulating；And
Step S6, an at least metal line for formation passive device on second layer insulating, and the multiple connecting hole
The other end connects at least metal line on the second layer insulating, to form an at least passive device.
Further, further include step S7, form third layer insulating, it is exhausted that the third layer insulating surrounds the second layer
An at least metal line on edge layer；Step S8, forms multiple vias, and one end of the multiple via connects the second layer
An at least metal line on insulating layer；Step S9 forms passive device extremely on the third layer insulating
A few metal line, and at least metal line on the other end connection third layer insulating of the multiple via,
To form an at least passive device.
Further, step S7 further includes step S71, and one first resistance is formed before forming the third layer insulating
Barrier, first barrier layer are located on second layer insulating and fill at least gold medal on the second layer insulating
Belong between connecting up.
Further, step S8 further includes step S81, formed before forming the multiple via the second barrier layer and
4th insulating layer, wherein second barrier layer is between the third insulating layer and the 4th insulating layer, and described
Between the multiple via is filled on two barrier layers, at least gold medal on the 4th insulating layer filling third layer insulating
Between belonging to wiring, and at least metal line on overlays third layer insulating layer.
Further, at least metal line on the first layer insulating includes one first metal line and one
Second metal line, wherein first metal line and second metal line constitute two electrodes of a capacitance.
Further, at least metal line on the first layer insulating includes a third metal line, institute
It is an inductor winding to state third metal line.
Further, at least metal line on the first layer insulating includes one first metal line, one
Second metal line and a third metal line, the multiple connecting hole include one first connecting hole, one second connecting hole, third
Connecting hole and one the 4th connecting hole, wherein one end of first connecting hole connects first metal line, described second connects
The one end for connecing hole connects second metal line, and one end of the third connecting hole connects the one of the third metal line
End, one end of the 4th connecting hole connects the other end of the third metal line, on the second layer insulating it is described extremely
A few metal line includes one the 4th metal line, fifth metal wiring and one the 6th metal line, first connecting hole
The other end connect the 4th metal line, the other end of second connecting hole connects the fifth metal wiring, described
The other end of third connecting hole connects one end of the 6th metal line, the other end connection of the 4th connecting hole described the
The other end of six metal lines, so that first metal line is electrically connected with the 4th metal line and constitutes the of capacitance
One electrode, second metal line connect up the second electrode for the capacitance that is electrically connected to form, the third gold with the fifth metal
Belong to wiring to be electrically connected to form an inductance with the 6th metal line.
Further, at least metal line on the first layer insulating includes one first metal line, one
Second metal line and a third metal line, the multiple connecting hole include one first connecting hole, one second connecting hole, one the
Three connecting holes and one the 4th connecting hole, wherein one end connection first metal line of first connecting hole, described second
One end of connecting hole connects second metal line, and one end of the third connecting hole connects the one of the third metal line
End, one end of the 4th connecting hole connects the other end of the third metal line, on the second layer insulating it is described extremely
A few metal line includes one the 4th metal line, fifth metal wiring and one the 6th metal line, first connecting hole
The other end connect the 4th metal line, the other end of second connecting hole connects the fifth metal wiring, described
The other end of third connecting hole connects one end of the 6th metal line, the other end connection of the 4th connecting hole described the
The other end of six metal lines, the multiple via include one first via, one second via, a third via and one the 4th mistake
The one end in hole, first via connects the 4th metal line, and one end of second via connects the fifth metal
Wiring, one end of the third via connect one end of the 6th metal line, described in one end connection of the 4th via
The other end of 6th metal line, at least metal line on third layer insulating include one the 7th metal line,
The other end of one the 8th metal line and one the 9th metal line, first via connects the 7th metal line, described
The other end of second via connects the 8th metal line, and the other end of the third via connects the 9th metal line
One end, the other end of the 4th via connects the other end of the 9th metal line so that first metal line,
4th metal line is electrically connected and constitutes the first electrode of capacitance, second hardware cloth with the 7th metal line
Line, the fifth metal connect up the second electrode for the capacitance that is electrically connected to form with the 8th metal line, the third hardware cloth
Line, the 6th metal line and the 9th metal line are electrically connected to form an inductance.
The present invention further also provides a kind of integrated circuit structure, which is characterized in that including：One substrate and a first layer are exhausted
Edge layer, first layer insulating are located at the substrate；An at least metal line for one transistor and passive device, it is described
An at least metal line for transistor and passive device is located on first layer insulating and is insulated by a second layer
Layer surrounds；Multiple connecting holes, the multiple connecting hole is located in second layer insulating, and one end of the multiple connecting hole
Connect at least metal line on the first layer insulating；Passive device on second layer insulating
An at least metal line and a third layer insulating, the third layer insulating surround on the second layer insulating it is described at least
One metal line, and the other end of the multiple connecting hole connects at least metal line on the second layer insulating,
To form an at least passive device.
Further, further include at least the one of multiple vias and the passive device on the third layer insulating
Metal line, wherein one end of the multiple via connects at least metal line on the second layer insulating, it is described
An at least metal line on the other end connection third layer insulating of multiple vias, to form at least one passive member
Part.
Further, at least metal line on the first layer insulating includes one first metal line, one
Second metal line and a third metal line, the multiple connecting hole include one first connecting hole, one second connecting hole, one the
Three connecting holes and one the 4th connecting hole, wherein one end connection first metal line of first connecting hole, described second
One end of connecting hole connects second metal line, and one end of the third connecting hole connects the one of the third metal line
End, one end of the 4th connecting hole connects the other end of the third metal line, on the second layer insulating it is described extremely
A few metal line includes one the 4th metal line, fifth metal wiring and one the 6th metal line, first connecting hole
The other end connect the 4th metal line, the other end of second connecting hole connects the fifth metal wiring, described
The other end of third connecting hole connects one end of the 6th metal line, the other end connection of the 4th connecting hole described the
The other end of six metal lines, so that first metal line is electrically connected with the 4th metal line and constitutes the of capacitance
One electrode, second metal line connect up the second electrode for the capacitance that is electrically connected to form, the third gold with the fifth metal
Belong to wiring to be electrically connected to form an inductance with the 6th metal line.
Further, at least metal line on the first layer insulating includes one first metal line, one
Second metal line and a third metal line, the multiple connecting hole include one first connecting hole, one second connecting hole, one the
Three connecting holes and one the 4th connecting hole, wherein one end connection first metal line of first connecting hole, described second
One end of connecting hole connects second metal line, and one end of the third connecting hole connects the one of the third metal line
End, one end of the 4th connecting hole connects the other end of the third metal line, on the second layer insulating it is described extremely
A few metal line includes one the 4th metal line, fifth metal wiring and one the 6th metal line, first connecting hole
The other end connect the 4th metal line, the other end of second connecting hole connects the fifth metal wiring, described
The other end of third connecting hole connects one end of the 6th metal line, the other end connection of the 4th connecting hole described the
The other end of six metal lines, the multiple via include one first via, one second via, a third via and one the 4th mistake
The one end in hole, first via connects the 4th metal line, and one end of second via connects the fifth metal
Wiring, one end of the third via connect one end of the 6th metal line, described in one end connection of the 4th via
The other end of 6th metal line, at least metal line on third layer insulating include one the 7th metal line,
The other end of one the 8th metal line and one the 9th metal line, first via connects the 7th metal line, described
The other end of second via connects the 8th metal line, and the other end of the third via connects the 9th metal line
One end, the other end of the 4th via connects the other end of the 9th metal line so that first metal line,
4th metal line is electrically connected and constitutes the first electrode of capacitance, second hardware cloth with the 7th metal line
Line, the fifth metal connect up the second electrode for the capacitance that is electrically connected to form with the 8th metal line, the third hardware cloth
Line, the 6th metal line and the 9th metal line are electrically connected to form an inductance.
The manufacturing method of integrated circuit provided by the invention, by being formed simultaneously active member on a layer insulating
The metal line of the metal line and passive device (as inductively or capacitively) of (such as transistor), and will be on the layer by connecting hole
The metal line of passive device is connect with the metal line of passive device on other insulating layers, not only constitutes active member and quilt
The integrated morphology of dynamic element, and so that passive device is increased one (as inductively or capacitively) under the premise of not increasing technological process
Layer metal line, therefore improve the performance of passive device (as inductively or capacitively) or increase the capacitance of capacitance.
Description of the drawings
Fig. 1 is the flow chart of the manufacturing method of the integrated circuit of one embodiment of the invention.
Fig. 2 is the manufacturing process sectional view of the integrated circuit of one embodiment of the invention.
Fig. 3 is the manufacturing process sectional view of the integrated circuit of one embodiment of the invention.
Fig. 4 is the manufacturing process vertical view of the integrated circuit of one embodiment of the invention.
Fig. 5 is the manufacturing process sectional view of the integrated circuit of one embodiment of the invention.
Fig. 6 is the manufacturing process sectional view of the integrated circuit of one embodiment of the invention.
Fig. 7 is the manufacturing process sectional view of the integrated circuit of one embodiment of the invention.
Fig. 8 is the manufacturing process sectional view of the integrated circuit of one embodiment of the invention.
The reference numerals are as follows for main element in figure：
110, substrate；120, the first layer insulating；130, transistor；141, the first metal line；142, the second hardware cloth
Line；150, third metal line；171, the first connecting hole；172, the second connecting hole；173, third connecting hole；174, the 4th connection
Hole；160, the second layer insulating；241, the 4th metal line；242, fifth metal connects up；250, the 6th metal line.
Specific implementation mode
Below in conjunction with attached drawing, clear, complete description is carried out to the technical solution in the present invention, it is clear that described
Embodiment is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is general
All other embodiment that logical technical staff is obtained under the premise of not making creative work belongs to what the present invention protected
Range.
In an embodiment of the present invention, a kind of manufacturing method of integrated circuit is provided.Specifically, referring to Fig. 1, Fig. 1 is
The flow chart of the manufacturing method of the integrated circuit of one embodiment of the invention.As shown in Figure 1, the manufacturing method of the integrated circuit includes
Following steps：
Step S1 provides a wafer, and wafer includes substrate and the first layer insulating, wherein the first layer insulating is located at substrate
On.Specifically, referring to Fig. 2, Fig. 2 be one embodiment of the invention integrated circuit manufacturing process sectional view, as shown in Fig. 2,
Wafer includes substrate 110 and the first layer insulating 120, and the first layer insulating 120 is located on substrate 110.Wherein, first layer
Insulating layer 120 can be the insulating layer that buried layer oxide layer is constituted, and such first layer insulating 120 and substrate 110 constitute dielectric substrate.
Step S2 forms drain electrode and the source electrode of transistor on the first layer insulating.Specifically, referring to Fig. 2, as schemed
Shown in 2, drain electrode and the source configuration 131 of a transistor are formed on the first layer insulating 120, e.g., are based on FinFet modes
Form drain electrode and the source electrode of transistor.
Step S3 forms the grid of transistor and an at least metal line for passive device on the first layer insulating.
Specifically, referring to Fig. 3, Fig. 3 is the manufacturing process sectional view of the integrated circuit of one embodiment of the invention, as shown in figure 3, the
The grid 132 of transistor is formed on one layer insulating 120, so that drain electrode and source configuration 131 collectively form crystalline substance with grid 132
Body pipe 130 forms silicon SOI (Silicon-On-Insulator) structure in dielectric substrate.And the first layer insulating 120 it
A upper formation at least metal line, such as the first metal line 141 and the second metal line 142 or third metal line 150.?
In one embodiment of the invention, third metal line 150 is an inductor winding, the as metal line of a passive device.It please refers to
Fig. 4, Fig. 4 are the manufacturing process vertical view of the integrated circuit of one embodiment of the invention, as shown in figure 4, third metal line 150 is
One snakelike cyclic structure, certain third metal line 150 or other shapes, the present invention do not limit its shape and the number of turns
It is fixed.In an embodiment of the present invention, the first metal line 141 and the second metal line 142 may make up two electrodes of a capacitance,
The as metal line of a passive device.In an embodiment of the present invention, first hardware cloth is formed by metallization process
Line 141, the second metal line 142 and third metal line 150.In an embodiment of the present invention, the grid of transistor are formed simultaneously
Pole 132, the first metal line 141 and the second metal line 142；Or it is formed simultaneously the grid 132 and third hardware cloth of transistor
Line 150；Or it is formed simultaneously the grid 132 of transistor, the first metal line 141, the second metal line 142 and third metal line
150, namely the metal line and extremely of active member is formed simultaneously on the first layer insulating 120 by a metallization process
The metal line of a few passive device.As follows to be formed simultaneously the grid 132, the first metal line 141, the second metal of transistor
It is illustrated for wiring 142 and third metal line 150.
Step S4, forms the second layer insulating, and the second layer insulating surrounds on transistor and the first layer insulating extremely
A few metal line.Specifically, referring to Fig. 5, Fig. 5 be one embodiment of the invention integrated circuit manufacturing process sectional view,
As shown in figure 5, the second layer insulating 160 is located on the first layer insulating 120, filling transistor 130, the first metal line 141,
Between second metal line 142 and third metal line 150, and covering transistor 130, the first metal line 141, the second metal
Wiring 142 and third metal line 150, namely surround at least hardware cloth on transistor 130 and the first layer insulating 120
Line.Such as depositing technics is utilized to form the second layer insulating.
Step S5, forms multiple connecting holes in the second layer insulating, and one end of plurality of connecting hole connects first layer
An at least metal line on insulating layer.Specifically, referring to Fig. 6, Fig. 6 is the system of the integrated circuit of one embodiment of the invention
Process sectional view is made, is connected as shown in fig. 6, forming the first connecting hole 171, the second connecting hole 172, third connecting hole 173 and the 4th
Hole 174 is connect, wherein one end of the first connecting hole 171 connects the first metal line 141；One end connection the of second connecting hole 172
Two metal lines 142；One end of one end connection third metal line 150 of third connecting hole 173；The one of 4th connecting hole 174
The other end of end connection third metal line 150.The present invention does not limit the number of connecting hole, can be insulated according to first layer
Metal line on layer 120 is adjusted.
Step S6, an at least metal line for formation passive device on the second layer insulating, and multiple connecting holes
The other end connects at least metal line on the second layer insulating, to form an at least passive device.Specifically, please referring to
Fig. 7, Fig. 7 are the manufacturing process sectional view of the integrated circuit of one embodiment of the invention, as shown in fig. 7, in the second layer insulating 160
On form the 4th metal line 241, fifth metal wiring 242 and the 6th metal line 250, the first connecting hole 171 it is another
The 4th metal line 241 of end connection, wherein the other end connection fifth metal wiring 242 of the second connecting hole 172, wherein third connects
The other end for connecing hole 173 connects one end of the 6th metal line 250, wherein the other end of the 4th connecting hole 174 connects the 6th gold medal
The other end for belonging to wiring 250, so that the first metal line 141 is electrically connected and constitutes the first of capacitance with the 4th metal line 241
Electrode, the second metal line 142 and fifth metal wiring 242 are electrically connected to form the second electrode of capacitance, third metal line 150
It is electrically connected to form an inductance with the 6th metal line 250.
In semiconductor integrated circuit, it is desirable to which the characteristic of passive device (such as capacitance and inductance) is become better and better, and can be realized
Capacitance is increasing；And in semiconductor integrated circuit manufacturing process, it is desirable to which step is fewer and fewer, and manufacture is more and more simpler.
As described above, metal line and passive device by being formed simultaneously active member (such as transistor) on a layer insulating
The metal line of (as inductively or capacitively), and by connecting hole by the metal line of passive device on this layer and other insulating layers
On passive device metal line connection, not only constitute the integrated morphology of active member and passive device, and do not increasing
So that passive device is increased one layer of metal line (as inductively or capacitively) under the premise of technological process, therefore improves passive device
The performance of (as inductively or capacitively) or the capacitance for increasing capacitance.
In an embodiment of the present invention, it can include also further step S7, form third layer insulating, third layer insulation
Layer surrounds at least metal line on the second layer insulating.Specifically, referring to Fig. 8, Fig. 8 is one embodiment of the invention
The manufacturing process sectional view of integrated circuit, as shown in figure 8, third layer insulating 180 is located on the second layer insulating 160, filling
4th metal line 241, fifth metal wiring 242 and the 6th be between metal line 250, and covers the 4th metal line 241, the
Five metal lines 242 and the 6th metal line 250, namely surround at least metal line on the second layer insulating 160.Into
One step, further include step S8, forms multiple vias, and one end of plurality of via connects on the second layer insulating at least
One metal line.Specifically, referring to Fig. 8, as shown in figure 8, forming the first via 271, the second via 272, third via 273
With the 4th via 274, wherein the first via 271 one end connect the 4th metal line 241；One end of second via 272 connects
Fifth metal wiring 242；One end of third via 273 connects one end of the 6th metal line 250；One end of 4th via 274
Connect the other end of the 6th metal line 250.The present invention does not limit the number of connecting hole, can be according to the second layer insulating
Metal line on 160 is adjusted.Further, including step S9, passive device is formed on third layer insulating
An at least metal line, and multiple vias the other end connection third layer insulating on an at least metal line, with shape
At an at least passive device.Specifically, referring to Fig. 8, as shown in figure 8, forming the 7th metal on third layer insulating 180
The 341, the 8th metal line 342 and the 9th metal line 350 are connected up, the other end of the first via 271 connects the 7th metal line
341, the other end of the second via 272 connects the 8th metal line 342, and the other end of third via 273 connects the 9th hardware cloth
One end of line 350, the other end of the 4th via 274 connects the other end of the 9th metal line 350, so that the first metal line
141, the 4th metal line 241 is electrically connected and constitutes the first electrode of capacitance, the second metal line with the 7th metal line 341
142, fifth metal wiring 242 and the 8th metal line 342 are electrically connected to form the second electrode of capacitance, third metal line 150,
6th metal line 250 and the 9th metal line 350 are electrically connected to form an inductance.
Further, step S7 further includes step S71, and one first blocking is formed before forming third layer insulating
Layer, the first barrier layer are located between at least metal line on the second layer insulating and on the second layer insulating of filling.Tool
Body, referring to Fig. 8, as shown in figure 8, the first barrier layer 181 be located at the second layer insulating 160 and third layer insulating 180 it
Between, and fill between the 4th metal line 241, fifth metal wiring 242 and the 6th metal line 250.Implement in the present invention one
In example, the first barrier layer 181 is insulating layer.Further, step S8 further includes step S81, before forming multiple vias
The second barrier layer and the 4th insulating layer are formed, wherein the second barrier layer is between third insulating layer and the 4th insulating layer, and
Between multiple vias are filled on two barrier layers, between the 4th insulating layer fills at least metal line on third layer insulating,
And at least metal line on overlays third layer insulating layer.Specifically, referring to Fig. 8, as shown in figure 8, the second barrier layer
191 between third insulating layer 180 and the 4th insulating layer 190, and the first via 271, the second mistake are filled in the second barrier layer 191
Between hole 272, third via 273 and the 4th via 274, the 4th insulating layer 190 fills the 7th metal line 341, the 8th metal
Between wiring 342 and the 9th metal line 350, and cover the 7th metal line 341, the 8th metal line 342 and the 9th metal
Wiring 350.
It is, of course, also possible to include the metal line of more layers passive device, on technique and third layer insulating 180
Metal line is identical, and details are not described herein；Its connection relation on the second layer insulating 160 metal line and third layer it is exhausted
The connection relation between metal line on edge layer 180 is identical, and details are not described herein.
In an embodiment of the present invention, a kind of integrated circuit structure is also provided.Specifically, referring to Fig. 8, as shown in figure 8,
The integrated circuit structure includes：
Substrate 110 and the first layer insulating 120, the first layer insulating 120 are located on substrate 110.
An at least metal line (such as the first metal line 141 and the second metal line of transistor 130 and passive device
142 and third metal line 150), an at least metal line for transistor 130 and passive device is located at the first layer insulating 120
On and surrounded by the second layer insulating 160.As shown in figure 8, the second layer insulating 160 is located on the first layer insulating 120, fill out
It fills between transistor 130, the first metal line 141, the second metal line 142 and third metal line 150, and covering transistor
130, the first metal line 141, the second metal line 142 and third metal line 150, namely surround transistor 130 and first
An at least metal line on layer insulating 120.
Multiple connecting holes, multiple connecting holes are located in the second layer insulating 160, and one end connection first of multiple connecting holes
An at least metal line on layer insulating 120.As shown in figure 8, the first connecting hole 171, the second connecting hole 172, third connect
Hole 173 and the 4th connecting hole 174 are connect, wherein one end of the first connecting hole 171 connects the first metal line 141；Second connecting hole
172 one end connects the second metal line 142；One end of one end connection third metal line 150 of third connecting hole 173；The
The other end of one end connection third metal line 150 of four connecting holes 174；
An at least metal line and third layer insulating 180 for passive device on the second layer insulating 160, the
Three-layer insulated layer 180 surrounds at least metal line on the second layer insulating 160, and the other end connection of multiple connecting holes
An at least metal line on second layer insulating 160, to form an at least passive device.As shown in figure 8, third layer insulate
Layer 180 is located on the second layer insulating 160, the 4th metal line 241, fifth metal wiring 242 and the 6th metal line 250
On the second layer insulating 160, third layer insulating 180 fills the 4th metal line 241, fifth metal wiring 242 and the
Between six metal lines 250, and the 4th metal line 241, fifth metal wiring 242 and the 6th metal line 250 are covered, namely
Surround at least metal line on the second layer insulating 160.The other end of first connecting hole 171 connects the 4th metal line
241, wherein the other end connection fifth metal wiring 242 of the second connecting hole 172, the wherein other end of third connecting hole 173 connects
One end of the 6th metal line 250 is connect, wherein the other end of the 4th connecting hole 174 connects the other end of the 6th metal line 250,
So that the first metal line 141 is electrically connected and constitutes the first electrode of capacitance, the second metal line with the 4th metal line 241
142 second electrodes for being electrically connected to form capacitance with fifth metal wiring 242, third metal line 150 and the 6th metal line 250
Be electrically connected to form an inductance.
It is thusly-formed the integrated morphology of active member and passive device, and includes passive in the metal wiring layer of active member
The metal line of element, therefore improve the performance of passive device (as inductively or capacitively) or increase the capacitance of capacitance.
Further, further include multiple vias and on the third layer insulating in the integrated circuit structure of the present invention
Passive device an at least metal line, one end of plurality of via connects at least metal on the second layer insulating
Wiring, the other end of multiple vias connect at least metal line on third layer insulating, to form at least one passive member
Part.Specifically, referring to Fig. 8, as shown in figure 8, one end of the first via 271 connects the 4th metal line 241；Second via
272 one end connection fifth metal wiring 242；One end of third via 273 connects one end of the 6th metal line 250；4th
One end of via 274 connects the other end of the 6th metal line 250.The 7th metal is formed on third layer insulating 180
The 341, the 8th metal line 342 and the 9th metal line 350 are connected up, the other end of the first via 271 connects the 7th metal line
341, the other end of the second via 272 connects the 8th metal line 342, and the other end of third via 273 connects the 9th hardware cloth
One end of line 350, the other end of the 4th via 274 connects the other end of the 9th metal line 350, so that the first metal line
141, the 4th metal line 241 is electrically connected and constitutes the first electrode of capacitance, the second metal line with the 7th metal line 341
142, fifth metal wiring 242 and the 8th metal line 342 are electrically connected to form the second electrode of capacitance, third metal line 150,
6th metal line 250 and the 9th metal line 350 are electrically connected to form an inductance.
By being formed simultaneously the metal line and passive device of active member (such as transistor) on a layer insulating
Metal line, and by connecting hole by the passive device on the metal line of passive device on this layer and other insulating layers
Metal line connects, and not only constitutes the integrated morphology of active member and passive device, and in the premise for not increasing technological process
Under so that passive device (as inductively or capacitively) is increased one layer of metal line, therefore improve passive device (as inductively or capacitively)
Performance or increase capacitance capacitance.
In the description of the present invention, it should be noted that term "upper" and " on " instruction orientation or positional relationship be
It is based on the orientation or positional relationship shown in the drawings, is merely for convenience of description of the present invention and simplification of the description, rather than instruction or dark
Show that signified device or element must have a particular orientation, with specific azimuth configuration and operation, therefore should not be understood as pair
The limitation of the present invention.
In conclusion by be formed simultaneously on a layer insulating active member (such as transistor) metal line and by
The metal line of dynamic element (as inductively or capacitively), and by connecting hole by the metal line of passive device on this layer with it is other
The metal line of passive device connects on insulating layer, not only the integrated morphology of composition active member and passive device, and
So that passive device (as inductively or capacitively) is increased one layer of metal line under the premise of not increasing technological process, thus improve by
The performance of dynamic element (as inductively or capacitively) or the capacitance for increasing capacitance.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, it will be understood by those of ordinary skill in the art that：Its according to
So can with technical scheme described in the above embodiments is modified, either to which part or all technical features into
Row equivalent replacement；And these modifications or replacements, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (12)
1. a kind of manufacturing method of integrated circuit, which is characterized in that including：
Step S1 provides a wafer, and wafer includes substrate and the first layer insulating, wherein the first layer insulating layer is positioned at described
On substrate；
Step S2 forms drain electrode and the source electrode of a transistor on first layer insulating；
Step S3 forms the grid of the transistor and an at least hardware cloth for passive device on first layer insulating
Line；
Step S4, forms the second layer insulating, and second layer insulating surrounds on the transistor and the first layer insulating
An at least metal line；
Step S5 forms multiple connecting holes in second layer insulating, wherein one end connection the of the multiple connecting hole
An at least metal line on one layer insulating；And
Step S6 forms an at least metal line for passive device, and the multiple connection on second layer insulating
The other end in hole connects at least metal line on the second layer insulating, to form an at least passive device.
2. the manufacturing method of integrated circuit according to claim 1, which is characterized in that further include：
Step S7, forms third layer insulating, and the third layer insulating surrounds described at least one on the second layer insulating
Metal line；
Step S8, forms multiple vias, and one end of the multiple via connects at least gold medal on the second layer insulating
Belong to wiring；
Step S9 forms an at least metal line for passive device, and the multiple via on the third layer insulating
The other end connection third layer insulating on an at least metal line, to form an at least passive device.
3. the manufacturing method of integrated circuit according to claim 2, which is characterized in that step S7 further includes step S71,
One first barrier layer is formed before forming the third layer insulating, first barrier layer is located on second layer insulating
And between at least metal line on the second layer insulating of filling.
4. the manufacturing method of integrated circuit according to claim 2, which is characterized in that step S8 further includes step S81,
The second barrier layer and the 4th insulating layer are formed before forming the multiple via, wherein second barrier layer is located at the third
Between insulating layer and the 4th insulating layer, and between the multiple via of second barrier layer filling, the 4th insulation
Layer filling third layer insulating on an at least metal line between, and on overlays third layer insulating layer it is described extremely
A few metal line.
5. the manufacturing method of integrated circuit according to claim 1, which is characterized in that described on the first layer insulating
An at least metal line includes one first metal line and one second metal line, wherein first metal line and described the
Two metal lines constitute two electrodes of a capacitance.
6. the manufacturing method of integrated circuit according to claim 1, which is characterized in that described on the first layer insulating
An at least metal line includes a third metal line, and the third metal line is an inductor winding.
7. the manufacturing method of integrated circuit according to claim 1, which is characterized in that described on the first layer insulating
An at least metal line includes one first metal line, one second metal line and a third metal line, the multiple connection
Hole includes one first connecting hole, one second connecting hole, a third connecting hole and one the 4th connecting hole, wherein first connecting hole
One end connect first metal line, one end of second connecting hole connects second metal line, the third
One end of connecting hole connects one end of the third metal line, and one end of the 4th connecting hole connects the third hardware cloth
The other end of line, at least metal line on the second layer insulating include one the 4th metal line, a fifth metal
The other end of wiring and one the 6th metal line, first connecting hole connects the 4th metal line, second connection
The other end in hole connects the fifth metal wiring, and the other end of the third connecting hole connects the one of the 6th metal line
End, the other end of the 4th connecting hole connects the other end of the 6th metal line so that first metal line with
4th metal line is electrically connected and constitutes the first electrode of capacitance, and second metal line is connected up with the fifth metal
Be electrically connected to form the second electrode of capacitance, and the third metal line and the 6th metal line are electrically connected to form an inductance.
8. the manufacturing method of integrated circuit according to claim 2, which is characterized in that described on the first layer insulating
An at least metal line includes one first metal line, one second metal line and a third metal line, the multiple connection
Hole includes one first connecting hole, one second connecting hole, a third connecting hole and one the 4th connecting hole, wherein first connecting hole
One end connect first metal line, one end of second connecting hole connects second metal line, the third
One end of connecting hole connects one end of the third metal line, and one end of the 4th connecting hole connects the third hardware cloth
The other end of line, at least metal line on the second layer insulating include one the 4th metal line, a fifth metal
The other end of wiring and one the 6th metal line, first connecting hole connects the 4th metal line, second connection
The other end in hole connects the fifth metal wiring, and the other end of the third connecting hole connects the one of the 6th metal line
The other end at end, the 4th connecting hole connects the other end of the 6th metal line, and the multiple via includes one first
One end of via, one second via, a third via and one the 4th via, first via connects the 4th hardware cloth
One end of line, second via connects the fifth metal wiring, and one end of the third via connects the 6th metal
One end of wiring, one end of the 4th via connect the other end of the 6th metal line, on third layer insulating
An at least metal line include one the 7th metal line, one the 8th metal line and one the 9th metal line, described first
The other end of via connects the 7th metal line, and the other end of second via connects the 8th metal line, institute
The other end for stating third via connects one end of the 9th metal line, the other end connection the described 9th of the 4th via
The other end of metal line, so that first metal line, the 4th metal line are electrically connected with the 7th metal line
Connect and constitute the first electrode of capacitance, second metal line, fifth metal wiring and the 8th metal line electricity
Connect and compose the second electrode of capacitance, the third metal line, the 6th metal line and the 9th metal line electricity
Connect and compose an inductance.
9. a kind of integrated circuit structure, which is characterized in that including：
One substrate and one first layer insulating, first layer insulating are located at the substrate；
An at least hardware cloth for an at least metal line for one transistor and passive device, the transistor and passive device
Line is located on first layer insulating and is surrounded by one second layer insulating；
Multiple connecting holes, the multiple connecting hole are located in second layer insulating, and one end of the multiple connecting hole connects
Connect at least metal line on the first layer insulating；And
An at least metal line and a third layer insulating for passive device on second layer insulating, described
Three-layer insulated layer surrounds at least metal line on the second layer insulating, and the other end of the multiple connecting hole connects
At least metal line on the second layer insulating is connect, to form an at least passive device.
10. integrated circuit structure according to claim 9, which is characterized in that further include multiple vias and positioned at described the
An at least metal line for passive device on three-layer insulated layer, wherein one end connection second layer insulation of the multiple via
Layer on an at least metal line, the multiple via the other end connection third layer insulating on it is described at least
One metal line, to form an at least passive device.
11. integrated circuit structure according to claim 9, which is characterized in that on the first layer insulating it is described at least
One metal line includes one first metal line, one second metal line and a third metal line, the multiple connecting hole packet
One first connecting hole, one second connecting hole, a third connecting hole and one the 4th connecting hole are included, wherein the one of first connecting hole
End connects first metal line, and one end of second connecting hole connects second metal line, the third connection
The one end in hole connects one end of the third metal line, and one end of the 4th connecting hole connects the third metal line
The other end, at least metal line on the second layer insulating include that one the 4th metal line, a fifth metal connect up
And one the 6th metal line, the other end of first connecting hole connect the 4th metal line, second connecting hole
The other end connects the fifth metal wiring, and the other end of the third connecting hole connects one end of the 6th metal line,
The other end of 4th connecting hole connects the other end of the 6th metal line so that first metal line with it is described
4th metal line is electrically connected and constitutes the first electrode of capacitance, and second metal line is electrically connected with fifth metal wiring
Connect the second electrode for constituting capacitance, the third metal line and the 6th metal line are electrically connected to form an inductance.
12. integrated circuit structure according to claim 10, which is characterized in that on the first layer insulating it is described at least
One metal line includes one first metal line, one second metal line and a third metal line, the multiple connecting hole packet
One first connecting hole, one second connecting hole, a third connecting hole and one the 4th connecting hole are included, wherein the one of first connecting hole
End connects first metal line, and one end of second connecting hole connects second metal line, the third connection
The one end in hole connects one end of the third metal line, and one end of the 4th connecting hole connects the third metal line
The other end, at least metal line on the second layer insulating include that one the 4th metal line, a fifth metal connect up
And one the 6th metal line, the other end of first connecting hole connect the 4th metal line, second connecting hole
The other end connects the fifth metal wiring, and the other end of the third connecting hole connects one end of the 6th metal line,
The other end of 4th connecting hole connects the other end of the 6th metal line, and the multiple via includes one first mistake
One end of hole, one second via, a third via and one the 4th via, first via connects the 4th metal line,
One end of second via connects the fifth metal wiring, and one end of the third via connects the 6th metal line
One end, one end of the 4th via connects the other end of the 6th metal line, described on third layer insulating
An at least metal line includes one the 7th metal line, one the 8th metal line and one the 9th metal line, first via
The other end connect the 7th metal line, the other end of second via connects the 8th metal line, described the
The other end of three vias connects one end of the 9th metal line, and the other end of the 4th via connects the 9th metal
The other end of wiring so that first metal line, the 4th metal line be electrically connected with the 7th metal line and
The first electrode of capacitance is constituted, second metal line, fifth metal wiring are electrically connected with the 8th metal line
The second electrode of capacitance is constituted, the third metal line, the 6th metal line are electrically connected with the 9th metal line
Constitute an inductance.
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| EP3664144A3 (en) * | 2018-12-04 | 2020-08-26 | LG Display Co., Ltd. | Electroluminescent display apparatus and display apparatus |
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