CN115241158A - High capacitance density semiconductor capacitor and method of making the same - Google Patents

Abstract

The invention relates to the field of semiconductor capacitors, and discloses a semiconductor capacitor with high capacitance density and a preparation method thereof, wherein the capacitor comprises a substrate, conducting layers and dielectric layers, wherein the conducting layers and the dielectric layers are sequentially and alternately stacked on the substrate, the conducting layers comprise odd layers and even layers, and the capacitor is respectively provided with odd layer connecting holes and even layer connecting holes which penetrate through the conducting layers and the dielectric layers; the odd-layer connecting holes are filled with conductive materials and are used for being electrically connected with the odd-layer through the conductive materials and being in insulation connection with the even-layer; and the even layer connecting holes are filled with conductive materials and are used for being electrically connected with the even layer and being in insulation connection with the odd layer through the conductive materials. Through the multilayer stack structure and the connection mode of the capacitor electrode, the effective area of the electrode is increased, the capacitance density is improved, the service life of the capacitor is prolonged, and the application in the fields of power electronics, high voltage and the like is realized.

Description

High capacitance density semiconductor capacitor and method of making the same

Technical Field

The invention relates to the technology of semiconductor capacitors, in particular to a semiconductor capacitor with high capacitance density and a preparation method thereof.

Background

Integrated circuit technology allows many types of devices to be formed on a silicon die, and as semiconductor integrated circuit fabrication technology continues to advance, performance is increasing, and as device miniaturization and miniaturization progress, it is desirable to provide as many devices as possible within a certain area to achieve higher integration performance. The most common devices are transistors, diodes, resistors or capacitors. A capacitor is an element for storing charge in a semiconductor device. The capacitor includes two conductive plates separated by an insulating material. Capacitors are used in applications such as electronic filters, analog-to-digital converters, memory devices, control applications, and many other types of semiconductor device applications.

The capacitor is used as an important component unit in an integrated circuit and is widely applied to chips such as a memory, microwaves, radio frequencies, smart cards, high voltage and filtering chips and the like. In order to obtain higher capacitance density, three methods are generally adopted at present, namely, a dielectric material with higher dielectric constant is adopted to improve the capacitance density; however, there is limited space to replace high-k materials because there are fewer dielectric materials available and that can be combined with existing processes. Secondly, according to the physical capacitance calculation principle, the capacitance can be increased by reducing the distance between the two polar plates; in the specific capacitor manufacturing process, the thickness of the dielectric layer is reduced, but the reduction of the thickness of the dielectric layer causes the electric field intensity borne by the dielectric material to be correspondingly increased under the same working voltage, and because the breakdown-resistant degree of the dielectric material is certain, in order to obtain a reliable capacitor device and reduce the risk of breakdown damage, the improvement of the capacitance density by reducing the thickness of the dielectric layer is limited. Thirdly, under the structure of the single-layer capacitor, the area of the capacitor plate in unit area is increased by utilizing the fluctuated appearance or the hemispherical grains, but the method has limited improvement range and great difficulty in process.

Therefore, a simple method capable of effectively increasing the capacitance density of the capacitor is lacking in the prior art.

Disclosure of Invention

The invention aims to overcome the problem that the prior art lacks a simple method capable of effectively improving the capacitance density of a capacitor, and provides a semiconductor capacitor and a preparation method thereof.

In order to achieve the above object, an aspect of the present invention provides a method for manufacturing a semiconductor capacitor with high capacitance density, comprising the steps of:

s1, depositing two conductive layers and a dielectric layer on a substrate, wherein the dielectric layer is positioned between the two conductive layers;

s2, etching a first groove on the conducting layer positioned on the outer layer, and depositing a dielectric layer on the first groove and the conducting layer positioned on the outer layer;

s3, depositing a conductive layer on the dielectric layer positioned on the outer layer, etching a second groove on the conductive layer, wherein the second groove is staggered with the first groove, and then depositing a dielectric layer on the second groove and the conductive layer;

s4, repeating the steps S2 and S3 for a plurality of times in sequence to obtain a plurality of first grooves and a plurality of second grooves, wherein the plurality of first grooves are arranged on the same straight line, and the plurality of second grooves are arranged on the same straight line;

s5, etching odd connection holes in the center position corresponding to the first groove, wherein the odd connection holes penetrate through the outermost dielectric layer to the innermost dielectric layer; etching even-numbered connecting holes at the center position corresponding to the second groove, wherein the even-numbered connecting holes penetrate through from the outermost dielectric layer to the dielectric layer on the upper layer of the innermost dielectric layer;

and S6, filling conductive materials in the odd-numbered layer connecting holes and the even-numbered layer connecting holes respectively.

The invention provides a semiconductor capacitor with high capacitance density, which is prepared by the method and comprises a substrate, a conducting layer and a dielectric layer, wherein the conducting layer and the dielectric layer are sequentially and alternately stacked on the substrate, the conducting layer comprises odd layers and even layers, and the capacitor is respectively provided with odd layer connecting holes and even layer connecting holes which penetrate through the conducting layer and the dielectric layer;

the odd layer connecting holes are filled with conductive materials and are used for being electrically connected with the odd layers through the conductive materials and being in insulation connection with the even layers;

and the even layer connecting holes are filled with conductive materials and are used for being electrically connected with the even layer and being in insulation connection with the odd layer through the conductive materials.

Through the technical scheme, the conducting layers and the dielectric layers are stacked to form the groove structure connected with the internal multilayer electrodes, the effective area of the electrodes is increased, the capacitance density is improved, the service life of the capacitor is prolonged, the capacitor holes with high depth-to-width ratio do not need to be etched on the substrate in the preparation process, and the capacitor holes with high depth-to-width ratio do not need to be filled, so that the process difficulty and the process cost are greatly reduced.

Drawings

FIG. 1 is a schematic diagram of the structure of the conductive and dielectric layers of the capacitor of the present invention;

FIG. 2 is a schematic diagram of the first trench of the capacitor of the present invention;

FIG. 3 is a schematic diagram of the structure of a second trench of the capacitor of the present invention;

FIG. 4 is a structural diagram of the odd-numbered layer connecting holes and the even-numbered layer connecting holes of the capacitor of the present invention;

FIG. 5 is a schematic view of a partial structure of the capacitor of the present invention;

FIG. 6 is a schematic diagram of the structure of the odd-numbered layer conductive blocks and the even-numbered layer conductive blocks of the capacitor of the present invention;

fig. 7 is a schematic diagram of the structure of the capacitor of the present invention.

Description of the reference numerals

1. A substrate; 2. a first conductive layer; 3. a first dielectric layer; 4. a second conductive layer; 5. a first groove; 6. a second dielectric layer; 7. a third conductive layer; 8. a second groove; 9. odd layers of connection holes; 10. connecting holes of even number layers; 11. a fifth dielectric layer; 12. odd-numbered layers of conductive blocks; 13. an even number of layers of conductive blocks; 14. an insulating isolation layer; 15. a first metal outer electrode; 16. a second metal external electrode.

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are given by way of illustration and explanation only, not limitation.

A method for preparing a semiconductor capacitor with high capacitance density comprises the following steps:

s1, depositing two conductive layers and a dielectric layer on a substrate 1, wherein the dielectric layer is positioned between the two conductive layers:

illustratively, as shown in fig. 1, a first conductive layer 2 is formed on a substrate 1 by a method such as sputtering, chemical vapor deposition, etc., a first dielectric layer 3 is formed by a chemical vapor deposition method, and a second conductive layer 4 is formed by a method such as sputtering, chemical vapor deposition, etc. The substrate 1 may be a semiconductor material substrate or an insulating substrate, and an undoped silicon substrate is exemplarily selected; the resistivity of the conductive layer 2 is less than 10 Ω × m, and the conductive layer 2 of this embodiment is made of polysilicon by way of example. The thickness of the conductive layer 2 is between 15nm and 2 μm, and illustratively, the thickness may be 20nm, 80nm, 100nm or 1 μm; in this embodiment, the dielectric layer 3 is made of silicon dioxide. The thickness of the dielectric layer 3 is between 20nm and 3 μm, preferably, the thickness of the dielectric layer 3 is 30nm, 80nm, 1 μm or 2 μm, and the thickness of the dielectric layer 3 depends on the requirement of the voltage-resistant design;

s2, etching a first groove 5 on the conducting layer positioned on the outer layer, and depositing a dielectric layer on the first groove 5 and the conducting layer positioned on the outer layer;

illustratively, as shown in fig. 2, after cleaning the second conductive layer 4 (i.e. the conductive layer on the outer layer) by using sulfuric acid and hydrogen peroxide, selectively masking and photoetching the second conductive layer 4 to obtain a first trench 5, wherein the etching width depends on the voltage-resistant grade of the capacitor, and preferably, the etching width is 6-8 μm. A dielectric layer is then deposited over the first trench 5 and the conductive layer on the outer layer, specifically: depositing a material for filling the dielectric layer in the first trench 5 to serve as an insulation isolation region of the second conductive layer 4, and depositing a second dielectric layer 6 on the second conductive layer 4, as shown in fig. 3, wherein the materials of the first trench 5 and the second dielectric layer 6 may be the same or different;

s3, depositing a conductive layer on the dielectric layer positioned on the outer layer, etching a second groove 8 on the conductive layer, wherein the second groove 8 is arranged in a staggered mode with the first groove 5, and then depositing a dielectric layer on the second groove 8 and the conductive layer:

illustratively, as shown in fig. 3, a third conductive layer 7 is deposited on the second dielectric layer 6 (i.e. the dielectric layer located at the outer layer as described above), a second trench 8 is etched in the third conductive layer 7, the second trench 8 is located at the right side of the first trench 5, the etching width depends on the voltage-resistant class of the capacitor, and preferably, the etching width is 6-15 μm. Then, depositing a material for filling the dielectric layer in the second trench 8 as an insulation isolation region of the third conductive layer 7, and depositing a third dielectric layer on the third conductive layer 7, wherein the materials of the second trench 8 and the third dielectric layer may be the same or different;

s4, repeating the steps S2 and S3 for a plurality of times in sequence to obtain a plurality of the first grooves 5 and the second grooves 8, wherein the first grooves 5 are arranged on the same straight line, and the second grooves 8 are arranged on the same straight line:

exemplarily, a structure with 5 conducting layers and 5 dielectric layers stacked alternately is finally obtained, wherein the second conducting layer and the fourth conducting layer are respectively provided with a first groove 5, two first grooves 5 are arranged in an aligned manner, the third conducting layer and the fifth conducting layer are respectively provided with a second groove 8, and two second grooves 8 are arranged in an aligned manner;

s5, etching an odd layer connecting hole 9 at the center position corresponding to the first groove 5, wherein the odd layer connecting hole 9 penetrates from an outermost layer (namely, a fifth layer shown in figure 4) dielectric layer to an innermost layer (namely, a first layer shown in figure 4) dielectric layer; etching an even-numbered layer of connection holes 10 at the center position corresponding to the second groove 8, wherein the even-numbered layer of connection holes 10 penetrate from the dielectric layer at the outermost layer (i.e. the fifth layer shown in fig. 4) to the dielectric layer at the layer above the innermost layer (i.e. the second layer shown in fig. 4), exemplarily shown in fig. 4; the first groove 5 is wider than the odd-layer connecting hole 9 by 4-6 μm, namely the edge of the first groove 5 is 2-3 μm away from the edge of the odd-layer connecting hole 9, and the second groove 8 is wider than the even-layer connecting hole 10 by 4-6 μm, namely the edge of the second groove 8 is 2-3 μm away from the edge of the even-layer connecting hole 10, wherein the specific range is not limited to the value and is adjusted according to the requirement of voltage resistance;

s6, filling conductive materials in the odd layer connecting holes 9 and the even layer connecting holes 10 respectively;

illustratively, as shown in fig. 6, the odd-numbered layer connection holes 9 and the even-numbered connection holes enable the extraction of the odd-numbered conductive layers (first, third, and fifth conductive layers) and the even-numbered conductive layers (second and fourth conductive layers) in the capacitor by filling the conductive material.

Further, a method for manufacturing a semiconductor capacitor with high capacitance density further comprises:

s7, respectively filling an odd layer conductive block 12 and an even layer conductive block 13 on the outermost dielectric layer, wherein the odd layer conductive block 12 is in contact connection with the conductive material of the odd layer connecting hole 9, and the even layer conductive block 13 is in contact connection with the conductive material of the even layer connecting hole 10:

exemplarily, as shown in fig. 5, a conductive layer is deposited on the fifth dielectric layer 11, and the excess conductive material on the surface is etched to form an odd conductive block 12 and an even conductive block 13 which are separated from each other, so that the odd conductive block 12 and the even conductive block 13 are electrically separated from each other, as shown in fig. 6;

s8, depositing an insulating isolation layer 14 on one side of the capacitor far away from the substrate 1: an insulating isolation layer 14 is obtained by depositing silicon dioxide by CVD, the insulating isolation layer 14 covers the fifth dielectric layer 11, the odd-numbered conductive blocks 12 and the even-numbered conductive blocks 13 at the same time,

selectively etching the insulating isolation layer 14 to expose the odd layer conductive blocks 12 and the even layer conductive blocks 13; as shown in fig. 7, the odd-numbered conductive blocks 12 and the even-numbered conductive upper surfaces are partially exposed,

respectively sputtering metal layers on the exposed parts of the odd-layer conductive block 12 and the even-layer conductive block 13 to form a first metal external electrode 15 and a second metal external electrode 16; the first metal external electrode 15 and the second metal external electrode 16 may be made of Al-Si-Cu alloy, or may be made of other metal materials; the first metallic external electrode 15 can be connected equipotentially to the odd-numbered conductive layer, while the second metallic external electrode 16 can be connected equipotentially to the even-numbered conductive layer, thereby leading the capacitor out.

A semiconductor capacitor with high capacitance density is prepared by the method, and as shown in figure 7, the semiconductor capacitor comprises a substrate 1, a conducting layer, a dielectric layer, a first metal outer electrode 15 and a second metal outer electrode 16, wherein the conducting layer and the dielectric layer are sequentially and alternately stacked on the substrate 1, the conducting layer comprises odd layers and even layers, and the capacitor is respectively provided with odd layer connecting holes 9 and even layer connecting holes 10 penetrating through the conducting layer and the dielectric layer; the conductive layer has a resistivity of less than 10 Ω x m and a thickness of 15nm to 2 μm, preferably 20nm to 1 μm; the thickness of the dielectric layer is 20nm-3 μm; a first groove 5 and a second groove 8 penetrating through the conductive layer and the dielectric layer are respectively arranged in the capacitor, the first groove 5 is positioned on the even layer, the middle line of the first groove 5 is superposed with the middle line of the connecting hole 9 of the odd layer, and the width of the first groove is greater than that of the connecting hole of the odd layer; the second groove 8 is positioned on the odd-numbered layer, the middle line of the second groove 8 is superposed with the middle line of the even-numbered layer connecting hole 10, and the width of the second groove is greater than that of the even-numbered layer connecting hole; preferably, the first trench 5 and the second trench 8 are respectively 6 to 8 μm wide, the first trench 5 is 4 to 6 μm wider than the odd-numbered layer connection hole 9, and the second trench 8 is 4 to 6 μm wider than the even-numbered layer connection hole 10; the first metal external electrode 15 is electrically connected with the odd-numbered layers, and the second metal external electrode 16 is electrically connected with the even-numbered layers; the odd layer connecting holes 9 are filled with conductive materials and used for being electrically connected with the odd layers through the conductive materials and being in insulation connection with the even layers; the even layer connection holes 10 are filled with a conductive material, and are used for being electrically connected with the even layers and being in insulation connection with the odd layers through the conductive material.

In summary, the invention forms a plurality of conductive layers alternately distributed on the substrate, and the adjacent conductive layers are separated by the dielectric layer to form the capacitor structure, thereby increasing the density of the silicon capacitor. The capacitor has the advantages of small volume, large capacitance, high reliability (the capacitance value does not change along with voltage and temperature), good temperature characteristic (the capacitance value does not change along with temperature basically), and the like compared with a common ceramic capacitor. On the basis of realizing the high-density capacitor by using a lamination mode, the invention etches the grooves on the odd layers and the even layers and deposits and fills the insulating dielectric layers in the grooves, thereby realizing the extraction of the capacitor lamination capacitor electrode and realizing the insulation and voltage resistance of the odd layers and the even layers so as to expand the application to power electronics.

The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited thereto. Within the scope of the technical idea of the invention, numerous simple modifications can be made to the technical solution of the invention, including any suitable combination of specific features, and in order to avoid unnecessary repetition, the invention will not be described in detail in relation to the various possible combinations. Such simple modifications and combinations should be considered within the scope of the present disclosure as well.

Claims (9)

1. A method for manufacturing a semiconductor capacitor with high capacitance density is characterized by comprising the following steps:

s1, depositing two conductive layers and a dielectric layer on a substrate, wherein the dielectric layer is positioned between the two conductive layers;

s2, etching a first groove on the conducting layer positioned on the outer layer, and depositing a dielectric layer on the first groove and the conducting layer positioned on the outer layer;

s3, depositing a conductive layer on the dielectric layer positioned on the outer layer, etching a second groove on the conductive layer, wherein the second groove is staggered with the first groove, and then depositing a dielectric layer on the second groove and the conductive layer;

s4, repeating the steps S2 and S3 for a plurality of times in sequence to obtain a plurality of first grooves and a plurality of second grooves, wherein the plurality of first grooves are arranged on the same straight line, and the plurality of second grooves are arranged on the same straight line;

s5, etching odd connection holes in the center position corresponding to the first groove, wherein the odd connection holes penetrate through the outermost dielectric layer to the innermost dielectric layer; etching even-numbered connecting holes at the center position corresponding to the second groove, wherein the even-numbered connecting holes penetrate through from the outermost dielectric layer to the dielectric layer on the innermost layer;

and S6, filling conductive materials in the odd-numbered layer connecting holes and the even-numbered layer connecting holes respectively.

2. The method of claim 1, further comprising filling an odd-numbered layer conductive block and an even-numbered layer conductive block on the outermost dielectric layer, respectively, the odd-numbered layer conductive block being in contact connection with the conductive material of the odd-numbered layer connection hole, and the even-numbered layer conductive block being in contact connection with the conductive material of the even-numbered layer connection hole.

3. The method of claim 1 or 2, further comprising:

depositing an insulating isolation layer on one side of the capacitor far away from the substrate;

selectively etching the insulating isolation layer to expose the odd layer conductive blocks and the even layer conductive blocks;

and respectively sputtering metal layers on the exposed parts of the odd-numbered conductive blocks and the even-numbered conductive blocks to form metal outer electrodes.

4. A semiconductor capacitor with high capacitance density, which is prepared by the method of any one of claims 1 to 3, and comprises a substrate, conductive layers and dielectric layers, wherein the conductive layers and the dielectric layers are alternately stacked on the substrate in sequence, the conductive layers comprise odd layers and even layers, and the capacitor is provided with connecting holes of the odd layers and the even layers penetrating through the conductive layers and the dielectric layers respectively;

the odd layer connecting holes are filled with conductive materials and are used for being electrically connected with the odd layers through the conductive materials and being in insulation connection with the even layers;

and the even layer connecting holes are filled with conductive materials and are used for being electrically connected with the even layer through the conductive materials and being in insulated connection with the odd layer.

5. A capacitor according to claim 4, wherein the capacitor has first and second trenches formed therein through the conductive and dielectric layers, respectively,

the first groove is positioned on the even layer, and the central line of the first groove is superposed with the central line of the connecting hole of the odd layer;

the second groove is positioned on the odd-numbered layer, and the central line of the second groove is superposed with the central line of the connecting hole of the even-numbered layer.

6. The capacitor according to claim 5, wherein the first trench and the second trench are respectively 6-15 μm wide, the first trench coincides with a center line of the connection hole of the odd-numbered layer, and the width of the first trench is greater than the width of the connection hole of the odd-numbered layer; the second groove is superposed with the middle line of the even layer connecting hole, and the width of the second groove is larger than that of the even layer connecting hole.

7. A capacitor according to claim 6, wherein the conductive layer has a resistivity of less than 10 Ω m and a thickness of 15nm-2 μm, preferably 20nm-1 μm.

8. A capacitor according to any of claims 4-7, wherein the dielectric layer has a thickness of 20nm-3 μm.

9. The capacitor of claim 8 further comprising first and second external metal electrodes, said first external metal electrode being electrically connected to said odd-numbered layers and said second external metal electrode being electrically connected to said even-numbered layers.

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