CN115588577A - Terminal electrode capacitor and preparation method thereof - Google Patents
Terminal electrode capacitor and preparation method thereof Download PDFInfo
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- CN115588577A CN115588577A CN202211320410.5A CN202211320410A CN115588577A CN 115588577 A CN115588577 A CN 115588577A CN 202211320410 A CN202211320410 A CN 202211320410A CN 115588577 A CN115588577 A CN 115588577A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
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- H01G4/005—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/10—Metal-oxide dielectrics
Abstract
The invention discloses a terminal electrode capacitor and a preparation method thereof, wherein the terminal electrode capacitor comprises: the capacitor comprises a capacitor body, a first metal electrode arranged on the left side of the capacitor body and a second metal electrode arranged on the right side of the capacitor body; the capacitor main body comprises a three-dimensional matrix structure, a first insulating layer deposited on the upper surface of the three-dimensional matrix structure, a capacitor structure deposited on the upper surface of the first insulating layer and a second insulating layer deposited on the upper surface of the capacitor structure; the capacitor structure comprises a plurality of conductive material layers, and a dielectric layer is arranged between every two adjacent conductive material layers; in the multiple layers of conductive material layers, the odd layers of conductive material layers are connected with the first metal electrode, and the even layers of conductive material layers are connected with the second metal electrode; or the even layers of the conductive material layers are connected with the first metal electrodes, and the odd layers of the conductive material layers are connected with the second metal electrodes. The invention can improve the binding force between the metal electrode and the substrate.
Description
Technical Field
The invention relates to the technical field of terminal electrode capacitors, in particular to a terminal electrode capacitor and a preparation method thereof.
Background
In recent years, with the development of microwave communication technology, there has been an increasing demand for compact and lightweight electronic devices, and the communication frequency used has been increasing toward higher frequencies, and thus electronic components such as capacitors have been increasingly used in high-frequency applications. In order to improve the capacitance density of the capacitor without increasing the size, the comparative area of the electrode can be increased by etching the substrate, so that the capacitance is increased, but the bonding force between the metal electrode and the ceramic substrate of the optimized traditional chip capacitor is poor.
Disclosure of Invention
The invention aims to provide a terminal electrode capacitor and a preparation method thereof, which can improve the bonding force between a metal electrode and a substrate.
In order to achieve the purpose, the invention provides the following scheme:
the invention provides a terminal electrode capacitor, comprising: a capacitor body, a first metal electrode disposed on a left side of the capacitor body, and a second metal electrode disposed on a right side of the capacitor body;
the capacitor body comprises a three-dimensional matrix structure, a first insulating layer deposited on the upper surface of the three-dimensional matrix structure, a capacitor structure deposited on the upper surface of the first insulating layer, and a second insulating layer deposited on the upper surface of the capacitor structure;
the capacitor structure comprises a plurality of conductive material layers, and a dielectric layer is arranged between every two adjacent conductive material layers;
in the multiple layers of conductive material layers, the conductive material layers of odd layers are connected with the first metal electrode, and the conductive material layers of even layers are connected with the second metal electrode; or, in the multiple layers of conductive material layers, even layers of conductive material layers are connected with the first metal electrode, and odd layers of conductive material layers are connected with the second metal electrode.
Optionally, the three-dimensional matrix structure is a grooved three-dimensional matrix structure, a holed three-dimensional matrix structure, or a spiral grooved three-dimensional matrix structure.
Optionally, the three-dimensional substrate structure is formed by etching a substrate; the three-dimensional base structure is sequentially divided into a left substrate area, a three-dimensional structure area and a right substrate area from left to right.
Optionally, in the multiple layers of conductive material layers, when the odd layers of conductive material layers are connected to the first metal electrode and the even layers of conductive material layers are connected to the second metal electrode, the odd layers of conductive material layers cover the first region, and the even layers of conductive material layers cover the second region; or, in the multiple layers of conductive material layers, when the even layers of conductive material layers are connected with the first metal electrode and the odd layers of conductive material layers are connected with the second metal electrode, the odd layers of conductive material layers cover the second area, and the even layers of conductive material layers cover the first area;
the first area is an area formed by a left substrate area, a three-dimensional structure area and a part of a right substrate area; the second area is an area formed by a part of the left substrate area, the three-dimensional structure area and the right substrate area; wherein the partial left substrate region is a region connected with the three-dimensional structure region; the partial right substrate region is a region connected to the three-dimensional structure region.
Optionally, the thickness of the first insulating layer and the thickness of the second insulating layer are both 20nm; the thickness of the dielectric layer is 20nm; the thickness of the conductive material layer is 50nm.
Optionally, the material of the first metal electrode and the material of the second metal electrode are the same; the first metal electrode is made of one or more metal materials of Ag, pd, cu, ni, au, al and Cr.
Optionally, the material of the first insulating layer is one or more insulating materials of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide and hafnium oxide; the second insulating layer is made of one or more insulating materials of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide and hafnium oxide; the dielectric layer is made of one or more insulating materials of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide and hafnium oxide.
The invention also provides a preparation method of the end electrode capacitor, which comprises the following steps:
processing the upper surface of the substrate by adopting an etching process to obtain a three-dimensional matrix structure;
depositing a first insulating layer on an upper surface of the three-dimensional base structure;
depositing a capacitor structure on an upper surface of the first insulating layer;
depositing a second insulating layer on the upper surface of the capacitor structure to obtain a capacitor main body;
mounting a first metal electrode on the left side of the capacitor body, and mounting a second metal electrode on the right side of the capacitor body;
the capacitor structure comprises a plurality of conductive material layers, and a dielectric layer is arranged between every two adjacent conductive material layers; in the multiple layers of conductive material layers, the odd layers of conductive material layers are connected with the first metal electrode, and the even layers of conductive material layers are connected with the second metal electrode; or, in the multiple layers of conductive material layers, even layers of conductive material layers are connected with the first metal electrode, and odd layers of conductive material layers are connected with the second metal electrode.
Optionally, the three-dimensional base structure is sequentially divided into a left substrate area, a three-dimensional structure area and a right substrate area from left to right; depositing a capacitor structure on the upper surface of the first insulating layer specifically comprises:
depositing a first initial conductive material layer on the upper surface of the first insulating layer, and etching the right area of the first initial conductive material layer by adopting a conductive material etching process to form a first conductive material layer; the first conductive material layer can cover the first area;
depositing a first dielectric layer on the upper surface of the first conductive material layer; the first dielectric layer can cover the third area;
depositing a second initial conductive material layer on the upper surface of the first dielectric layer, and etching the left area of the second initial conductive material layer by adopting a conductive material etching process to form a second conductive material layer; the second layer of conductive material can cover the second region;
analogizing in sequence until the number of layers of the conductive material layers reaches a target value to form a capacitor structure;
the first region is a region formed by a left substrate region, a three-dimensional structure region and a part of a right substrate region; the second area is an area formed by a part of the left substrate area, the three-dimensional structure area and the right substrate area; the third area is an area formed by a left substrate area, a three-dimensional structure area and a right substrate area; the partial left substrate region is a region connected with the three-dimensional structure region; the part of the right substrate region is a region connected with the three-dimensional structure region.
Optionally, the three-dimensional base structure is sequentially divided into a left substrate area, a three-dimensional structure area and a right substrate area from left to right; depositing a capacitor structure on the upper surface of the first insulating layer specifically includes:
depositing a first initial conductive material layer on the upper surface of the first insulating layer, and etching the left area of the first initial conductive material layer by adopting a conductive material etching process to form a first conductive material layer; the first layer of conductive material can cover the second region;
depositing a first dielectric layer on the upper surface of the first conductive material layer; the first dielectric layer can cover the third area;
depositing a second initial conductive material layer on the upper surface of the first dielectric layer, and etching the right area of the second initial conductive material layer by adopting a conductive material etching process to form a second conductive material layer; the second conductive material layer can cover the first region;
repeating the steps until the number of the conductive material layers reaches a target value to form a capacitor structure;
the first region is a region formed by a left substrate region, a three-dimensional structure region and a part of a right substrate region; the second area is an area formed by a part of the left substrate area, the three-dimensional structure area and the right substrate area; the third area is an area formed by a left substrate area, a three-dimensional structure area and a right substrate area; the part of the left substrate region is a region connected with the three-dimensional structure region; the partial right substrate region is a region connected to the three-dimensional structure region.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention applies semiconductor materials and technology to electronic components, can optimize the problems of poor bonding force between the metal electrode and the ceramic substrate of the traditional chip capacitor and the like, realizes the preparation of the terminal electrode capacitor with high quality and low loss, and improves the reliability and the stability of the capacitor.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic side cross-sectional view of an end electrode capacitor according to the present invention;
FIG. 2 is a schematic top view of a cell structure end electrode capacitor according to the present invention;
FIG. 3 is a schematic top view of an end electrode capacitor with an aperture structure according to the present invention;
FIG. 4 is a schematic top view of an end electrode capacitor with a spiral slot structure according to the present invention;
FIG. 5 is a schematic side cross-sectional view of a silicon substrate of the present invention;
FIG. 6 is a schematic side cross-sectional view of a three-dimensional slotted structure according to the present invention;
FIG. 7 is a schematic side cross-sectional view of the present invention after a first silicon nitride insulating layer is deposited on the trench three-dimensional structure;
FIG. 8 is a schematic side cross-sectional view of the present invention after depositing a first layer of polysilicon conductive material over the trench three-dimensional structure;
FIG. 9 is a schematic top view of the right side region of the first layer of polysilicon conductive material in accordance with the present invention;
FIG. 10 is a schematic side cross-sectional view of a trench three-dimensional structure having a first silicon nitride dielectric layer deposited thereon in accordance with the present invention;
FIG. 11 is a schematic cross-sectional side view of the present invention after depositing a second layer of polysilicon conductive material over the trench three-dimensional structure;
FIG. 12 is a schematic side cross-sectional view of the present invention after depositing a second silicon nitride dielectric layer over the trench three-dimensional structure;
FIG. 13 is a schematic cross-sectional side view of the present invention after a third layer of polysilicon conductive material has been deposited over the three-dimensional trenched structure;
FIG. 14 is a schematic cross-sectional side view of the present invention after depositing a third silicon nitride dielectric layer over the trench three-dimensional structure;
FIG. 15 is a schematic side cross-sectional view of the present invention after depositing a fourth layer of polysilicon conductive material over the slotted three-dimensional structure;
FIG. 16 is a schematic side cross-sectional view of a fourth silicon nitride dielectric layer deposited over a trench three-dimensional structure in accordance with the present invention;
fig. 17 is a schematic cross-sectional side view of the present invention after depositing a fifth layer of polysilicon conductive material over the trenched three-dimensional structure;
FIG. 18 is a schematic side cross-sectional view of the present invention after depositing a second insulating layer of silicon nitride on the three dimensional trench structure;
fig. 19 is a schematic side cross-sectional view of a final end electrode capacitor of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description thereof.
Example one
As shown in fig. 1, an embodiment of the present invention provides a terminal electrode capacitor, including: a capacitor body, a first metal electrode 20 disposed on a left side of the capacitor body, and a second metal electrode 30 disposed on a right side of the capacitor body; the capacitor body comprises a three-dimensional matrix structure 10, a first insulating layer deposited on the upper surface of the three-dimensional matrix structure, a capacitor structure deposited on the upper surface of the first insulating layer, and a second insulating layer deposited on the upper surface of the capacitor structure; the capacitor structure comprises a plurality of conductive material layers, and a dielectric layer is arranged between every two adjacent conductive material layers.
In the multiple layers of conductive material layers, the odd layers of conductive material layers are connected with the first metal electrode, and the even layers of conductive material layers are connected with the second metal electrode; or, in the multiple layers of conductive material layers, the even layers of conductive material layers are connected with the first metal electrode, and the odd layers of conductive material layers are connected with the second metal electrode.
As shown in fig. 2 to 4, the three-dimensional matrix structure is a groove-type three-dimensional matrix structure, a hole-type three-dimensional matrix structure, or a spiral groove-type three-dimensional matrix structure. The three-dimensional matrix structure is formed by etching the substrate; the three-dimensional base structure is sequentially divided into a left substrate area, a three-dimensional structure area and a right substrate area from left to right.
One example is as follows: as shown in fig. 1, the capacitor body according to the embodiment of the present invention sequentially includes, from bottom to top: the three-dimensional substrate structure comprises a three-dimensional substrate structure 10, a first insulating layer, a first conductive material layer, a first dielectric layer, a second conductive material layer, a second dielectric layer, a third conductive material layer, a third dielectric layer, a fourth conductive material layer, a fourth dielectric layer, a fifth conductive material layer and a second insulating layer.
The first conductive material layer, the third conductive material layer and the fifth conductive material layer are all connected with the first metal electrode 20, and the second conductive material layer and the fourth conductive material layer are all connected with the second metal electrode 30.
Further, in the multiple layers of conductive material layers, when the odd layers of conductive material layers are connected with the first metal electrode and the even layers of conductive material layers are connected with the second metal electrode, the odd layers of conductive material layers cover the first region and the even layers of conductive material layers cover the second region; or, in the multiple layers of conductive material layers, when the even layers of conductive material layers are connected with the first metal electrode and the odd layers of conductive material layers are connected with the second metal electrode, the odd layers of conductive material layers cover the second region, and the even layers of conductive material layers cover the first region.
The first area is an area formed by a left substrate area, a three-dimensional structure area and a part of a right substrate area; the second area is an area formed by a part of the left substrate area, the three-dimensional structure area and the right substrate area; wherein the partial left substrate region is a region connected with the three-dimensional structure region; the part of the right substrate region is a region connected with the three-dimensional structure region.
One example is: as shown in fig. 1, the first, third and fifth conductive material layers each cover the first region, and the second and fourth conductive material layers each cover the second region.
The thickness of the first insulating layer and the thickness of the second insulating layer are both 20nm; the thickness of the dielectric layer is 20nm; the thickness of the conductive material layer is 50nm. The material of the first metal electrode is the same as that of the second metal electrode; the first metal electrode is made of one or more metal materials of Ag, pd, cu, ni, au, al and Cr. The first insulating layer is made of one or more insulating materials of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide and hafnium oxide; the second insulating layer is made of one or more insulating materials of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide and hafnium oxide; the dielectric layer is made of one or more insulating materials of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide and hafnium oxide.
Example two
The embodiment of the invention also provides a preparation method of the end electrode capacitor, which comprises the following steps:
s1: and processing the upper surface of the substrate by adopting an etching process to obtain the three-dimensional matrix structure.
S1: depositing a first insulating layer on an upper surface of the three-dimensional base structure.
S1: depositing a capacitor structure on an upper surface of the first insulating layer.
S1: and depositing a second insulating layer on the upper surface of the capacitor structure to obtain a capacitor main body.
S1: a first metal electrode is mounted on the left side of the capacitor body, and a second metal electrode is mounted on the right side of the capacitor body.
The capacitor structure comprises a plurality of conductive material layers, and a dielectric layer is arranged between every two adjacent conductive material layers; in the multiple layers of conductive material layers, the odd layers of conductive material layers are connected with the first metal electrode, and the even layers of conductive material layers are connected with the second metal electrode; or, in the multiple layers of conductive material layers, even layers of conductive material layers are connected with the first metal electrode, and odd layers of conductive material layers are connected with the second metal electrode.
The three-dimensional base structure is sequentially divided into a left substrate area, a three-dimensional structure area and a right substrate area from left to right; depositing a capacitor structure on the upper surface of the first insulating layer specifically comprises:
(1) Depositing a first initial conductive material layer on the upper surface of the first insulating layer, and etching the right side area of the first initial conductive material layer by adopting a conductive material etching process to form a first conductive material layer; the first layer of conductive material can cover the first region;
(2) Depositing a first dielectric layer on the upper surface of the first conductive material layer; the first dielectric layer can cover the third area;
(3) Depositing a second initial conductive material layer on the upper surface of the first dielectric layer, and etching the left area of the second initial conductive material layer by adopting a conductive material etching process to form a second conductive material layer; the second layer of conductive material can cover the second region;
(4) Analogizing in sequence until the number of layers of the conductive material layers reaches a target value to form a capacitor structure;
the first region is a region formed by a left substrate region, a three-dimensional structure region and a part of a right substrate region; the second area is an area formed by a part of the left substrate area, the three-dimensional structure area and the right substrate area; the third area is an area formed by a left substrate area, a three-dimensional structure area and a right substrate area; the part of the left substrate region is a region connected with the three-dimensional structure region; the part of the right substrate region is a region connected with the three-dimensional structure region.
Or the three-dimensional base structure is sequentially divided into a left substrate area, a three-dimensional structure area and a right substrate area from left to right; depositing a capacitor structure on the upper surface of the first insulating layer specifically comprises:
(1) Depositing a first initial conductive material layer on the upper surface of the first insulating layer, and etching the left area of the first initial conductive material layer by adopting a conductive material etching process to form a first conductive material layer; the first layer of conductive material can cover the second region;
(2) Depositing a first dielectric layer on the upper surface of the first conductive material layer; the first dielectric layer can cover the third area;
(3) Depositing a second initial conductive material layer on the upper surface of the first dielectric layer, and etching the right area of the second initial conductive material layer by adopting a conductive material etching process to form a second conductive material layer; the second layer of conductive material can cover the first region;
(4) Repeating the steps until the number of the conductive material layers reaches a target value to form a capacitor structure;
the first region is a region formed by a left substrate region, a three-dimensional structure region and a part of a right substrate region; the second area is an area formed by a part of the left substrate area, the three-dimensional structure area and the right substrate area; the third area is an area formed by a left substrate area, a three-dimensional structure area and a right substrate area; the partial left substrate region is a region connected with the three-dimensional structure region; the part of the right substrate region is a region connected with the three-dimensional structure region.
The conductive material etching process in the above scheme may be a dry etching process, a plasma etching process or a wet etching process.
EXAMPLE III
The embodiment of the invention aims to prepare a high-quality, low-loss and high-reliability end electrode capacitor, and the preparation method comprises the following steps.
The method comprises the following steps: selecting a silicon wafer as a material of a silicon substrate 1; wherein the silicon substrate 1 has a side cross-section as shown in fig. 5.
Step two: etching a groove type three-dimensional structure 2 shown in figure 2 on the upper surface of a silicon substrate 1; wherein the side section of the groove-type three-dimensional structure 2 is shown in figure 6.
Step three: depositing a first silicon nitride insulating layer 3 with the thickness of 20nm on the upper surface of the groove type three-dimensional structure 2, wherein the first silicon nitride insulating layer 3 covers the whole silicon substrate 1 and the upper surface of the groove type three-dimensional structure 2; wherein the cross-section of the lateral surface after deposition 3 of the first insulating layer of silicon nitride on the three-dimensional structure 2 of trench type is shown in figure 7.
Step four: depositing a first polysilicon conductive material layer 4 with the thickness of 50nm on the upper surface of the first silicon nitride insulating layer 3, and etching the right side area of the first polysilicon conductive material layer 4 by using a mask etching method to expose the lower first silicon nitride insulating layer 3, so as to prevent the conductive material from contacting with the terminal electrode 14 on the right side; wherein, the cross section of the side surface of the three-dimensional structure 2 after the first polysilicon conductive material layer 4 is deposited is shown in fig. 8, and the right area of the first polysilicon conductive material layer 4 is shown in fig. 9.
Step five: depositing a first silicon nitride dielectric layer 5 with the thickness of 20nm on the upper surface of the first polycrystalline silicon conductive material layer 4 and covering the lower first polycrystalline silicon conductive material layer 4; wherein, the cross section of the side surface after depositing the first silicon nitride dielectric layer 5 on the trench type three-dimensional structure 2 is shown in fig. 10.
Step six: depositing a second polysilicon conductive material layer 6 with the thickness of 50nm on the upper surface of the first silicon nitride dielectric layer 5, and etching the left area of the second polysilicon conductive material layer 6 by using a mask etching method to expose the lower first silicon nitride dielectric layer 5, thereby avoiding the conductive material from contacting with the terminal electrode 15 on the left side; wherein the cross-sectional side view after depositing the second polysilicon conductive material layer 6 on the trench type three-dimensional structure 2 is shown in fig. 11.
Step seven: depositing a second silicon nitride dielectric layer 7 with the thickness of 20nm on the upper surface of the second polycrystalline silicon conducting material layer 6 and covering the lower second polycrystalline silicon conducting material layer 6; wherein the cross section of the side surface after depositing the second silicon nitride dielectric layer 7 on the trench type three-dimensional structure 2 is shown in fig. 12.
Step eight: depositing a layer of third polysilicon conductive material layer 8 with the thickness of 50nm on the upper surface of the second silicon nitride dielectric layer 7, and etching the right side area of the third polysilicon conductive material layer 8 by using a mask etching method to expose the lower layer of the second silicon nitride dielectric layer 7, so as to prevent the conductive material from contacting with the terminal electrode 14 on the right side; wherein the cross-sectional side view after depositing the third polysilicon conductive material layer 8 on the trench type three-dimensional structure 2 is shown in fig. 13.
Step nine: depositing a third silicon nitride dielectric layer 9 with the thickness of 20nm on the upper surface of the third polycrystalline silicon conductive material layer 8 and covering the lower third polycrystalline silicon conductive material layer 8; wherein the cross-sectional side view after depositing the third silicon nitride dielectric layer 9 on the trench type three-dimensional structure 2 is shown in fig. 14.
Step ten: depositing a layer of fourth polysilicon conductive material layer 10 with the thickness of 50nm on the upper surface of the third silicon nitride dielectric layer 9, and etching the left area of the fourth polysilicon conductive material layer 10 by using a mask etching method to expose the lower layer of the third silicon nitride dielectric layer 9, so as to prevent the conductive material from contacting with the terminal electrode 15 on the left side; wherein the cross section of the side surface after the fourth polysilicon conductive material layer 10 is deposited on the trench type three-dimensional structure 2 is shown in fig. 15.
Step eleven: depositing a fourth silicon nitride dielectric layer 11 with the thickness of 20nm on the upper surface of the fourth polycrystalline silicon conductive material layer 10 and covering the lower fourth polycrystalline silicon conductive material layer 10; wherein, the cross section of the side surface after depositing the fourth silicon nitride dielectric layer 11 on the trench type three-dimensional structure 2 is shown in fig. 16.
Step eight: depositing a fifth polysilicon conductive material layer 12 with the thickness of 50nm on the upper surface of the fourth silicon nitride dielectric layer 11, and etching the right side area of the fifth polysilicon conductive material layer 12 by using a mask etching method to expose the lower fourth silicon nitride dielectric layer 11, so as to prevent the conductive material from contacting the terminal electrode 14 on the right side; wherein the cross-sectional side view after depositing the fifth polysilicon conductive material layer 12 on the trench type three-dimensional structure 2 is shown in fig. 17.
Step thirteen: depositing a second silicon nitride insulating layer 13 with the thickness of 200nm on the upper surface of the fifth polycrystalline silicon conducting material layer 12 and covering the lower five polycrystalline silicon conducting material layer 12; wherein the cross-sectional side view after depositing the second insulating silicon nitride layer 13 on the trench type three-dimensional structure 2 is shown in fig. 18.
Fourteen steps: and cutting the capacitor with the preliminary structure to obtain a single-end electrode capacitor.
A fifteenth step: the shorter two ends of the capacitor are covered with a right electrode 14 and a left electrode 15 respectively, the right electrode 14 is connected with the second polysilicon conductive material layer 6 and the fourth polysilicon conductive material layer 10 respectively, the left electrode 15 is connected with the first polysilicon conductive material layer 4, the third polysilicon conductive material layer 8 and the fifth polysilicon conductive material layer 12 respectively, and the final result is as shown in fig. 19.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (10)
1. A terminal electrode capacitor, comprising: a capacitor body, a first metal electrode disposed on a left side of the capacitor body, and a second metal electrode disposed on a right side of the capacitor body;
the capacitor body comprises a three-dimensional matrix structure, a first insulating layer deposited on the upper surface of the three-dimensional matrix structure, a capacitor structure deposited on the upper surface of the first insulating layer, and a second insulating layer deposited on the upper surface of the capacitor structure;
the capacitor structure comprises a plurality of conductive material layers, and a dielectric layer is arranged between every two adjacent conductive material layers;
in the multiple layers of conductive material layers, the conductive material layers of odd layers are connected with the first metal electrode, and the conductive material layers of even layers are connected with the second metal electrode; or, in the multiple layers of conductive material layers, even layers of conductive material layers are connected with the first metal electrode, and odd layers of conductive material layers are connected with the second metal electrode.
2. A terminal electrode capacitor according to claim 1 wherein said three-dimensional matrix structure is a trench three-dimensional matrix structure, a hole three-dimensional matrix structure, or a spiral trench three-dimensional matrix structure.
3. A terminal electrode capacitor according to claim 1, wherein said three-dimensional body structure is formed by etching a substrate; the three-dimensional base structure is sequentially divided into a left substrate area, a three-dimensional structure area and a right substrate area from left to right.
4. A terminal electrode capacitor according to claim 3, wherein among the plurality of conductive material layers, when odd-numbered conductive material layers are connected to the first metal electrode and even-numbered conductive material layers are connected to the second metal electrode, the odd-numbered conductive material layers cover the first region and the even-numbered conductive material layers cover the second region; or, in the multiple layers of conductive material layers, when the even layers of conductive material layers are connected with the first metal electrode and the odd layers of conductive material layers are connected with the second metal electrode, the odd layers of conductive material layers cover the second region, and the even layers of conductive material layers cover the first region;
the first area is an area formed by a left substrate area, a three-dimensional structure area and a part of a right substrate area; the second area is an area formed by a part of the left substrate area, the three-dimensional structure area and the right substrate area; wherein the partial left substrate region is a region connected with the three-dimensional structure region; the part of the right substrate region is a region connected with the three-dimensional structure region.
5. A terminal electrode capacitor according to claim 1, wherein said first insulating layer and said second insulating layer are both 20nm thick; the thickness of the dielectric layer is 20nm; the thickness of the conductive material layer is 50nm.
6. A terminal electrode capacitor according to claim 1, wherein said first metal electrode and said second metal electrode are the same material; the first metal electrode is made of one or more metal materials of Ag, pd, cu, ni, au, al and Cr.
7. A terminal electrode capacitor according to claim 1, wherein the material of said first insulating layer is one or more of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide; the second insulating layer is made of one or more insulating materials of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide and hafnium oxide; the dielectric layer is made of one or more insulating materials of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide and hafnium oxide.
8. A method for manufacturing an end electrode capacitor, comprising:
processing the upper surface of the substrate by adopting an etching process to obtain a three-dimensional matrix structure;
depositing a first insulating layer on an upper surface of the three-dimensional base structure;
depositing a capacitor structure on an upper surface of the first insulating layer;
depositing a second insulating layer on the upper surface of the capacitor structure to obtain a capacitor main body;
a first metal electrode is arranged on the left side of the capacitor body, and a second metal electrode is arranged on the right side of the capacitor body;
the capacitor structure comprises a plurality of conductive material layers, and a dielectric layer is arranged between every two adjacent conductive material layers; in the multiple layers of conductive material layers, the odd layers of conductive material layers are connected with the first metal electrode, and the even layers of conductive material layers are connected with the second metal electrode; or, in the multiple layers of conductive material layers, even layers of conductive material layers are connected with the first metal electrode, and odd layers of conductive material layers are connected with the second metal electrode.
9. The method for manufacturing a terminal electrode capacitor as claimed in claim 8, wherein said three-dimensional matrix structure is divided into a left substrate region, a three-dimensional structure region and a right substrate region in sequence from left to right; depositing a capacitor structure on the upper surface of the first insulating layer specifically includes:
depositing a first initial conductive material layer on the upper surface of the first insulating layer, and etching the right area of the first initial conductive material layer by adopting a conductive material etching process to form a first conductive material layer; the first layer of conductive material can cover the first region;
depositing a first dielectric layer on the upper surface of the first conductive material layer; the first dielectric layer can cover the third area;
depositing a second initial conductive material layer on the upper surface of the first dielectric layer, and etching the left area of the second initial conductive material layer by adopting a conductive material etching process to form a second conductive material layer; the second layer of conductive material can cover the second region;
repeating the steps until the number of the conductive material layers reaches a target value to form a capacitor structure;
the first region is a region composed of a left substrate region, a three-dimensional structure region and a part of a right substrate region; the second area is an area formed by a part of the left substrate area, the three-dimensional structure area and the right substrate area; the third area is an area formed by a left substrate area, a three-dimensional structure area and a right substrate area; the part of the left substrate region is a region connected with the three-dimensional structure region; the part of the right substrate region is a region connected with the three-dimensional structure region.
10. The method for manufacturing a terminal electrode capacitor as claimed in claim 8, wherein said three-dimensional matrix structure is divided into a left substrate region, a three-dimensional structure region and a right substrate region in sequence from left to right; depositing a capacitor structure on the upper surface of the first insulating layer specifically comprises:
depositing a first initial conductive material layer on the upper surface of the first insulating layer, and etching the left area of the first initial conductive material layer by adopting a conductive material etching process to form a first conductive material layer; the first layer of conductive material can cover the second region;
depositing a first dielectric layer on the upper surface of the first conductive material layer; the first dielectric layer can cover the third area;
depositing a second initial conductive material layer on the upper surface of the first dielectric layer, and etching the right area of the second initial conductive material layer by adopting a conductive material etching process to form a second conductive material layer; the second layer of conductive material can cover the first region;
repeating the steps until the number of the conductive material layers reaches a target value to form a capacitor structure;
the first region is a region formed by a left substrate region, a three-dimensional structure region and a part of a right substrate region; the second area is an area formed by a part of the left substrate area, the three-dimensional structure area and the right substrate area; the third area is an area formed by a left substrate area, a three-dimensional structure area and a right substrate area; the part of the left substrate region is a region connected with the three-dimensional structure region; the part of the right substrate region is a region connected with the three-dimensional structure region.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117423548A (en) * | 2023-12-19 | 2024-01-19 | 广州天极电子科技股份有限公司 | Capacitor substrate, high-capacity density capacitor and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117423548A (en) * | 2023-12-19 | 2024-01-19 | 广州天极电子科技股份有限公司 | Capacitor substrate, high-capacity density capacitor and manufacturing method thereof |
| CN117423548B (en) * | 2023-12-19 | 2024-03-29 | 广州天极电子科技股份有限公司 | Capacitor substrate, high-capacity density capacitor and manufacturing method thereof |
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