CN213519941U

CN213519941U - Capacitor with three-dimensional structure

Info

Publication number: CN213519941U
Application number: CN202022785757.XU
Authority: CN
Inventors: 马晓辉
Original assignee: Wuxi Jingyuan Microelectronics Co Ltd
Current assignee: Wuxi Jingyuan Microelectronics Co Ltd
Priority date: 2020-11-26
Filing date: 2020-11-26
Publication date: 2021-06-22
Anticipated expiration: 2030-11-26

Abstract

The scheme discloses a capacitor with a three-dimensional structure, which comprises a substrate, an insulating medium, a positive electrode and a negative electrode; the insulating medium grows on the substrate, and the surface of the insulating medium is provided with a plurality of layers of positive electrodes and a plurality of layers of negative electrodes; each layer of positive electrode is provided with a positive electrode extension section, and the positive electrode extension section is embedded into the insulating medium and extends towards one side of the negative electrode without contacting with the negative electrode; each layer of negative electrode is provided with a negative electrode extension section, and the negative electrode extension section is embedded into the insulating medium and extends towards one side of the positive electrode without contacting with the positive electrode; a first through hole conducting layer is arranged between two adjacent positive electrode extending sections, and a second through hole conducting layer is arranged between two adjacent negative electrode extending sections. The positive electrode and the negative electrode of the capacitor have a three-dimensional structure, so that the capacitor has better voltage regulation characteristics, the distance between metal layers can be regulated according to the requirement on withstand voltage, the process cost is not additionally increased, and the capacitor is used in a chip, so that the area of the chip is favorably reduced, and the cost of the chip is reduced.

Description

Capacitor with three-dimensional structure

Technical Field

The utility model relates to an electrical components technical field, in particular to spatial structure condenser.

Background

Capacitors are indispensable devices in the design and fabrication of integrated circuits. The current capacitor types are mainly MOS capacitor, PIP capacitor, MIM capacitor and MOM capacitor. The MOS capacitor is difficult to realize high withstand voltage in many processes due to the limitation of the thickness of gate oxide, and the capacity of the MOS capacitor is greatly changed along with the voltage; the PIP capacitor and the MIM capacitor are planar capacitors, so that a contradiction exists between the capacitance and the withstand voltage of the capacitors, the higher the withstand voltage requirement is, the lower the capacitance per unit area is, the larger the required area is, extra photoetching and related process steps are also needed to be added, the process cost is increased, and in addition, not all the processes support the PIP capacitor and the MIM capacitor; the MOM capacitor has better voltage characteristics, and the withstand voltage can be improved by increasing the distance between metal plates, but because of the limitation of the metal thickness, particularly the metal thickness of the process below 0.18 mu m is thinner, the capacitance per unit area is difficult to be increased.

SUMMERY OF THE UTILITY MODEL

One objective of the present disclosure is to provide a capacitor with a three-dimensional structure, which has the characteristics of high voltage endurance, good characteristic of changing with voltage, large capacity per unit area, and no additional process cost, and can make many high-voltage integrated circuits have better performance and cost advantages.

In order to achieve the purpose, the scheme is as follows:

a three-dimensional structure capacitor comprises a substrate, an insulating medium, a positive electrode and a negative electrode;

the insulating medium grows on the substrate, and the surface of the insulating medium is provided with a plurality of layers of positive electrodes and a plurality of layers of negative electrodes;

each layer of positive electrode is provided with a positive electrode extension section, and the positive electrode extension section is embedded into the insulating medium and extends towards one side of the negative electrode without contacting with the negative electrode;

each layer of negative electrode is provided with a negative electrode extension section, and the negative electrode extension section is embedded into the insulating medium and extends towards one side of the positive electrode without contacting with the positive electrode;

a first through hole conducting layer is arranged between two adjacent positive electrode extending sections, and a second through hole conducting layer is arranged between two adjacent negative electrode extending sections.

Preferably, each layer of positive electrode extension segment and each layer of negative electrode extension segment are staggered and adjacent in the insulating medium and are parallel to each other.

Preferably, each layer of positive electrode extension section and each layer of negative electrode extension section form an interdigital structure.

Preferably, each adjacent layer of positive electrode extension and negative electrode extension has a facing surface.

Preferably, the facing surfaces of each adjacent positive electrode extension and negative electrode extension and the insulating medium therebetween form a first capacitor.

Preferably, the surfaces of the first through hole conducting layer and the second through hole conducting layer which are opposite to each other in the adjacent layer and the insulating medium between the two layers form a second capacitor.

Preferably, the capacitor comprises a plurality of first capacitors and second capacitors which are alternately adjacent to each other

Preferably, the positive and negative electrodes of the same layer have the same thickness.

Preferably, the substrate is a silicon substrate.

In a second aspect, a chip is provided, which comprises the capacitor as described above.

The scheme has the following beneficial effects:

in the scheme, the positive electrode and the negative electrode of the capacitor have a three-dimensional structure, so that the capacitor has better voltage regulation characteristics, the distance between metal layers can be regulated according to the requirement on withstand voltage, the process cost is not additionally increased, the withstand voltage can reach 50V or even more than 100V, the three-dimensional structure of the capacitor longitudinally increases the effective area of the capacitor, and the capacitance per unit area is improved. The number of layers of the metal layer can be two or more, the more the number of metal layers is, the larger the unit area capacity is, thereby the unit area capacity is improved to a greater extent, and the capacitor of the scheme is used in the chip, which is beneficial to reducing the chip area and reducing the chip cost.

Drawings

In order to illustrate the implementation of the solution more clearly, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the solution, and that other drawings may be derived from these drawings by a person skilled in the art without inventive effort.

FIG. 1 is a perspective view of a capacitor according to the present embodiment;

FIG. 2 is a longitudinal structural view of the capacitor of the present embodiment;

FIG. 3 is a plan view of a first electrode metal layer and first and second via conductive layers in the capacitor according to the present invention;

FIG. 4 is a plan view of a second electrode metal layer and first and second via conductive layers in the capacitor according to the present invention;

fig. 5 is a plan view of the first plate capacitor C1 according to the present embodiment;

fig. 6 is a plan view of the second plate capacitor C2 according to the present embodiment;

fig. 7 is a plan view of a third flat capacitor C3 according to the present embodiment;

FIG. 8 is a longitudinal structure diagram of a capacitor having a three-dimensional structure formed by four layers of metals in the embodiment;

wherein, 101-substrate; 102-a first insulating medium; 103-a first layer positive electrode; 104-a first layer of negative electrodes; 105-a first via conductive layer; 106-a second via conductive layer; 107-a second insulating medium; 108-a third insulating medium; 109-second layer positive electrode; 110-second layer negative electrode.

Detailed Description

Embodiments of the present solution will be described in further detail below with reference to the accompanying drawings. It is clear that the described embodiments are only a part of the embodiments of the present solution, and not an exhaustive list of all embodiments. It should be noted that, in the present embodiment, features of the embodiment and the embodiment may be combined with each other without conflict.

The terms "first," "second," and the like in the description and in the claims, and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be understood that the term "and/or" as used herein is only one type of association relationship describing the associated object, and means that there may be three types of relationships, e.g., a and/or B, and may mean-three types of a exists alone, a and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrases "if determined" or "if detected (a stated condition or event)" may be interpreted as "when determined" or "in response to a determination" or "when detected (a stated condition or event)" or "in response to a detection (a stated condition or event)", depending on the context.

The MOM capacitor has better voltage characteristic, the withstand voltage can be improved by increasing the distance between metal polar plates, but the MOM capacitor is limited by the metal thickness, particularly the metal thickness of the process below 0.18 mu m is thinner, the capacitance capacity per unit area is difficult to be increased, the scheme provides a capacitor, a positive electrode and a negative electrode are of a multilayer structure and are formed by a plurality of conducting layers, the conducting layers are overlapped to form a conducting wall, so that the positive electrode and the negative electrode in the capacitor form two mutually parallel conducting walls, and the positive electrode and the negative electrode are provided with a plurality of extending conducting walls, so that the inside of the capacitor has a three-dimensional structure, the capacitor adopting the structure of the scheme has better capacitance characteristic changing along with the voltage, and under the condition that the thickness of a capacitance medium is determined according to the capacitance withstand voltage requirement, the three-dimensional structure of the positive electrode and the negative electrode can effectively increase the effective area in the capacitor and improve, the capacitor is used in the chip, the area of the chip can be reduced, the additional process cost is not increased, and the chip cost is reduced while the performance of the chip is ensured.

The capacitor with a three-dimensional structure comprises a substrate 101, a first insulating medium 102, a plurality of layers of positive electrodes and a plurality of layers of negative electrodes. A first insulating medium 102 is grown on a substrate 101, and a multilayer positive electrode is arranged on the surface of the first insulating medium 102; a plurality of negative electrodes are provided on the first insulating medium 102;

a first through hole conducting layer 105 is arranged between the positive electrodes of the adjacent upper and lower layers, and a second through hole conducting layer 106 is arranged between the negative electrodes of the adjacent upper and lower layers;

counting from the substrate upwards, wherein the layer thickness of the Nth positive electrode and the layer thickness of the Nth negative electrode are the same;

each layer of positive electrode is provided with a plurality of positive electrode extension sections, the positive electrode extension sections of each layer are connected with each layer of positive electrode, the positive electrode extension sections are embedded into an insulating medium and extend to one side of the negative electrode, the positive electrode extension sections are not contacted with the negative electrode, and a first through hole conductive medium layer is arranged between the positive electrode extension sections of the upper layer and the lower layer;

each layer of negative electrode is provided with a plurality of negative electrode extension sections, the negative electrode extension sections of each layer are connected with each layer of negative electrode, the negative electrode extension sections are embedded into the insulating medium and extend towards one side of the positive electrode, the negative electrode extension sections are not in contact with the positive electrode, and a second through hole dielectric conducting layer is arranged between the negative electrode extension sections of the upper layer and the lower layer.

In one embodiment, the facing surfaces of the positive electrode extension and the negative electrode extension of each adjacent layer and the insulating medium between the facing surfaces form a capacitor.

In one embodiment, each layer of positive electrode extension and each layer of negative electrode extension form an interdigitated structure.

In one embodiment, the facing surfaces of the first via hole conductive layer and the second via hole conductive layer in the adjacent layers and the insulating medium therebetween form a second capacitor.

Preferably, the capacitor includes a plurality of first capacitors and second capacitors alternately adjacent to each other.

The present solution is described in detail below with reference to the accompanying drawings.

In fig. 1-8, C1 — first plate capacitor; c2 — second plate capacitance; c3-third plate capacitance; c4-fourth plate capacitance; c5-fifth plate capacitance; c6-sixth plate capacitance; c7-seventh plate capacitance; d1 — spacing between first layer positive electrode and first layer negative electrode; d2 — the spacing between the first via conductive layer and the second via conductive layer; d 3-spacing between the second layer positive electrode and the second layer negative electrode; h1 — thickness of first layer positive and negative electrodes; h2 — thickness of first and second via conductive layers; h 3-thickness of second layer positive and negative electrodes.

As shown in fig. 1 to 8, a capacitor includes a substrate 101, an insulating medium 10, a multilayer positive electrode and a multilayer negative electrode.

In this embodiment, each of the positive electrodes and each of the negative electrodes is a metal layer.

The substrate 101 is a silicon substrate, a first insulating medium 102 is grown on the substrate 101, a first layer of positive electrodes 103 and a first layer of negative electrodes 104 are arranged on the first insulating medium 102, a second insulating medium 107 is arranged between the first layer of positive electrodes 103 and the first layer of negative electrodes 104, a second layer of positive electrodes 109 and a second layer of negative electrodes 110 are arranged between the second layer of positive electrodes 109 and the second layer of negative electrodes 110, a third insulating medium 108 is arranged between the second layer of positive electrodes 109 and the second layer of negative electrodes 110, a first layer of through hole conducting layers 105 is connected between the first layer of positive electrodes 103 and the second layer of positive electrodes 109, and a second layer of through hole conducting layers 106 is connected between the first layer of negative electrodes 104 and.

The first layer positive electrode 103 and the first layer negative electrode 104 are of an interdigital structure parallel to each other, but are not limited to an interdigital structure; the first layer positive electrode 103 and the first layer negative electrode 104 respectively form a positive electrode and a negative electrode of the first flat capacitor C1, and the positive electrode and the negative electrode can be interchanged; the second insulating medium 107 is the capacitance medium of the first plate capacitance C1. As shown in fig. 3 and 4, the first through-hole conductive layer 105 is located in the first positive electrode layer 103 and the second positive electrode layer 109 on the plane, the first through-hole conductive layer 105 is electrically connected to the first positive electrode layer 103 and the second positive electrode layer 109, and the first through-hole conductive layer 105 is made of metal; according to the requirement on the withstand voltage of the capacitor, on the premise of meeting the design rule, the distance d1 between the first layer positive electrode 103 and the first layer negative electrode 104 is adjusted, and the larger the d1 is, the higher the withstand voltage of the capacitor is, but the capacity per unit area is reduced; the distance d1 between the first layer of positive electrodes 103 and the first layer of negative electrodes 104 and the thickness h1 of the first layer of electrodes determine the capacity per unit area of the first plate capacitor C1.

The second layer of positive electrodes 109 and the second layer of negative electrodes 110 are interdigitated structures parallel to each other, but are not limited to interdigitated structures. The second layer positive electrode 109 and the second layer negative electrode 110 respectively constitute a positive electrode and a negative electrode of the third plate capacitor C3, and the positive electrode and the negative electrode can be interchanged; the third insulating dielectric 108 is the capacitance dielectric of the third plate capacitor C3. The second through hole conducting layer 106 is arranged in the first layer negative electrode 104 and the second layer negative electrode 110 on the plane, the second through hole conducting layer 106 is electrically connected with the first layer negative electrode 104 and the second layer negative electrode 110, and the second through hole conducting layer 106 is made of metal; according to the requirement on the capacitor withstand voltage, on the premise of meeting the design rule, the distance d3 between the second layer metal 1 and the second layer metal 2 is adjusted, and the larger the d3 is, the higher the capacitor withstand voltage is, but the unit area capacity is reduced; the distance d3 between the second layer metal 1 and the second layer metal 2 and the thickness h3 of the second layer metal determine the capacity per unit area of C3.

The first via conductive layer 105 and the second via conductive layer 106 are parallel to each other, but not limited to an interdigital structure, the first via conductive layer 105 and the second via conductive layer 106 respectively form a positive electrode and a negative electrode of the second planar capacitor C2, and the positive electrode and the negative electrode can be interchanged; the second insulating medium 107 is the capacitance medium of the second plate capacitance C2. The distance d2 and the thickness h2 of the first via conductive layer 105 and the second via conductive layer 106 determine the capacity per unit area of the capacitor C2.

The first layer of positive electrode 103, the second layer of positive electrode 109 and the first through hole conducting layer 105 form a three-dimensional first metal wall, the first layer of negative electrode 104, the second layer of negative electrode 110 and the second through hole conducting layer 106 form a second three-dimensional metal wall, the first metal wall and the second metal wall are respectively the positive electrode and the negative electrode of the capacitor, the positive electrode and the negative electrode can be interchanged, and the capacity of the capacitor is the sum of the first plate capacitor C1, the second plate capacitor C2 and the third plate capacitor C3.

In a process with a small line width, particularly a process below 0.25 μm, the first plate capacitor C1 and the third plate capacitor C3 are conventional MOM (metal-oxide-metal) capacitors, and have substantially equal capacity per unit area, and the second plate capacitor C2 has a capacity per unit area 1.5-2 times that of the first plate capacitor C1 or the third plate capacitor C3. The capacitor structure of the embodiment enables the unit area capacity to be increased by 75% -100% compared with the conventional MOM capacitance.

The number of layers of the positive electrode and the negative electrode of the capacitor can be two or more, and the more the number of metal layers forming the electrodes is, the larger the unit area electric capacity is. In fact, when the number of metal layers is greater than two, taking four layers of metal as an example as shown in fig. 8, the total capacity of the capacitor is the sum of the plate capacitances C1, C2, C3, C4, C5, C6 and C7, wherein C1, C3, C5 and C7 are conventional MOM capacitances, and at this time, the total capacity of the capacitor is increased by 110% to 150% compared with the conventional MOM capacitance, which greatly reduces the chip area occupied by the capacitor.

In conclusion, the capacitor provided by the scheme can realize high voltage resistance of 50V or even more than 100V by forming the three-dimensional flat capacitor through the unique electrode layer structure, has the characteristics of adjustable voltage resistance and good voltage adjustment characteristic, does not increase the process cost, greatly improves the unit area capacity, overcomes the defect that the plane capacitor can only increase the capacitance by increasing the plane area, reduces the chip area using the capacitor while realizing high performance, and reduces the chip cost.

Obviously, the above embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it is obvious for those skilled in the art to make other variations or changes based on the above descriptions, and all the embodiments cannot be exhausted here, and all the obvious variations or changes that belong to the technical solutions of the present invention are still in the protection scope of the present invention.

Claims

1. A capacitor with a three-dimensional structure is characterized by comprising a substrate, an insulating medium, a positive electrode and a negative electrode;

a first through hole conducting layer is arranged between two adjacent positive electrode extending sections, and a second through hole conducting layer is arranged between two adjacent negative electrode extending sections;

the positive electrode and the negative electrode of the same layer have the same thickness.

2. The capacitor of claim 1, wherein each layer of positive electrode extension and each layer of negative electrode extension are interleaved adjacent and parallel to each other in the insulating medium.

3. The capacitor of claim 1, wherein each layer of positive electrode extension and each layer of negative electrode extension form an interdigitated structure.

4. The capacitor of claim 2, wherein each adjacent layer of positive and negative electrode extensions has facing surfaces.

5. The capacitor of claim 4, wherein the facing surfaces of each adjacent positive and negative electrode extension and the insulating medium therebetween form a first capacitor.

6. The capacitor of claim 5, wherein the facing surfaces of the first and second via conductive layers of the adjacent layers and the insulating medium therebetween form a second capacitor.

7. The capacitor according to claim 6, wherein the capacitor comprises a plurality of first capacitors and second capacitors that are alternately adjacent.

8. The capacitor of claim 1, wherein the positive and negative electrodes of the same layer have the same thickness.

9. The capacitor of any one of claims 1 to 8, wherein the substrate is a silicon substrate.