CN102024806A - Metal Oxide Metal Capacitors with Low Parasitic Capacitance - Google Patents
Metal Oxide Metal Capacitors with Low Parasitic Capacitance Download PDFInfo
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- CN102024806A CN102024806A CN2009101743570A CN200910174357A CN102024806A CN 102024806 A CN102024806 A CN 102024806A CN 2009101743570 A CN2009101743570 A CN 2009101743570A CN 200910174357 A CN200910174357 A CN 200910174357A CN 102024806 A CN102024806 A CN 102024806A
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Abstract
The invention discloses a metal-oxide layer-metal capacitor, which comprises a first metal layer and a second metal layer, wherein the first metal layer has electronegativity; a second metal layer having electronegativity; and at least one third metal layer arranged between the first metal layer and the second metal layer, wherein each third metal layer in the at least one third metal layer comprises a plurality of first leads with electronegativity and a plurality of second leads with electropositivity, and the two sides of each third metal layer are respectively the first leads in the plurality of first leads. The parasitic capacitance of the positive electrode of the metal-oxide layer-metal capacitor relative to the ground or other points is greatly reduced compared with the prior art, and the metal-oxide layer-metal capacitor is more suitable for circuits sensitive to the parasitic capacitance, such as the input end of an operational amplifier.
Description
Technical field
The present invention relates to a kind of metal-oxide layer-metal capacitance, refer to that especially a kind of positive electrode has the metal-oxide layer-metal capacitance of low parasitic capacitance to other point.
Background technology
(Metal-Oxide-Metal, MOM) electric capacity is common a kind of semicoductor capacitor to metal-oxide layer-metal, and high capacitance density can be provided, and is widely used in mixed signal circuit and the radio circuit.(technology of formation metal-oxide layer-metal capacitance is one photomask less for Metal-Insulator-Metal, MIM) electric capacity, and technology is simpler and easy, economical compared to metal-insulator-metal.
Please refer to Fig. 1 and Fig. 2, Fig. 1 is the plane graph of the odd number metal level 11 of known cross joint (Interdigitated) metal-oxide layer-metal capacitance 10, and Fig. 2 is the plane graph of the even number metal level 12 of metal-oxide layer-metal capacitance 10.As electrode, the material of lead can be metal or polysilicon (Polystalline Silicon) with lead for metal-oxide layer-metal capacitance 10.The electrode pattern of each metal level such as finger-shaped fork closes, adjacent wires have different electrically, in the accompanying drawings with+and-indicate.In metal level 11, lead 111,113,115 is connected in bus bar 117, and lead 112,114,116 is connected in bus bar 118; In metal level 12, lead 122,124,126 is connected in bus bar 128, and lead 121,123,125 is connected in bus bar 127.Identical electrical lead sees through the interlayer hole (Via) on the bus bar, shown in hatched example areas, electrically connects mutually.
By Fig. 1 and Fig. 2 as can be known, electrically different with lead adjacent in the layer of each lead, and with adjacent bed in adjacent lead electrically different, therefore, the vertical section of metal-oxide layer-metal capacitance 10 can be represented as Fig. 3.In metal-oxide layer-metal capacitance 10, the electropositive lead is over the ground or to the parasitic capacitance of other point in the circuit, with elecrtonegativity lead big or small identical over the ground or to the parasitic capacitance of other point in the circuit.Please note, in common circuit such as analogy digital quantizer, digital analogue converter, sample-and-hold circuit or filter circuit, the input of operational amplifier is quite responsive to parasitic capacitance, and parasitic capacitance should be as much as possible little, to avoid influencing the service behaviour of operational amplifier.Yet for metal-oxide layer-metal capacitance 10, wherein the electropositive lead diminishes it through design over the ground or to the parasitic capacitance of other point, therefore is not suitable for the input of operational amplifier.
Except cross joint metal-oxide layer-metal capacitance 10, known semiconductor technology also can form the metal-oxide layer-metal capacitance of other form.Please refer to Fig. 4, Fig. 4 is the sectional arrangement drawing of known parallel plate type (Parallel Plate) metal-oxide layer-metal capacitance 40.Metal-oxide layer-metal capacitance 40 is overlapped with dielectric layer by the identical metal level 41～45 of area and forms, and dielectric layer omits sign in Fig. 4.Each metal level is a plate electrode, and different electrical plate electrode is staggered.Be with cross joint metal-oxide layer-metal capacitance 10 similarities, in parallel plate type metal-oxide layer-metal capacitance 40, the electropositive plate electrode is over the ground or to the parasitic capacitance of other point in the circuit, with elecrtonegativity plate electrode big or small identical over the ground or to the parasitic capacitance of other point, be not suitable for the input of operational amplifier.
In addition, with actual process, when etching formed in metal-oxide layer-metal capacitance 40 each plate electrode, if the edge of plate electrode was shown in Figure 4 generally neat, but uneven.The edge of each plate electrode is to the parasitic capacitance at the edge of its upper panel electrode, inequality to the parasitic capacitance at the edge of its lower floor's plate electrode with the edge of this plate electrode, the parasitic capacitance that irregular electrode edge caused has reduced the accuracy of metal-oxide layer-metal capacitance 40.Moreover, when the input of operational amplifier uses metal-oxide layer-metal capacitance 40, the variability of the parasitic capacitance value that irregular electrode edge caused, the electric capacity coupling of gain that may cause being used for designing operational amplifier is bad, makes the gain of operational amplifier depart from ideal value.
Summary of the invention
Therefore, main purpose of the present invention promptly is to provide a kind of metal-oxide layer-metal capacitance, and its positive electrode has lower parasitic capacitance with respect to negative electrode.
The present invention discloses a kind of metal-oxide layer-metal capacitance, includes the first metal layer, has first electrical; Second metal level has that this is first electrical; And at least one the 3rd metal level, be located between this first metal layer and this second metal level, each the 3rd metal level comprises and has these first electrical many first leads and have second many second electrical leads in this at least one the 3rd metal level, and the both sides of this each the 3rd metal level are respectively these many first leads first lead wherein.
The present invention discloses a kind of metal-oxide layer-metal capacitance in addition, includes a plurality of the first metal layers, has first electrical; And at least one second metal level, have second electrical, each second metal level is located in these a plurality of the first metal layers between the two adjacent the first metal layers in this at least one second metal level, and the area of this each second metal level is less than the area of this adjacent the first metal layer.
Description of drawings
Fig. 1 is the plane graph of the odd number metal level of known cross joint metal-oxide layer-metal capacitance.
Fig. 2 is the plane graph of even number metal level of cross joint metal-oxide layer-metal capacitance of Fig. 1.
Fig. 3 is the sectional arrangement drawing of cross joint metal-oxide layer-metal capacitance of Fig. 1.
Fig. 4 is the sectional arrangement drawing of known parallel plate type metal-oxide layer-metal capacitance.
Fig. 5 is the sectional arrangement drawing of the cross joint metal-oxide layer-metal capacitance of the embodiment of the invention.
Fig. 6 is the plane graph of odd number metal level of metal-oxide layer-metal capacitance of Fig. 5.
Fig. 7 is the plane graph of even number metal level of metal-oxide layer-metal capacitance of Fig. 5.
Fig. 8 and Fig. 9 are the sectional arrangement drawing of the cross joint metal-oxide layer-metal capacitance of the embodiment of the invention.
Figure 10 is the sectional arrangement drawing of embodiment of the invention parallel plate type metal-oxide layer-metal capacitance.
Figure 11 is the plane perspective view of metal-oxide layer-metal capacitance of Figure 10.
Figure 12 is the plane perspective view of embodiment of the invention parallel plate type metal-oxide layer-metal capacitance.
Description of reference numerals
10,40,50,80,90,100,120 metal-oxide layer-metal capacitances
11,12,41～45,51,52, L1～LN metal level
111～118,121～128,511～529,531,533,535 leads
Embodiment
Please refer to Fig. 5, Fig. 5 is the sectional arrangement drawing of embodiment of the invention cross joint metal-oxide layer-metal capacitance 50.Metal-oxide layer-metal capacitance 50 includes metal level L1～LN, and wherein the 1st layer (bottom) and N layer (top layer) are plate electrode, the 2nd layer to (N-1) layer each layer be with lead as electrode, lead with electrically with+and-indicate.Be dielectric layer between the metal level, omit sign in the accompanying drawings.The number of conductors of each metal level shown in the following drawings only is embodiments of the invention, does not limit to category of the present invention.The bottom of metal-oxide layer-metal capacitance 50 and top layer are electronegative plate electrode, rather than positive and negative electrical staggered lead, and in the 2nd layer to (N-1) layer each the layer in, the lead that is positioned at both sides is all elecrtonegativity, then is that electropositive lead and elecrtonegativity lead are staggered except that both sides.The elecrtonegativity lead left and right sides in each electropositive lead and the same metal level is adjacent, and neighbouring with the elecrtonegativity lead in the adjacent metal.
Please refer to Fig. 6 and Fig. 7, Fig. 6 and Fig. 7 be respectively the 2nd layer of metal-oxide layer-metal capacitance 50 of Fig. 5 to (N-1) layer wherein odd number metal level 51 and the plane graph of even number metal level 52.In metal level 51, elecrtonegativity lead 511,513,515,517,519,521 is connected in bus bar 523, and electropositive lead 512,514,516 is connected in bus bar 518.In metal level 52, elecrtonegativity lead 525,527,529,531,533 is connected in bus bar 535, and electropositive lead 520,522,524,526 is connected in bus bar 528.Electropositive lead in all metal levels, electrically connects shown in hatched example areas mutually by the interlayer hole on the bus bar; Elecrtonegativity lead in all metal levels also electrically connects by the interlayer hole on the bus bar, and electrically connects with the elecrtonegativity plate electrode of bottom and top layer.In addition, the elecrtonegativity lead of each odd number metal level both sides is provided with interlayer hole, is used for electrically connecting the both sides of adjacent odd number metal level.
As from the foregoing, metal～oxide layer-metal capacitance 50 is with the elecrtonegativity plate electrode of bottom and top layer and the elecrtonegativity lead of other metal level both sides, the electropositive lead of inside is surrounded, therefore, the electropositive lead reaches the parasitic capacitance to other point over the ground, is subjected to peripheral elecrtonegativity plate electrode and covering of lead and reduces.Thus, metal-oxide layer-metal capacitance 50 more known cross joint metal-oxide layer-metal capacitances more are applicable to the circuit to the parasitic capacitance sensitivity, as the input of operational amplifier.
Note that metal-oxide layer-metal capacitance 50 is embodiments of the invention, those of ordinary skills are when doing different variations and modification according to this.Please refer to Fig. 8, Fig. 8 is the sectional arrangement drawing of embodiment of the invention cross joint metal-oxide layer-metal capacitance 80.Metal-oxide layer-metal capacitance 80 metalloids-oxide layer-metal capacitance 50, difference are that the bottom of metal-oxide layer-metal capacitance 80 and top layer are not plate electrodes, but the elecrtonegativity lead.Metal-oxide layer-metal capacitance 80 is with the elecrtonegativity lead of bottom, top layer and each metal level both sides, the electropositive lead of inside is surrounded, reach parasitic capacitance over the ground to reduce the electropositive lead to other point, precisely because for the minimizing effect of parasitic capacitance not as metal-oxide layer-metal capacitance 50.Those of ordinary skills can know the plane graph and the process of each metal level by inference according to the sectional arrangement drawing of metal-oxide layer-metal capacitance 80, do not give unnecessary details at this.
Please refer to Fig. 9, Fig. 9 is the sectional arrangement drawing of embodiment of the invention cross joint metal-oxide layer-metal capacitance 90.Metal-oxide layer-metal capacitance 90 includes metal level L1～LN, and wherein bottom and top layer are plate electrode, the 2nd layer to (N-1) layer in each the layer with lead as electrode.Metal-oxide layer-metal capacitance 50 of metal-oxide layer-metal capacitance 90 similar Fig. 5, difference is the 2nd layer to each layer of (N-1) layer, except both sides must be the elecrtonegativity leads, electrically being staggered of all the other leads is not that with a lead be unit, but is unit with two leads.Metal-oxide layer-metal capacitance 90 is with the elecrtonegativity plate electrode of bottom and top layer and the elecrtonegativity lead of other metal level both sides equally, the electropositive lead of inside is surrounded, therefore reduced the electropositive lead and reached parasitic capacitance over the ground, be applicable to the input of operational amplifier other point.
Furthermore, in the cross joint metal-oxide layer-metal capacitance of the embodiment of the invention, the 2nd layer to (N-1) layer in each layer except the elecrtonegativity lead of both sides, remaining elecrtonegativity lead can be considered the set of a plurality of groups, and all electropositive leads also can be considered the set of a plurality of groups.Embodiment conclusion by Fig. 5 and Fig. 9 learns that each electropositive lead group includes at least one electropositive lead, and each elecrtonegativity lead group includes at least one elecrtonegativity lead.The elecrtonegativity lead group left and right sides in each electropositive lead group and the same metal level is adjacent, and neighbouring with the elecrtonegativity lead group in the adjacent metal.
Please refer to Figure 10, Figure 10 is the sectional arrangement drawing of embodiment of the invention parallel plate type metal-oxide layer-metal capacitance 100.Metal-oxide layer-metal capacitance 100 is overlapped by metal level L1～LN and dielectric layer and forms, and dielectric layer is not shown among Figure 10.Each metal level is a plate electrode, and different electrical plate electrode is staggered, odd number metal level L1, L3, L5 ..., LN is the elecrtonegativity plate electrode, even number metal level L2, L4, L5 ..., L (N-1) is the electropositive plate electrode.The area of each electropositive plate electrode is less than the area of two neighbouring elecrtonegativity plate electrodes.Please refer to the 11st figure, Figure 11 is the plane perspective view of metal-oxide layer-metal capacitance 100, is the odd number metal level with solid line sign person wherein; With dotted line sign person is the even number metal level.As shown in figure 11, each electropositive plate electrode is pulled out another electrode zone in the same side, electrically connects mutually by interlayer hole (shown in hatched example areas) and other electropositive plate electrode; Each elecrtonegativity plate electrode also electrically connects by interlayer hole and other elecrtonegativity plate electrode mutually in the same side.
By Figure 10 and Figure 11 as can be known, the bottom and the top layer of parallel plate type metal-oxide layer-metal capacitance 100 are all the elecrtonegativity plate electrode, and wherein the area of each electropositive plate electrode all less than the area of adjacent elecrtonegativity plate electrode.Thus, the electropositive plate electrode reaches the parasitic capacitance to other point over the ground, is subjected to peripheral covering of elecrtonegativity plate electrode and reduces.Compared to known parallel plate type metal-oxide layer-metal capacitance 40, the circuit that parallel plate type metal-oxide layer-metal capacitance 100 more is applicable to the parasitic capacitance sensitivity is as the input of operational amplifier.
Note that Figure 10 and metal-oxide layer-metal capacitance 100 shown in Figure 11 are two-point electric capacity, dwindle the electropositive plate electrode among the present invention, also can be used to form bikini electric capacity to reduce the notion of parasitic capacitance.Please refer to Figure 12, Figure 12 is the plane perspective view of embodiment of the invention metal-oxide layer-metal capacitance 120.Metal-oxide layer-metal capacitance 120 is a bikini electric capacity, is the odd number metal level with solid line sign person wherein, i.e. the elecrtonegativity plate electrode; With dotted line sign person is the even number metal level, i.e. the electropositive plate electrode; Hatched example areas is an interlayer hole.Those of ordinary skills can obtain the bikini capacitor design as Figure 12 according to notion shown in Figure 10, do not describe in detail at this.
In sum, in cross joint metal-oxide layer-metal capacitance and parallel plate type metal-oxide layer-metal capacitance that the present invention proposes, the electrode of positively charged significantly reduces than known technology over the ground or to the parasitic capacitance of other point, and therefore metal-oxide layer-metal capacitance of the present invention is more suitable for being used in the operation amplifier circuit of analogy digital quantizer, digital analogue converter or sample-and-hold circuit.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (16)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101743570A CN102024806A (en) | 2009-09-11 | 2009-09-11 | Metal Oxide Metal Capacitors with Low Parasitic Capacitance |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009101743570A CN102024806A (en) | 2009-09-11 | 2009-09-11 | Metal Oxide Metal Capacitors with Low Parasitic Capacitance |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2011104425539A Division CN102522403A (en) | 2009-09-11 | 2009-09-11 | Metal-oxide-metal (MOM) capacitor possessing low parasitic capacitance |
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| CN102024806A true CN102024806A (en) | 2011-04-20 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103384313A (en) * | 2012-05-01 | 2013-11-06 | 香港科技大学 | CMOS active pixel image sensor and calibration method thereof |
| CN104934410A (en) * | 2015-05-08 | 2015-09-23 | 武汉新芯集成电路制造有限公司 | MOM capacitor and capacitance adjusting method |
| CN105280609A (en) * | 2014-06-06 | 2016-01-27 | 格罗方德半导体公司 | Vertical capacitors with spaced conductive lines |
| CN108346676A (en) * | 2017-01-24 | 2018-07-31 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices |
-
2009
- 2009-09-11 CN CN2009101743570A patent/CN102024806A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103384313A (en) * | 2012-05-01 | 2013-11-06 | 香港科技大学 | CMOS active pixel image sensor and calibration method thereof |
| CN105280609A (en) * | 2014-06-06 | 2016-01-27 | 格罗方德半导体公司 | Vertical capacitors with spaced conductive lines |
| CN105280609B (en) * | 2014-06-06 | 2018-11-16 | 格罗方德半导体公司 | Vertical capacitor with interval conducting wire |
| CN104934410A (en) * | 2015-05-08 | 2015-09-23 | 武汉新芯集成电路制造有限公司 | MOM capacitor and capacitance adjusting method |
| CN104934410B (en) * | 2015-05-08 | 2017-10-24 | 武汉新芯集成电路制造有限公司 | A kind of MOM capacitor and electric capacity method of adjustment |
| CN108346676A (en) * | 2017-01-24 | 2018-07-31 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices |
| CN108346676B (en) * | 2017-01-24 | 2021-11-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device with a plurality of transistors |
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Application publication date: 20110420 |