US20140117501A1 - Differential moscap device - Google Patents
Differential moscap device Download PDFInfo
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- US20140117501A1 US20140117501A1 US13/660,172 US201213660172A US2014117501A1 US 20140117501 A1 US20140117501 A1 US 20140117501A1 US 201213660172 A US201213660172 A US 201213660172A US 2014117501 A1 US2014117501 A1 US 2014117501A1
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- 239000003990 capacitor Substances 0.000 claims abstract description 336
- 239000004065 semiconductor Substances 0.000 claims description 50
- 239000000758 substrate Substances 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 10
- 239000000463 material Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 206010035148 Plague Diseases 0.000 description 1
- 241000607479 Yersinia pestis Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the disclosure relates to differential MOS capacitor devices and methods for forming the same.
- Differential capacitor devices such as differential MOSCAP devices are widely used in various applications and in various devices in the electronics industry. These semiconductor devices are fabricated using MOS, metal oxide semiconductor, manufacturing techniques, materials and principles. Differential capacitor devices include multiple capacitor sections or multiple capacitor plates or regions, and the different capacitor sections or different capacitor plates or regions can include different capacitances. Capacitance can be increased in one capacitor section of the MOS capacitor and decreased in another capacitor section of the MOS capacitor during operation, for example. Variable capacitances can be applied and the MOS capacitor devices therefore also serve as MOSVAR devices, i.e. MOS devices with variable reactance, i.e. variable capacitance.
- MOSCAP devices are formed on or over semiconductor substrates using MOS processing operations.
- parasitic capacitance One problem that plagues differential capacitors is parasitic capacitance.
- Parasitic capacitance is present between electronic components or parts because of their proximity to each other.
- Parasitic capacitance can result between different capacitor electrodes coupled to different gates.
- Parasitic capacitance can also result between a capacitor electrode and the drain/source pickup devices used to couple various components such as a lower capacitor plate, to ground.
- Parasitic capacitance can alter the intrinsic capacitance of a capacitor and can also adversely affect the effective capacitance of the operating capacitor of the differential capacitor device. Parasitic capacitance negatively affects device speed and device performance.
- FIG. 1A is a top, plan view of an arrangement of a differential capacitor according to the disclosure and FIG. 1B is a cross-sectional view of a portion of the differential MOS capacitor of FIG. 1A ;
- FIGS. 2A and 2B are a plan view and a cross-sectional view of another embodiment of a differential MOS capacitor according to the disclosure.
- FIGS. 3A and 3B are a plan view and a cross-sectional view of another embodiment of a differential MOS capacitor according to the disclosure.
- FIG. 4 is a plan, top view of another embodiment of a differential MOS capacitor according to the disclosure.
- FIG. 5 is a plan, top view of another embodiment of a differential MOS capacitor according to the disclosure.
- the disclosure provides a differential MOS capacitor (MOSCAP) with capacitor plates coupled to different gates.
- the gates can be biased differently. Different signals can be delivered to the gates and in one embodiment, out-of-phase signals are delivered to the gates.
- the differential MOSCAP includes multiple upper capacitor electrodes disposed over a common lower capacitor electrode which serves as a common node.
- the common lower capacitor electrode is a conductive plate such as an N-well formed in a semiconductor substrate.
- the upper capacitor electrodes are formed over the common lower capacitor electrode in a capacitor region and, in some embodiments, no other electrical components are disposed in the capacitor region and no electrical connections are made to the capacitor region.
- the MOSCAP device includes two capacitors or two capacitor sections coupled to two separate gates, with each of the capacitors or capacitor sections including multiple upper capacitor electrodes.
- the multiple upper capacitor electrodes of each capacitor gate are adjacent one another, and in some embodiments, the multiple upper capacitor electrodes of both capacitors are disposed adjacent one another.
- a guard ring is used and at least partially surrounds the lower conductive plate.
- one or more drain/source pickup devices are used to couple the conductive plate serving as a common lower capacitor electrode, to ground.
- FIGS. 1A and 1B show an exemplary arrangement of a differential MOS capacitor according to the disclosure.
- the differential MOS capacitor includes capacitors 2 and 4 coupled to gates 6 and 8 , respectively.
- Each of capacitor 2 and capacitor 4 may be alternatively referred to and considered to be a capacitor section of a differential MOS capacitor but will be referred to as capacitors 2 and 4 throughout the disclosure.
- Capacitor 2 includes two upper capacitor plates 12 and capacitor 4 includes two upper capacitor plates 14 .
- Upper capacitor plates 12 and 14 are electrodes that are disposed within capacitor region 18 which is indicated by dashed lines.
- Capacitor region 18 is rectangular in the illustrated embodiment and takes on other shapes in other embodiments. Capacitor region 18 can generally be described as a convex polygon as capacitor region 18 does not include void areas or indentations within the region.
- Upper capacitor plates 12 and 14 are disposed over lower capacitor plate 10 .
- Lower capacitor plate 10 is a conductive structure, and in one embodiment, lower capacitor plate 10 is an N-well, or other active area or other conductive area formed within a semiconductor substrate such as within surface 16 , which is an upper surface of semiconductor substrate 48 . In other embodiments, lower capacitor plate 10 is formed of different materials and may be formed within surface 16 of semiconductor substrate 48 or over a semiconductor substrate such as semiconductor substrate 48 .
- Capacitors 2 and 4 each include capacitor dielectric 20 disposed between lower capacitor plate 10 and each upper capacitor plate 12 and 14 .
- Various oxides or other suitable dielectric materials are used for capacitor dielectric 20 and various dielectric thicknesses are used.
- Lower capacitor plate 10 represents a common node between the two upper capacitor plates 12 , a common node between the two upper capacitor plates 14 , and also a common node between upper capacitor plates 12 and 14 , i.e. lower capacitor plate 10 is a common node for capacitors 2 and 4 .
- each upper capacitor plate 12 , 14 includes different shapes and different structures in various embodiments.
- each upper capacitor plate 12 , 14 is formed of three semiconductive or conductive layers disposed over one another and coupled by vias.
- each of lower conductive layer 22 , middle conductive layer 24 , and upper conductive layer 26 is a metal and in another embodiment, lower conductive layer 22 is formed of doped or undoped polysilicon, with middle conductive layer 24 and upper conductive layer 26 formed of metal.
- Vias 28 couple lower conductive layer 22 to middle conductive layer 24 and also couple middle conductive layer 24 to upper conductive layer 26 .
- each upper capacitor plate 12 , 14 is formed of fewer than three semiconductive or conductive layers shown in FIGS. 1A and 1B .
- Upper capacitor plates 12 and 14 are rectangular in FIG. 1A , but other shapes are used in other embodiments.
- regions 34 are largely void of any parasitic capacitance between the respective upper capacitor plates 12 and between the upper capacitor plates 14 . Because there are no further electrical components in regions 34 , parasitic capacitance between upper capacitor plates 12 , 14 and a further electrical component, is avoided.
- the components shown in FIGS. 1A and 1B are formed using various semiconductor manufacturing processes and materials in various embodiments.
- Arrow 36 indicates that capacitors 2 and 4 serve as a differential MOS capacitor, with different signals delivered to respective capacitors 2 and 4 .
- gates 6 and 8 are coupled to signal source 38 as shown in FIG. 1A .
- Signal source 38 delivers AC signals in one embodiment.
- signal 42 delivered to gate 6 and capacitor 2 is out of phase with signal 44 delivered to gate 8 and capacitor 4 .
- signals 42 and 44 are 180° out of phase.
- signals 42 and 44 are sinusoidal signals that are delivered such that a voltage of +1V is delivered to one of gates 6 , 8 at the same time a negative voltage of ⁇ 1V is delivered to the other of gates 6 , 8 .
- Various amplitudes and frequencies are used in various embodiments.
- signals 42 and 44 are delivered in phase.
- signals 42 , 44 delivered to gates 6 and 8 include the capacitance increasing in capacitor 2 while the capacitance decreases in capacitor 4 , or vice versa.
- a single signal source 38 is shown in FIG. 1A , in other embodiments, two separate dedicated signal sources are used with a separate signal source dedicated to each gate 6 , 8 .
- Either or both of signals 42 , 44 may be signals that vary in strength and frequency and capacitors 2 and 4 are varactors in various embodiments.
- a guard ring is used to at least partially surround lower capacitor plate 10 .
- one or more pickup devices 30 are used.
- Pickup devices 30 are drain/source pickup devices and are used to provide a direct connection between lower capacitor plate 10 and ground.
- all pickup devices 30 are disposed outside capacitor region 18 .
- pickup devices 30 are situated such that they are not interposed between upper capacitor plates 12 and such that they are not interposed between upper capacitor plates 14 . In still other embodiments, pickup devices are not used.
- Pickup devices 30 are directly coupled to lower capacitor plate 10 by contacts 40 and are formed of one or more layers of stacked conductive or semiconductor materials such as polysilicon and metal. Pickup devices 30 are coupled to ground using various wires and other conductive interconnect features not shown in FIGS. 1A and 1B .
- FIGS. 2A , 2 B show another arrangement of a differential MOS capacitor according to the disclosure.
- the differential MOS capacitor includes capacitors 52 and 54 .
- capacitor 52 includes two upper capacitor plates 56 and capacitor 54 includes two upper capacitor plates 58 .
- Upper capacitor plates 56 and 58 are disposed within capacitor region 18 .
- Upper capacitor plates 56 and 58 are arranged in an alternating matter and adjacent one another within capacitor region 18 and capacitor region 18 includes no other electrical components therein.
- capacitor region 18 includes no pickup devices 30 situated over and contacting lower capacitor plate 10 .
- Two pickup devices 30 are disposed over and contacting lower capacitor plate 10 in regions outside capacitor region 18 .
- Capacitors 52 and 54 are coupled to respective gates (not shown) and the gates are coupled to a signal source or multiple signal sources that provide separate signals to the respective gates as described above and therefore separate signals to capacitors 52 , 54 .
- each upper capacitor plate 56 , 58 includes only two conductive or semiconductive layers.
- Upper capacitor plates 56 include two conductive or semiconductive layers 60 coupled by vias 62 and upper capacitor plates 58 each include two conductive or semiconductive layers 66 coupled by vias 68 .
- Conductive or semiconductive layers 60 may be the same as conductive or semiconductive layers 66 .
- each upper capacitor plate is formed of three stacked conductive plates with interconnecting vias.
- FIGS. 2A and 2B show pickup devices 30 disposed on and directly coupled to lower capacitor plate 10 by contacts 40 and disposed outside capacitor region 18 . In the illustrated embodiment of FIG.
- pickup device 30 is formed of only a single conductive layer which may be polysilicon or various suitable metals but pickup device 30 is formed of various levels of conductive materials in various embodiments.
- FIG. 2B also shows guard ring 70 formed within surface 16 of semiconductor substrate 48 and guard ring 70 completely or at least partially surrounds lower capacitor plate 10 .
- Guard ring 70 is formed of vias and stacked metal layers in some embodiments. The depiction of both pickup device 30 and guard ring 70 in FIG. 2B represents one embodiment only and in other embodiments, only one of pickup device 30 and guard ring 70 is used and in still other embodiments, neither of pickup device 30 and guard ring 70 is used.
- lower capacitor plate 10 is an N-well region.
- lower capacitor plate 10 is a P-well formed within an N-well or deep N-well region 50 in semiconductor substrate 48 .
- Lower capacitor plate 10 is formed of other materials in other embodiments.
- FIGS. 3A and 3B illustrate another arrangement of a differential MOS capacitor according to the disclosure.
- FIGS. 3A and 3B show capacitors 76 and 78 that combine to form the differential MOS capacitor.
- Capacitor 76 includes upper capacitor plates 80 and capacitor 78 includes upper capacitors plates 82 .
- Upper capacitor plates 80 and 82 are all within rectangular capacitor region 18 .
- Capacitor region 18 does not include pickup devices 30 or any other electrical components therein.
- the upper capacitor plates 80 from capacitor 76 are immediately adjacent one another and internally adjacent upper capacitor plates 82 of capacitor 78 .
- FIGS. 3A and 3B also show an embodiment in which the upper capacitor plates 80 , 82 are disposed sequentially adjacent one another along a direction within capacitor region 18 (extending left to right in the illustrated embodiment) which includes no further electrical components therein.
- FIG. 4 shows another embodiment of a differential MOS capacitor according to the disclosure.
- capacitors 86 , 88 each include more than two upper capacitor plates.
- capacitors 86 , 88 may alternatively be considered to represent respective capacitor sections of a differential MOS capacitor.
- Capacitor 86 includes four upper capacitor plates 90 and capacitor 88 includes four upper capacitor plates 92 .
- Each capacitor 86 , 88 is coupled to a gate and a signal source, not shown in FIG. 4 .
- FIG. 4 also illustrates an embodiment in which upper capacitor plates 90 , 92 are disposed sequentially adjacent one another within capacitor region 18 that includes no other electrical components therein.
- capacitor region 18 is void of pickup devices 30 which are, instead, disposed external to capacitor region 18 .
- the arrangements shown in FIGS. 1A , 1 B, 2 A, 2 B, 3 A, 3 B and FIG. 4 are examples of the various arrangements according to the disclosure in which two or more capacitors, each having two or more upper capacitor plates disposed over a common node, are formed in a capacitor region in which no further electrical components are situated.
- Various other arrangements in which two capacitors, each having two or more upper capacitor plates disposed over a common node, i.e., over a common lower capacitor plate, are used in other embodiments in which the capacitors combine to form a differential MOS capacitor.
- the upper capacitor electrodes are disposed adjacent one another in a region, i.e., capacitor region 18 , that does not include pickup devices or other electrical components within a capacitor region 18 .
- pickup devices are disposed outside the capacitor region and in other embodiments, a guard ring at least partially surrounds the lower capacitor plate.
- FIG. 5 shows another embodiment of a differential MOS capacitor according to the disclosure.
- FIG. 5 shows another exemplary arrangement and shows two differential MOS capacitors.
- Each differential MOS capacitor includes one capacitor 96 having upper capacitor plates 100 and one capacitor 98 having upper capacitor plates 102 .
- Each capacitor 96 , 98 is coupled to a gate and a common or dedicated signal source, as in the embodiment illustrated in FIG. 1A .
- the upper capacitor plates, 100 or 102 of a particular capacitor are disposed adjacent one another with no other electrical components such as pickup devices 30 , between the upper capacitor plates.
- pickup devices 30 are regularly spaced between capacitors 96 and 98 within lower capacitor plate 10 .
- Pickup devices couple lower capacitor plate 10 to ground.
- pickup devices 30 are not used and a guard ring such as guard ring 70 is used. In some embodiments, both pickup devices 30 and guard ring 70 are used.
- a differential MOS capacitor semiconductor device comprises: a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes coupled to the first gate; a second capacitor section coupled to a second gate and including a plurality of second capacitor upper electrodes coupled to the first gate; a conductive plate that serves as a common bottom capacitor plate for each of the first and second capacitor sections and is formed in or on a substrate surface, wherein the plurality of first capacitor upper electrodes and the plurality of second capacitor upper electrodes are each disposed over the common bottom capacitor plate. In some embodiments, no further electrical components are interposed between the capacitor upper electrodes.
- a differential MOS capacitor semiconductor device comprises: a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes; a second capacitor section coupled to a second gate and including a plurality of second capacitor upper electrodes; and a conductive plate that serves as a common bottom capacitor plate for each of the first and second capacitor sections, is disposed in or on a substrate surface, and includes an enclosed capacitor region thereover.
- the capacitor region includes the plurality of first capacitor upper electrodes and the plurality of second capacitor upper electrodes. In some embodiments, no further electrical components are within the capacitor region.
- a differential MOS capacitor semiconductor device comprises: a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes disposed over a common bottom capacitor plate; a second capacitor section coupled to a second gate and including a duality of second capacitor upper electrodes disposed over the common bottom capacitor plate; the common bottom capacitor plate comprising a conductive plate disposed in a semiconductor substrate.
- the first gate is coupled to a first AC signal source; and the second gate is coupled to a second AC signal source.
- the first signal source delivers first signals that are in phase or out of phase with second signals delivered from the second AC signal source.
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Abstract
A differential MOS capacitor structure includes two capacitor sections coupled to different gates and operating using different signals. The respective signals may be 180° out of phase. The capacitor sections of the differential capacitor each include two or more upper capacitor plates disposed over a single common lower capacitor plate which serves as a common node thereby preventing parasitic capacitance. The upper capacitor plates of a first capacitor section are adjacent one another with no electrical components disposed between them. The upper capacitor plates of a second capacitor section are adjacent one another with no electrical components disposed between them. The upper capacitor plates are formed of a plurality of stacked conductive layers in some embodiments.
Description
- The disclosure relates to differential MOS capacitor devices and methods for forming the same.
- Differential capacitor devices such as differential MOSCAP devices are widely used in various applications and in various devices in the electronics industry. These semiconductor devices are fabricated using MOS, metal oxide semiconductor, manufacturing techniques, materials and principles. Differential capacitor devices include multiple capacitor sections or multiple capacitor plates or regions, and the different capacitor sections or different capacitor plates or regions can include different capacitances. Capacitance can be increased in one capacitor section of the MOS capacitor and decreased in another capacitor section of the MOS capacitor during operation, for example. Variable capacitances can be applied and the MOS capacitor devices therefore also serve as MOSVAR devices, i.e. MOS devices with variable reactance, i.e. variable capacitance.
- MOSCAP devices are formed on or over semiconductor substrates using MOS processing operations. One problem that plagues differential capacitors is parasitic capacitance. Parasitic capacitance is present between electronic components or parts because of their proximity to each other. Parasitic capacitance can result between different capacitor electrodes coupled to different gates. Parasitic capacitance can also result between a capacitor electrode and the drain/source pickup devices used to couple various components such as a lower capacitor plate, to ground. Parasitic capacitance can alter the intrinsic capacitance of a capacitor and can also adversely affect the effective capacitance of the operating capacitor of the differential capacitor device. Parasitic capacitance negatively affects device speed and device performance.
- It would therefore be desirable to provide methods and designs for differential MOS capacitor devices that eliminate or prevent parasitic capacitance.
- The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not necessarily to scale. On the contrary, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. Like numerals denote like features throughout the specification and drawing.
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FIG. 1A is a top, plan view of an arrangement of a differential capacitor according to the disclosure andFIG. 1B is a cross-sectional view of a portion of the differential MOS capacitor ofFIG. 1A ; -
FIGS. 2A and 2B are a plan view and a cross-sectional view of another embodiment of a differential MOS capacitor according to the disclosure; -
FIGS. 3A and 3B are a plan view and a cross-sectional view of another embodiment of a differential MOS capacitor according to the disclosure; -
FIG. 4 is a plan, top view of another embodiment of a differential MOS capacitor according to the disclosure; and -
FIG. 5 is a plan, top view of another embodiment of a differential MOS capacitor according to the disclosure. - The disclosure provides a differential MOS capacitor (MOSCAP) with capacitor plates coupled to different gates. The gates can be biased differently. Different signals can be delivered to the gates and in one embodiment, out-of-phase signals are delivered to the gates. The differential MOSCAP includes multiple upper capacitor electrodes disposed over a common lower capacitor electrode which serves as a common node. In some embodiments, the common lower capacitor electrode is a conductive plate such as an N-well formed in a semiconductor substrate. The upper capacitor electrodes are formed over the common lower capacitor electrode in a capacitor region and, in some embodiments, no other electrical components are disposed in the capacitor region and no electrical connections are made to the capacitor region. In some embodiments, the MOSCAP device includes two capacitors or two capacitor sections coupled to two separate gates, with each of the capacitors or capacitor sections including multiple upper capacitor electrodes. In some embodiments, the multiple upper capacitor electrodes of each capacitor gate are adjacent one another, and in some embodiments, the multiple upper capacitor electrodes of both capacitors are disposed adjacent one another. In some embodiments, a guard ring is used and at least partially surrounds the lower conductive plate. In some embodiments, one or more drain/source pickup devices are used to couple the conductive plate serving as a common lower capacitor electrode, to ground.
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FIGS. 1A and 1B show an exemplary arrangement of a differential MOS capacitor according to the disclosure. The differential MOS capacitor includescapacitors gates capacitor 2 andcapacitor 4 may be alternatively referred to and considered to be a capacitor section of a differential MOS capacitor but will be referred to ascapacitors upper capacitor plates 12 andcapacitor 4 includes twoupper capacitor plates 14.Upper capacitor plates capacitor region 18 which is indicated by dashed lines. -
Capacitor region 18 is rectangular in the illustrated embodiment and takes on other shapes in other embodiments.Capacitor region 18 can generally be described as a convex polygon ascapacitor region 18 does not include void areas or indentations within the region.Upper capacitor plates lower capacitor plate 10.Lower capacitor plate 10 is a conductive structure, and in one embodiment,lower capacitor plate 10 is an N-well, or other active area or other conductive area formed within a semiconductor substrate such as withinsurface 16, which is an upper surface ofsemiconductor substrate 48. In other embodiments,lower capacitor plate 10 is formed of different materials and may be formed withinsurface 16 ofsemiconductor substrate 48 or over a semiconductor substrate such assemiconductor substrate 48.Capacitors lower capacitor plate 10 and eachupper capacitor plate Lower capacitor plate 10 represents a common node between the twoupper capacitor plates 12, a common node between the twoupper capacitor plates 14, and also a common node betweenupper capacitor plates lower capacitor plate 10 is a common node forcapacitors -
Upper capacitor plates FIG. 1A , eachupper capacitor plate conductive layer 22, middleconductive layer 24, and upperconductive layer 26 is a metal and in another embodiment, lowerconductive layer 22 is formed of doped or undoped polysilicon, with middleconductive layer 24 and upperconductive layer 26 formed of metal. Vias 28 couple lowerconductive layer 22 to middleconductive layer 24 and also couple middleconductive layer 24 to upperconductive layer 26. Other arrangements are used in other embodiments and in some embodiments, eachupper capacitor plate FIGS. 1A and 1B .Upper capacitor plates FIG. 1A , but other shapes are used in other embodiments. Becauselower capacitor plate 10 is a common node as indicated above,regions 34 are largely void of any parasitic capacitance between the respectiveupper capacitor plates 12 and between theupper capacitor plates 14. Because there are no further electrical components inregions 34, parasitic capacitance betweenupper capacitor plates FIGS. 1A and 1B are formed using various semiconductor manufacturing processes and materials in various embodiments. - Arrow 36 indicates that
capacitors respective capacitors gates source 38 as shown inFIG. 1A . Signalsource 38 delivers AC signals in one embodiment. In one embodiment, signal 42 delivered togate 6 andcapacitor 2, is out of phase withsignal 44 delivered togate 8 andcapacitor 4. In one embodiment, signals 42 and 44 are 180° out of phase. In one embodiment, signals 42 and 44 are sinusoidal signals that are delivered such that a voltage of +1V is delivered to one ofgates gates gates capacitor 2 while the capacitance decreases incapacitor 4, or vice versa. Although asingle signal source 38 is shown inFIG. 1A , in other embodiments, two separate dedicated signal sources are used with a separate signal source dedicated to eachgate signals capacitors - In some embodiments, such as will be shown in
FIGS. 2A and 2B , a guard ring is used to at least partially surroundlower capacitor plate 10. In other embodiments, such as shown inFIGS. 1A and 1B , one ormore pickup devices 30 are used.Pickup devices 30 are drain/source pickup devices and are used to provide a direct connection betweenlower capacitor plate 10 and ground. In one embodiment, allpickup devices 30 are disposed outsidecapacitor region 18. In other embodiments,pickup devices 30 are situated such that they are not interposed betweenupper capacitor plates 12 and such that they are not interposed betweenupper capacitor plates 14. In still other embodiments, pickup devices are not used.Pickup devices 30 are directly coupled tolower capacitor plate 10 bycontacts 40 and are formed of one or more layers of stacked conductive or semiconductor materials such as polysilicon and metal.Pickup devices 30 are coupled to ground using various wires and other conductive interconnect features not shown inFIGS. 1A and 1B . -
FIGS. 2A , 2B show another arrangement of a differential MOS capacitor according to the disclosure. The differential MOS capacitor includescapacitors FIG. 2A ,capacitor 52 includes twoupper capacitor plates 56 andcapacitor 54 includes twoupper capacitor plates 58.Upper capacitor plates capacitor region 18.Upper capacitor plates capacitor region 18 andcapacitor region 18 includes no other electrical components therein. In particular,capacitor region 18 includes nopickup devices 30 situated over and contactinglower capacitor plate 10. Twopickup devices 30 are disposed over and contactinglower capacitor plate 10 in regions outsidecapacitor region 18.Capacitors capacitors - In the cross-sectional view of
FIG. 2B , eachupper capacitor plate Upper capacitor plates 56 include two conductive orsemiconductive layers 60 coupled byvias 62 andupper capacitor plates 58 each include two conductive orsemiconductive layers 66 coupled byvias 68. Conductive orsemiconductive layers 60 may be the same as conductive or semiconductive layers 66. In other embodiments such as was shown inFIG. 1A , 1B, each upper capacitor plate is formed of three stacked conductive plates with interconnecting vias.FIGS. 2A and 2B showpickup devices 30 disposed on and directly coupled tolower capacitor plate 10 bycontacts 40 and disposedoutside capacitor region 18. In the illustrated embodiment ofFIG. 2B ,pickup device 30 is formed of only a single conductive layer which may be polysilicon or various suitable metals butpickup device 30 is formed of various levels of conductive materials in various embodiments.FIG. 2B also showsguard ring 70 formed withinsurface 16 ofsemiconductor substrate 48 andguard ring 70 completely or at least partially surroundslower capacitor plate 10.Guard ring 70 is formed of vias and stacked metal layers in some embodiments. The depiction of bothpickup device 30 andguard ring 70 inFIG. 2B represents one embodiment only and in other embodiments, only one ofpickup device 30 andguard ring 70 is used and in still other embodiments, neither ofpickup device 30 andguard ring 70 is used. In some embodiments,lower capacitor plate 10 is an N-well region. In some embodiments,lower capacitor plate 10 is a P-well formed within an N-well or deep N-well region 50 insemiconductor substrate 48.Lower capacitor plate 10 is formed of other materials in other embodiments. -
FIGS. 3A and 3B illustrate another arrangement of a differential MOS capacitor according to the disclosure.FIGS. 3A and 3B show capacitors Capacitor 76 includesupper capacitor plates 80 andcapacitor 78 includesupper capacitors plates 82.Upper capacitor plates rectangular capacitor region 18.Capacitor region 18 does not includepickup devices 30 or any other electrical components therein. In the arrangements shown inFIGS. 3A , 3B, theupper capacitor plates 80 fromcapacitor 76 are immediately adjacent one another and internally adjacentupper capacitor plates 82 ofcapacitor 78.FIGS. 3A and 3B also show an embodiment in which theupper capacitor plates -
FIG. 4 shows another embodiment of a differential MOS capacitor according to the disclosure. InFIG. 4 ,capacitors capacitors Capacitor 86 includes fourupper capacitor plates 90 andcapacitor 88 includes fourupper capacitor plates 92. Eachcapacitor FIG. 4 .FIG. 4 also illustrates an embodiment in whichupper capacitor plates capacitor region 18 that includes no other electrical components therein. In particular,capacitor region 18 is void ofpickup devices 30 which are, instead, disposed external tocapacitor region 18. The arrangements shown inFIGS. 1A , 1B, 2A, 2B, 3A, 3B andFIG. 4 are examples of the various arrangements according to the disclosure in which two or more capacitors, each having two or more upper capacitor plates disposed over a common node, are formed in a capacitor region in which no further electrical components are situated. Various other arrangements in which two capacitors, each having two or more upper capacitor plates disposed over a common node, i.e., over a common lower capacitor plate, are used in other embodiments in which the capacitors combine to form a differential MOS capacitor. In many embodiments, the upper capacitor electrodes are disposed adjacent one another in a region, i.e.,capacitor region 18, that does not include pickup devices or other electrical components within acapacitor region 18. In some embodiments, pickup devices are disposed outside the capacitor region and in other embodiments, a guard ring at least partially surrounds the lower capacitor plate. -
FIG. 5 shows another embodiment of a differential MOS capacitor according to the disclosure. -
FIG. 5 shows another exemplary arrangement and shows two differential MOS capacitors. Each differential MOS capacitor includes onecapacitor 96 havingupper capacitor plates 100 and onecapacitor 98 havingupper capacitor plates 102. Eachcapacitor FIG. 1A . In each case, the upper capacitor plates, 100 or 102 of a particular capacitor are disposed adjacent one another with no other electrical components such aspickup devices 30, between the upper capacitor plates. In the embodiment ofFIG. 5 ,pickup devices 30 are regularly spaced betweencapacitors lower capacitor plate 10. Pickup devices couplelower capacitor plate 10 to ground. In other embodiments,pickup devices 30 are not used and a guard ring such asguard ring 70 is used. In some embodiments, bothpickup devices 30 andguard ring 70 are used. - According to one aspect, a differential MOS capacitor semiconductor device is provided. The differential MOS capacitor semiconductor device comprises: a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes coupled to the first gate; a second capacitor section coupled to a second gate and including a plurality of second capacitor upper electrodes coupled to the first gate; a conductive plate that serves as a common bottom capacitor plate for each of the first and second capacitor sections and is formed in or on a substrate surface, wherein the plurality of first capacitor upper electrodes and the plurality of second capacitor upper electrodes are each disposed over the common bottom capacitor plate. In some embodiments, no further electrical components are interposed between the capacitor upper electrodes.
- According to another aspect, a differential MOS capacitor semiconductor device is provided. The differential MOS capacitor semiconductor device comprises: a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes; a second capacitor section coupled to a second gate and including a plurality of second capacitor upper electrodes; and a conductive plate that serves as a common bottom capacitor plate for each of the first and second capacitor sections, is disposed in or on a substrate surface, and includes an enclosed capacitor region thereover. The capacitor region includes the plurality of first capacitor upper electrodes and the plurality of second capacitor upper electrodes. In some embodiments, no further electrical components are within the capacitor region.
- According to yet another aspect, a differential MOS capacitor semiconductor device is provided. The differential MOS capacitor semiconductor device comprises: a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes disposed over a common bottom capacitor plate; a second capacitor section coupled to a second gate and including a duality of second capacitor upper electrodes disposed over the common bottom capacitor plate; the common bottom capacitor plate comprising a conductive plate disposed in a semiconductor substrate. The first gate is coupled to a first AC signal source; and the second gate is coupled to a second AC signal source. The first signal source delivers first signals that are in phase or out of phase with second signals delivered from the second AC signal source.
- The preceding merely illustrates the principles of the disclosure. It will thus be appreciated that those of ordinary skill in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the disclosure and are included within its spirit and scope. Furthermore, all examples and conditional language recited herein are principally intended expressly to be only for pedagogical purposes and to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.
- This description of the exemplary embodiments is intended to be read in connection with the figures of the accompanying drawing, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise
- Although the disclosure has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments of the disclosure, which may be made by those of ordinary skill in the art without departing from the scope and range of equivalents of the disclosure.
Claims (23)
1. A differential MOS capacitor semiconductor device comprising:
a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes coupled to said first gate;
a second capacitor section coupled to a second gate and including a plurality of second capacitor upper electrodes coupled to said first gate; and
a conductive plate that serves as a common bottom capacitor plate for each of said first and second capacitor sections and is formed in or on a substrate surface,
wherein said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes are each disposed over said common bottom capacitor plate.
2. The differential MOS capacitor semiconductor device as in claim 1 , wherein no electrical components are interposed between said first capacitor upper electrodes of said plurality of first capacitor upper electrodes; no electrical components are interposed between said second capacitor upper electrodes of said plurality of second capacitor upper electrodes, and no electrical components are interposed between said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes
3. The differential MOS capacitor semiconductor device as in claim 2 , wherein said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes are arranged adjacent one another.
4. The differential MOS capacitor semiconductor device as in claim 1 , wherein said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes are arranged adjacent one another.
5. The differential MOS capacitor semiconductor device as in claim 4 , wherein said plurality of first capacitor upper electrodes comprise a duality of said first capacitor upper electrodes and said plurality of second capacitor upper electrodes comprise a duality of said second capacitor upper electrodes and wherein said first capacitor upper electrodes are juxtaposed and disposed adjacent said duality of second capacitor upper electrodes which are also juxtaposed.
6. The differential MOS capacitor semiconductor device as in claim 4 , wherein said first capacitor upper electrodes and said second capacitor upper electrodes are arranged sequentially adjacent one another along a first direction and one of said plurality of first capacitor upper electrodes is interposed between adjacent second capacitor upper electrodes of said plurality of second capacitor upper electrodes.
7. The differential MOS capacitor semiconductor device as in claim 1 , wherein:
said substrate comprises a semiconductor substrate;
said conductive plate comprises an N-well formed in said substrate surface; and
no electrical components and no electrical connections to said conductive plate are disposed between said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes.
8. The differential MOS capacitor semiconductor device as in claim 1 , wherein said substrate comprises a semiconductor substrate and said conductive plate comprises an N-well formed in said semiconductor substrate.
9. The differential MOS capacitor semiconductor device as in claim 8 , wherein no electrical components are disposed within a convex polygonal region that includes said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes and further comprising a pickup device formed on said conductive plate laterally outside said convex polygonal region, said pickup device coupling said conductive plate to ground.
10. The differential MOS capacitor semiconductor device as in claim 9 , wherein said pickup device couples said conductive plate to ground through at least one electrical wire disposed over said conductive plate.
11. The differential MOS capacitor semiconductor device as in claim 1 , wherein said first gate is coupled to a first AC signal source and said second gate is coupled to a second AC signal source, wherein said first and second signal sources deliver signals that are out of phase.
12. The differential MOS capacitor semiconductor device as in claim 1 , wherein each said first capacitor upper electrode and each said second capacitor upper electrode is formed of polysilicon or a first metal layer of a plurality of metal layers, and
further comprising a guard ring disposed in said substrate surface and at least partially surrounding said conductive plate.
13. The differential MOS capacitor semiconductor device as in claim 1 , wherein each of said first capacitor section and said second capacitor section is a variable capacitance MOS capacitor.
14. The differential MOS capacitor semiconductor device as in claim 1 , wherein each said first capacitor upper electrode and each said second capacitor upper electrode is formed of a plurality of stacked metal layers coupled together with vias.
15. The differential MOS capacitor semiconductor device as in claim 1 , wherein each of said first capacitor upper electrodes and second capacitor upper electrodes are disposed within a capacitor portion of said conductive plate, said capacitor portion having a convex polygonal shape, and wherein no further electrical components are disposed within said capacitor portion.
16. A differential MOS capacitor semiconductor device comprising:
a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes;
a second capacitor section coupled to a second gate and including a plurality of second capacitor upper electrodes; and
a conductive plate that serves as a common bottom capacitor plate for each of said first and second capacitor sections, is disposed in or on a substrate surface, and includes an enclosed capacitor region thereover, said enclosed capacitor region including said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes.
17. The differential MOS capacitor semiconductor device as in claim 16 , wherein said enclosed capacitor region is a convex polygon and includes no further electrical components therein.
18. The differential MOS capacitor semiconductor device as in claim 16 , wherein said substrate comprises a semiconductor substrate, no further electrical components are disposed within said enclosed capacitor region, said conductive plate comprises an N-well formed in said semiconductor substrate, and
further comprising a pickup device formed on said conductive plate laterally outside said capacitor region, said pickup device coupling said conductive plate to ground.
19. The differential MOS capacitor semiconductor device as in claim 16 , wherein:
said first gate is coupled to a first AC signal source and said second gate is coupled to a second AC signal source, said first and second signal sources delivering signals that are out of phase;
each said first and second capacitor upper electrode is formed of a plurality of stacked metal layers coupled together with vias; and
each of said first capacitor section and said second capacitor section is a variable capacitance MOS capacitor.
20. A differential MOS capacitor semiconductor device comprising:
a first capacitor section coupled to a first gate and including a plurality of first capacitor upper electrodes disposed over a common bottom capacitor plate;
a second capacitor section coupled to a second gate and including a plurality of second capacitor upper electrodes disposed over said common bottom capacitor plate;
said common bottom capacitor plate comprising a conductive plate disposed in a semiconductor substrate;
said first gate coupled to a first AC signal source; and
said second gate coupled to a second AC signal source,
wherein said first AC signal source delivers first signals that are in phase or out of phase with second signals delivered from said second AC signal source.
21. The differential MOS capacitor semiconductor device as in claim 20 , wherein no electrical components are interposed between said first capacitor upper electrodes of said plurality of first capacitor upper electrodes; no electrical components are interposed between said second capacitor upper electrodes of said plurality of second capacitor upper electrodes, and no electrical components are interposed between said plurality of first capacitor upper electrodes and said plurality of second capacitor upper electrodes.
22. The differential MOS capacitor semiconductor device as in claim 21 , wherein said first capacitor upper electrodes and said second capacitor upper electrodes are arranged sequentially adjacent one another along a first direction in a capacitor region that includes no further electrical components therein.
23. The differential MOS capacitor semiconductor device as in claim 20 , further comprising a guard ring disposed in said semiconductor substrate and at least partially surrounding said conductive plate, and wherein said first capacitor upper electrodes and said second capacitor upper electrodes each include a plurality of stacked metal layers.
Priority Applications (4)
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US13/660,172 US20140117501A1 (en) | 2012-10-25 | 2012-10-25 | Differential moscap device |
KR1020120149657A KR101415385B1 (en) | 2012-10-25 | 2012-12-20 | Differential moscap device |
TW102133797A TWI512969B (en) | 2012-10-25 | 2013-09-18 | Differential mos capacitor semiconductor device |
US14/594,201 US9385246B2 (en) | 2012-10-25 | 2015-01-12 | Differential MOSCAP device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US13/660,172 US20140117501A1 (en) | 2012-10-25 | 2012-10-25 | Differential moscap device |
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US14/594,201 Division US9385246B2 (en) | 2012-10-25 | 2015-01-12 | Differential MOSCAP device |
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Also Published As
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KR20140052790A (en) | 2014-05-07 |
US20150123244A1 (en) | 2015-05-07 |
TW201417275A (en) | 2014-05-01 |
US9385246B2 (en) | 2016-07-05 |
KR101415385B1 (en) | 2014-07-04 |
TWI512969B (en) | 2015-12-11 |
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