CN108172565A - A kind of MOM capacitor and integrated circuit - Google Patents
A kind of MOM capacitor and integrated circuit Download PDFInfo
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- CN108172565A CN108172565A CN201711444665.1A CN201711444665A CN108172565A CN 108172565 A CN108172565 A CN 108172565A CN 201711444665 A CN201711444665 A CN 201711444665A CN 108172565 A CN108172565 A CN 108172565A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
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- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The application provides a kind of MOM capacitor and integrated circuit, the MOM capacitor include：Substrate；Shielded layer on substrate, shielded layer are flood structure；Positioned at shielded layer away from the cross layered more metal layers in one side of substrate and multilayer oxide layer；Every layer of metal layer includes multiple cross one another first interdigital structures and the second interdigital structure；The first interdigital structure and shielded layer short circuit in more metal layers in the metal layer of shielded layer；It insulate between the second interdigital structure and shielded layer in more metal layers in the metal layer of shielded layer.In the present invention shielded layer at least can between shielding metal leve and substrate apparent surface formed parasitic capacitance, so as to reduce some electrode of MOM capacitor relative to the parasitic capacitance of substrate, so that under homalographic, the capacitance bigger of MOM capacitor, increase the capacitance density of MOM capacitor so that MOM capacitor is more widely applied.
Description
Technical field
The present invention relates to integrated circuit device manufacture technology field more particularly to a kind of MOM capacitor and integrated circuits.
Background technology
Integrated circuit (IC) generally includes various passive devices, and capacitor is the one kind for being widely used in IC in various applications
Common passive device.Two kinds of capacitor arrangements commonly used in the prior art are MIM (metal insulator metal, gold
Category-insulator-metal) capacitor and MOM (metal oxide metal, metal-oxide-metal) capacitor.In general, MIM
Capacitor includes the insulator being added between double layer of metal, and MOM capacitor is a large amount of parallel by what is formed on many metal layers
" finger-shaped material " or electrode form.
In MIM capacitor, since bottom plate shields top plate, so usually parasitic capacitance is smaller, however MIM capacitor exists
Additional mask is needed in manufacturing process, causes its cost of manufacture higher.
Opposite, the making of MOM capacitor can usually be easy to generate metal layer by equipment, and with technology
Development, capacitance density gradually increases, and MOM capacitor is widely used.However compared with MIM capacitor, two electricity of MOM capacitor
The parasitic capacitance of pole is larger, so that the application of MOM capacitor in circuit is restricted.
Invention content
In view of this, the present invention provides a kind of MOM capacitor and integrated circuit, to solve the two of MOM capacitor in the prior art
The problem of parasitic capacitance of a electrode is larger.
To achieve the above object, the present invention provides following technical solution：
A kind of MOM capacitor, including：
Substrate；
Shielded layer on the substrate, the shielded layer are flood structure；
Positioned at the shielded layer away from the cross layered more metal layers in the one side of substrate and multilayer oxide layer；Every layer institute
It states metal layer and includes multiple cross one another first interdigital structures and the second interdigital structure；First in metal layer described in multilayer
Interdigital structure is electrical connected the first electrode as the MOM capacitor, and the second interdigital structure in metal layer described in multilayer is electrical
The second electrode being connected as the MOM capacitor；
The first interdigital structure and the shielded layer in metal layer described in multilayer in the metal layer of the shielded layer
Short circuit；Between the second interdigital structure and the shielded layer in metal layer described in multilayer in the metal layer of the shielded layer
Insulation.
Preferably, the more metal layers the substrate projection in the plane be located at the shielded layer in the lining
Bottom in projection in the plane.
Preferably, the shielded layer is polysilicon layer.
Preferably, the polysilicon layer is metal silication polysilicon layer.
Preferably, the shielded layer is metal layer.
Preferably, the shielded layer the substrate projection in the plane edge than the more metal layers in institute
State substrate the edge of projection in the plane extend out at least 2 microns.
Preferably, the shielded layer the substrate projection in the plane edge than the more metal layers in institute
State substrate the edge of projection in the plane extend out 2 microns.
The present invention also provides a kind of integrated circuit, including：MOM capacitor described in any of the above one.
Preferably, the integrated circuit is charge pump.
Preferably, the charge pump is cross-couplings charge pump.
It can be seen via above technical scheme that MOM capacitor provided by the invention, by between substrate and more metal layers
Form the shielded layer of a flood, the shielded layer at least being capable of apparent surface is formed between shielding metal leve and substrate parasitism electricity
Hold, so as to reduce some electrode of MOM capacitor relative to the parasitic capacitance of substrate, so that under homalographic, MOM electricity
The capacitance bigger of appearance increases the capacitance density of MOM capacitor so that MOM capacitor is more widely applied.
The present invention also provides a kind of integrated circuit, the integrated circuit includes MOM capacitor recited above, due to MOM electricity
The a certain termination electrode held becomes smaller relative to the parasitic capacitance of substrate, so as to application in integrated circuits so that integrated circuit
Parasitic capacitance reduce.
Description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention, for those of ordinary skill in the art, without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is MOM capacitor schematic three dimensional views of the prior art；
Fig. 2 is the schematic cross-section of MOM capacitor of the prior art；
Fig. 3 is the simple equivalent circuit schematic diagram of MOM capacitor in the prior art；
Fig. 4 is the schematic cross-section of MOM capacitor provided in the embodiment of the present invention；
Fig. 5 is the simple equivalent circuit schematic diagram of MOM capacitor provided in the embodiment of the present invention；
Fig. 6 is the schematic cross-section of another MOM capacitor provided in the embodiment of the present invention；
Fig. 7 is the schematic cross-section of another MOM capacitor provided in the embodiment of the present invention；
Fig. 8 is the charge pump equivalent circuit diagram for not considering parasitic capacitance in the prior art；
Fig. 9 a are the charge pump equivalent circuit diagram for considering parasitic capacitance in the prior art；
Fig. 9 b are the charge pump equivalent circuit diagram provided in the embodiment of the present invention；
The timing control figure that Figure 10 is Fig. 8, is switched in equivalent circuit diagram shown in Fig. 9 a, Fig. 9 b；
Figure 11 is the cross-couplings charge pump equivalent circuit diagram for not considering parasitic capacitance in the prior art；
Figure 12 a are the cross-couplings charge pump equivalent circuit diagram for considering parasitic capacitance in the prior art；
Figure 12 b are the cross-couplings charge pump equivalent circuit diagram provided in the embodiment of the present invention；
Figure 13 is Figure 11, clock signal timing control figure in Figure 12 a, equivalent circuit diagram shown in Figure 12 b.
Specific embodiment
Just as described in the background section, the parasitic capacitance of MOM capacitor is larger in the prior art.
Inventor has found that it is to refer to Fig. 1 the reason of this phenomenon occur, and Fig. 1 is the stacked metallization of MOM capacitor 100
The three dimensional representation of structure, MOM capacitor 100 are included in multiple metal layer M1-M6, wherein, M1 is the first layer metal of MOM capacitor,
M2 is second layer metal, and Mn is n-th layer metal, includes cross one another finger-shaped material 110 and 120 in every layer of metal layer.It is different
Interdigitated 110 on metal layer M1-M6 is connected with 120 by multiple through-holes, and can be by oxide skin(coating) (not shown)
It separates.Interdigitated 110 in each layer metal layer is interconnected to form the first electrode A of MOM capacitor, interdigital in more metal layers
Shape 120 is interconnected to form the second electrode B of MOM capacitor.
Refer to Fig. 2, Fig. 2 is the sectional view of MOM capacitor 100, and the capacitance in MOM capacitor is by between same layer metal sidewall
The capacitance of formation.As shown in Figure 2, also there are larger parasitic capacitances in MOM capacitor, and the parasitic capacitance is mainly by finger-shaped material
It is formed between 110 and 120 bottom surface and side and the upper surface of substrate 01.It should be noted that the first metal layer M1 is from lining
Bottom is nearest, therefore the parasitic capacitance between substrate 01 is maximum, and each metal layer above the first metal layer M1
M2 ... Mn are due to the blocking of the first metal layer M1, and the parasitic capacitance relative to substrate 01 is smaller, relative to the first metal layer M1
It ignores with the parasitic capacitance of substrate 01.
As shown in Figure 2, the first metal layer M1 includes two parts to the parasitic capacitance of substrate 01：A part is the first metal
The bottom surface of layer M1 forms parallel plate electrode capacitance with 01 face part of substrate, and another part is the side wall and substrate of the first metal layer M1
Between form sidewall capacitance, the actually capacitance of parallel plate electrode capacitance is bigger than the capacitance of sidewall capacitance.Both parasitic electricity
Rong it is total be denoted as Cp1, and as first electrode A with second electrode B is to the parasitic capacitance size of substrate 01, respectively account for Cp1/2,
That is in Fig. 3, Cp=Cp1/2.Fig. 3 is the simple equivalent circuit schematic diagram of Fig. 2, wherein, capacitance Cmom is the practical institute of MOM capacitor
The MOM capacitor used is needed, Cp is to be not intended to existing parasitic capacitance, it should be noted that the ground terminal in Fig. 3 is in Fig. 2
Substrate 01, in actual use, substrate 01 is grounded, therefore substrate is equivalent to ground terminal.From the prior art may be used
To learn two electrodes relative to substrate there are parasitic capacitance, and parasitic capacitance is larger.
Based on this, the present invention provides a kind of MOM capacitor, including：
Substrate；
Shielded layer on the substrate, the shielded layer are flood structure；
Positioned at the shielded layer away from the cross layered more metal layers in the one side of substrate and multilayer oxide layer；Every layer institute
It states metal layer and includes multiple cross one another first interdigital structures and the second interdigital structure；First in metal layer described in multilayer
Interdigital structure is electrical connected the first electrode as the MOM capacitor, and the second interdigital structure in metal layer described in multilayer is electrical
The second electrode being connected as the MOM capacitor；
The first interdigital structure and the shielded layer in metal layer described in multilayer in the metal layer of the shielded layer
Short circuit；Between the second interdigital structure and the shielded layer in metal layer described in multilayer in the metal layer of the shielded layer
Insulation.
MOM capacitor provided by the invention, it is described by forming the shielded layer of a flood between substrate and more metal layers
Shielded layer at least can between shielding metal leve and substrate apparent surface formed parasitic capacitance, so as to reduce MOM capacitor
Parasitic capacitance, so that under homalographic, the capacitance bigger of MOM capacitor increases the capacitance density of MOM capacitor so that MOM
Capacitance is more widely applied.
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment shall fall within the protection scope of the present invention.
Refer to Fig. 4, Fig. 4 is a kind of MOM capacitor cross section structure schematic diagram provided in the embodiment of the present invention, the MOM
Capacitance includes：
Substrate 1；
Shielded layer 2 on the substrate 1, the shielded layer 2 are flood structure；
Positioned at the shielded layer 2 away from the cross layered more metal layers (Mm ... Mn) in 1 side of substrate and multilayer
Oxide layer (not shown)；It is interdigital that every layer of metal layer includes multiple cross one another first interdigital structure A0 and second
Structure B0；The first interdigital structure in metal layer described in multilayer is electrical connected the first electrode A as the MOM capacitor, multilayer
The second interdigital structure in the metal layer is electrical connected the second electrode B as the MOM capacitor；
The first interdigital structure in metal layer described in multilayer (Mm ... Mn) in the metal layer Mm of the shielded layer 2
A0 and 2 short circuit of shielded layer；In metal layer described in multilayer (Mm ... Mn) in the metal layer Mm of the shielded layer 2
It insulate between second interdigital structure B0 and the shielded layer 2.
As shown in Figure 4, between the first interdigital structure A0 in the one layer of metal layer Mm in bottom and shielded layer 2 directly electrically
It connects, insulate between the second interdigital structure B0 and shielded layer 2 in the one layer of metal layer Mm in bottom, form capacitance.
As shown in figure 5, for MOM capacitor equivalent circuit diagram provided in an embodiment of the present invention, wherein ground terminal is also this reality
Apply substrate 1 shown in Fig. 4 in example.Capacitance Cmom between first electrode A and second electrode B is multiple same layers in MOM capacitor
The capacitance that the side wall of interdigital structure is formed.Shielded layer 2 and second interdigital is further included in Fig. 4 between first electrode A and second electrode B
The capacitance Cp2 formed between structure B0.And because of first electrode A and 2 direct short circuit of shielded layer, posting between shielded layer 2 and substrate 1
Raw capacitance is also the parasitic capacitance Cp3 between first electrode A and ground terminal.
The equivalent circuit diagram of comparison diagram 5 and Fig. 3, it can be seen that MOM capacitor provided in an embodiment of the present invention, due to shielding
The presence of layer, the parasitic capacitance Cp in Fig. 3 between second electrode B and substrate 1 is masked, which disappears.And the
Parasitic capacitance Cp2 in parallel is also added between one electrode A and second electrode B, according to capacitance principle of parallel, increases the first electricity
Capacitance between pole A and second electrode B namely the capacitance for increasing MOM capacitor.It should be noted that first electrode A with
Parasitic capacitance Cp3 is further included between substrate, but in actual application, such as charge pump example shown below of the invention
In, first electrode A is relative to the parasitic capacitance Cp3 of substrate can be received.As long as the so that parasitic capacitance of second electrode B
Reduce or disappear.
It should be noted that the material of the shielded layer is not limited in the present embodiment, as long as with certain electric conductivity, energy
It is enough to form parasitic capacitance with metal layer disposed thereon, and can short circuit, so as to posting between metal layer and substrate
Raw capacitance reduces.Optional in the present embodiment, the shielded layer is the smaller polysilicon layer of impedance ratio or metal layer.
More metal layers can be formed in integrated circuit fabrication process, is directed toward away from the direction of substrate by substrate, wrapped successively
The first metal layer M1, second metal layer M2 ... the n-th metal layer Mn are included, shielded layer described in the present embodiment can be the multilayer
A certain layer structure in metal layer.
Fig. 6 is referred to, Fig. 6 is that the first metal layer M1 in integrated circuit is made as flood structure, is used to form this hair
Shielded layer 12 in bright embodiment, at this point, since the first metal layer M1 forms parasitic electricity between flood structure, with substrate 11
Hold Cp3, and parasitic capacitance Cp2 is formed with the second interdigital structure in the second metal layer M2 above it, with the first interdigital structure
Direct short circuit.
In addition, in the present embodiment can also using other metal layers as shielded layer, at this point, positioned at the shielded layer and substrate it
Between metal layer be not present, can not be used as the interdigital structure of MOM capacitor.The utilization rate of metal layer reduces in this way.
For this purpose, in another embodiment of the present invention, setting polysilicon can also be increased between more metal layers and substrate
Layer is used as shielded layer, it should be noted that and " increase " described in the present embodiment is not individually to make one layer of polysilicon layer again,
But the polysilicon layer in integrated circuit in the prior art is used as the shielded layer in the present embodiment, if such as in integrated circuit
There are metal-oxide-semiconductor, then polysilicon layer when making the grid of metal-oxide-semiconductor may extend to MOM capacitor substrate described in the present embodiment
Top is used as shielded layer, will be also used as in the present embodiment without the gate polysilicon layer of other effects in the prior art
The shielded layer of MOM capacitor, in manufacture craft, there is no the making steps for increasing MOM capacitor in the present embodiment.
Refer to Fig. 7, Fig. 7 is structure of the polysilicon layer as shielded layer, at this point, polysilicon layer 22 is located at substrate 21 and the
Between one metal layer M1.Relative to MOM capacitor shown in fig. 5, the metal layer of MOM capacitor is occupied in the present embodiment and not,
So that the capacitance bigger of MOM capacitor.
The type of the polysilicon is not limited in the present embodiment, optionally, the polysilicon layer is smaller for square resistance value
Metal silication polysilicon (silicided poly-Si), so that the resistance of shielded layer totality is smaller, shield effectiveness is preferable.
The size of the shielded layer is not limited in above example of the present invention, as long as second in metal layer can be pitched
Referring to shielded layer that the parasitic capacitance between structure and substrate masks can be with.It should be noted that when shielded layer is smaller, position
Parasitic capacitance between the side wall and substrate of the second interdigital structure of marginal position is not it is possible that shielding is fallen, so that MOM
Parasitic capacitance between the second electrode and substrate of capacitance cannot be shielded completely.
In order to which the parasitic capacitance between the second electrode of MOM capacitor and substrate (is formed including bottom surface and substrate
The parasitic capacitance that parasitic capacitance and side wall are formed with substrate), more metal layers described in the present embodiment are where the substrate
Projection in plane be located at the shielded layer in the substrate in projection in the plane.
To avoid shielded layer area excessive, the influence to other devices in integrated circuit is caused, is shielded described in the present embodiment
Cover layer the substrate projection in the plane edge than the more metal layers the substrate throwing in the plane
The edge of shadow extends out at least 2 microns.Preferably, the shielded layer can be caused in substrate institute in the plane in manufacturing process
Projection edge than the more metal layers the substrate the edge of projection in the plane extend out 2 microns, this implementation
This is not limited in example, can selection design be carried out according to the component in the making of practical integrated circuit and integrated circuit.
MOM capacitor provided by the invention, it is described by forming the shielded layer of a flood between substrate and more metal layers
Shielded layer at least can between shielding metal leve and substrate apparent surface formed parasitic capacitance, so as to reduce MOM capacitor
Parasitic capacitance, so that under homalographic, the capacitance bigger of MOM capacitor increases the capacitance density of MOM capacitor so that MOM
Capacitance is more widely applied.
The present invention also provides a kind of integrated circuit, the integrated circuit includes the MOM described in all above embodiment
Capacitance.
It should be noted that the concrete structure of integrated circuit is not limited in the present embodiment, as long as integrated circuit includes MOM
The MOM capacitor with shielded layer described in above example of the present invention may be used in capacitance, so as to reduce one of electricity
Extremely to the parasitic capacitance of substrate, increase the capacitance of MOM capacitor.
The advantages of in order to more preferably illustrate the MOM capacitor provided in above example of the present invention, with institute in the embodiment of the present invention
Integrated circuit is stated to illustrate for charge pump.Using the MOM capacitor with shielded layer, the efficiency of charge pump can be improved.Specifically
It is as follows：
Refer to Fig. 8, Fig. 9 a, Fig. 9 b and Figure 10, wherein, Fig. 8 be charge pump equivalent circuit diagram of the prior art, Fig. 9 a
For the charge pump equivalent circuit diagram after consideration parasitic capacitance, Cmom is MOM capacitor.Fig. 9 b are an electricity for shielding MOM capacitor
Charge pump equivalent circuit diagram after extreme parasitic capacitance；Figure 10 is Fig. 8, is switched in equivalent circuit diagram shown in Fig. 9 a, Fig. 9 bWithTiming control figure.
Ignore switching loss, ideally, the charge efficiency of pump shown in Fig. 8 is up to 100%, output voltage for clock：
Vcpout=2*Vdd
In fig. 9 a, MOM capacitor can influence the charge efficiency of pump in the parasitic capacitance Cp of second electrode B ends over the ground：
Between high period, the first electrode A points of MOM capacitor are connected to ground, and second electrode B points are charged to Vdd, the
2 electrode B points storage total electrical charge be：
For Φ 2 between high period, the first electrode A points of MOM capacitor are connected to VDD, second electrode B points connection Cpout, and second
The parasitic capacitance Cp both end voltages of electrode B point by Vdd (Between high period) become Vcpout (Between high period),
Second electrode B point total electrical charges are：
B point charge conservations, therefore：
That is,
(Cmom+Cp) * Vdd=Cmom* (Vout-Vdd)+Cp*Vout
It obtains
If Cp/Cmom=0.1, Vout=1.91*Vdd, the efficiency of charge pump is 95.5%.
As it can be seen that the size of parasitic capacitance of the efficiency of charge pump by second electrode B over the ground is influenced.
The MOM capacitance structure with shielded layer described in above example of the present invention is employed in Fig. 9 b, MOM capacitor
Second electrode B ends are over the ground without Cp=0 in parasitic capacitance namely above formula, and the charge efficiency of pump is unaffected, and similary face
Under product, more Cp2 between first electrode A and second electrode B is in parallel with original MOM capacitor so that MOM capacitor density increases
(wherein, the parasitic capacitance Cp3 of A ends over the ground does not influence the charge efficiency of pump).
As it can be seen that the efficiency of charge pump can be improved using the MOM capacitor with shielded layer described in the embodiment of the present invention,
Increase the capacitance of MOM capacitor so that under homalographic, MOM capacitor density increases.
A kind of cross-couplings charge pump, structure such as Figure 11, Figure 12 a, Figure 12 b are also provided in another embodiment of the present invention
Shown in Figure 13, wherein, Figure 11 is charge pump equivalent circuit diagram of the prior art, and Figure 12 a are the electricity considered after parasitic capacitance
Lotus pumps equivalent circuit diagram, and Cmom is MOM capacitor.Figure 12 b are the electricity after the parasitic capacitance for an electrode tip for shielding MOM capacitor
Lotus pumps equivalent circuit diagram；Figure 13 is Figure 11, in Figure 12 a, equivalent circuit diagram shown in Figure 12 b clock signal Clk1 and Clk2 when
Sequence control figure；
Specifically, Figure 11 be using two flying capacitances charge pump construction (flying capacitances refer to quick charge capacitor,
Be exactly capacitance in capacitance C1 and the capacitance C2, Fig. 8 in Figure 11 between A and B it is also flying capacitances), to open in the present embodiment
It is NMOS to close pipe M1 and switching tube M3, and switching tube M2 and M4 are illustrated for switching tube PMOS.
Ignore switching loss, ideally, the charge efficiency of pump is clock up to 100%, output voltage：
Vout=Vin+Vdd
Similarly according to principle of charge conservation, Figure 12 a can be derived, have parasitic capacitance Cp's over the ground in node M and N
When, charge pump output voltage is：
Parasitic capacitance Cp influences the charge efficiency of pump.
And as shown in Figure 12b, the MOM capacitance structure with shielded layer described in above example of the present invention is employed,
The parasitism of M and N points over the ground can be shielded, but the parasitic capacitance pair of clock incoming end Clk1 and clock incoming end Clk2 over the ground
The charge efficiency of pump has substantially no effect on, it is only necessary to increase reverser size, reverser is made to have enough driving forces.
Therefore, electricity can be improved using the MOM capacitor with shielded layer described in the embodiment of the present invention in the present embodiment
The efficiency of lotus pump increases the capacitance of MOM capacitor so that under homalographic, MOM capacitor density increases.
It should be noted that each embodiment in this specification is described by the way of progressive, each embodiment weight
Point explanation is all difference from other examples, and just to refer each other for identical similar part between each embodiment.
The foregoing description of the disclosed embodiments enables professional and technical personnel in the field to realize or use the present invention.
A variety of modifications of these embodiments will be apparent for those skilled in the art, it is as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and the principles and novel features disclosed herein phase one
The most wide range caused.
Claims (10)
1. a kind of MOM capacitor, which is characterized in that including：
Substrate；
Shielded layer on the substrate, the shielded layer are flood structure；
Positioned at the shielded layer away from the cross layered more metal layers in the one side of substrate and multilayer oxide layer；Every layer of gold
Belong to layer and include multiple cross one another first interdigital structures and the second interdigital structure；First in metal layer described in multilayer is interdigital
Structure is electrical connected the first electrode as the MOM capacitor, and the second interdigital structure in metal layer described in multilayer is electrical connected
Second electrode as the MOM capacitor；
The first interdigital structure and the shielded layer short circuit in metal layer described in multilayer in the metal layer of the shielded layer；
It insulate between the second interdigital structure and the shielded layer in metal layer described in multilayer in the metal layer of the shielded layer.
2. MOM capacitor according to claim 1, which is characterized in that more metal layers plane where the substrate
On projection be located at the shielded layer in the substrate in projection in the plane.
3. MOM capacitor according to claim 2, which is characterized in that the shielded layer is polysilicon layer.
4. MOM capacitor according to claim 3, which is characterized in that the polysilicon layer is metal silication polysilicon layer.
5. MOM capacitor according to claim 2, which is characterized in that the shielded layer is metal layer.
6. according to the MOM capacitor described in claim 2-5 any one, which is characterized in that the shielded layer is in the substrate institute
The edge of projection in the plane than the more metal layers the substrate the edge of projection in the plane extend out at least 2
Micron.
7. MOM capacitor according to claim 6, which is characterized in that the shielded layer in the substrate in the plane
The edge of projection than the more metal layers the substrate the edge of projection in the plane extend out 2 microns.
8. a kind of integrated circuit, which is characterized in that including：MOM capacitor described in claim 1-7 any one.
9. integrated circuit according to claim 8, which is characterized in that the integrated circuit is charge pump.
10. integrated circuit according to claim 9, which is characterized in that the charge pump is cross-couplings charge pump.
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| CN201711444665.1A CN108172565B (en) | 2017-12-27 | 2017-12-27 | MOM capacitor and integrated circuit |
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| CN201711444665.1A CN108172565B (en) | 2017-12-27 | 2017-12-27 | MOM capacitor and integrated circuit |
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| CN108172565B CN108172565B (en) | 2020-12-11 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| EP4447106A1 (en) * | 2023-03-30 | 2024-10-16 | ABLIC Inc. | Capacitive element and semiconductor device |
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| CN108172565B (en) | 2020-12-11 |
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