CN114566490A - MSM capacitor structure with vertical layout and manufacturing method thereof - Google Patents

Abstract

The invention discloses a vertical layout MSM capacitor structure and a manufacturing method thereof, which can be applied to various semiconductor integrated/packaging structures with medium and small capacitance values and miniaturization requirements. The capacitor comprises two flat metallized through grooves or blind grooves inserted into a semiconductor medium substrate, wherein the two flat metallized through grooves, blind grooves or buried grooves which are vertical to the surface of the semiconductor medium substrate and are separated by a medium partition wall S1 are formed at specific positions of the semiconductor medium substrate, and a medium partition wall of an MSM capacitor structure which is vertically distributed on the upper surface and the lower surface of the semiconductor medium substrate forms a medium layer of a capacitor; two rectangular through grooves, blind grooves or embedded grooves which are parallel to each other are embedded with metal electrode plates P1 and P2 which form homoepitaxy of a capacitor body, the two metal electrode plates extend to two ends of a dielectric partition wall S1 through metal layer microstrip connecting lines etched on the surface of a semiconductor dielectric substrate to form an electrode structure led out from MSM capacitor leading-out ends L1 and L2, and therefore the MSM capacitor equivalent circuit structure in vertical layout is formed.

Description

Vertical layout MSM capacitor structure and fabrication method thereof

technical field

The invention relates to the fields of microwave technology and wireless communication technology, an embedded integrated three-dimensional plate capacitor structure, in particular a representative metal-semiconductor- Metal (MSM), ie MSM=metal-semiconductor-metal vertical capacitor structure, and also relates to a manufacturing method of the MSM capacitor.

Background technique

限制了平行金属极板/层的尺寸，造成容值扩充与小型化的必然矛盾。而第4)类金属-绝缘体-金属(MIM)电容形态虽然解决了容值扩充与小型化的矛盾，但MIM结构中绝缘体(I)层的制备成型势必为基于半导体的一体化三维集成技术引入额外的工艺和风险。因此，如何在保证不引入额外材料、制备工艺和风险的前提下，有效缩减电容XY平面布局尺寸，进而满足电路小型化和一体化高性能集成设计需求，成为当前亟待突破的关键技术。In the current 2D/2.5D/3D integrated circuit/package design, capacitors with different capacitance values and packages are widely used in functional links such as decoupling, bypass, DC blocking, resonance, and energy storage. Existing capacitor forms mainly include: 1) electrolytic capacitors, tantalum capacitors, monolithic capacitors, ceramic capacitors, etc. traditionally installed on the surface of the plate or package; 2) small and medium-sized capacitors installed in the cavity for easy interconnection or gold wire bonding Capacitance chip capacitors; 3) Z-direction stacked MIM capacitors or wafer-level integrated capacitors based on three-dimensional stacking/package structure, such as low temperature co-fired ceramic LTCC, high temperature co-fired ceramic HTCC, printed circuit board PCB, silicon-based transfer board/MEMS stack, glass-based interposer/MEMS stack, etc.; 4) Metal-insulator-metal MIM capacitors in vertical layout. Type 1) capacitor form is aimed at traditional board-level circuit requirements; type 2), 3) and 4) type capacitor form is mainly aimed at three-dimensional packaging/3D integrated miniaturization design requirements, such as system-in-package SiP, system-on-chip SoC, packaging Antenna AiP, etc. However, compared with the extension in the Z direction, the main contradiction in the miniaturization of chips or modules is still concentrated in the XY plane layout. Compared with the type 1) capacitor type, although the type 2) and 3) type capacitor types can reduce the area occupied by the plane layout to a certain extent and improve the miniaturization performance in the application field of small and medium capacitance values, the calculation formula of the plate capacitance

The size of the parallel metal plates/layers is limited, resulting in the inevitable contradiction between capacitance expansion and miniaturization. While the 4th) metal-insulator-metal (MIM) capacitor morphology solves the contradiction between capacitance expansion and miniaturization, the preparation and molding of the insulator (I) layer in the MIM structure is bound to be introduced into semiconductor-based integrated three-dimensional integration technology. Additional craftsmanship and risk. Therefore, how to effectively reduce the size of the XY plane layout of the capacitor without introducing additional materials, preparation processes and risks, so as to meet the requirements of circuit miniaturization and integrated high-performance integrated design, has become a key technology that needs to be broken through.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a vertical layout metal-semiconductor-metal MSM capacitor structure with a simple structure, which can effectively reduce the XY plane size layout, and the intermediate semiconductor medium is compatible with current On the basis of an integrated three-dimensional integration process, the high-precision design requirements of capacitors can be maintained. Therefore, the present invention also relates to a preparation method of the metal-semiconductor-metal MSM capacitor structure as described below.

The above object of the present invention can be achieved by the following measures. A vertical layout MSM capacitor structure includes: a multilayer semiconductor dielectric substrate stack structure, which is closely attached to the surface of the semiconductor dielectric substrate, and metal layers G1, G2 that are not connected to the capacitor plates. , G1 and G2 can be metal surfaces of any shape, and can be connected or non-connected to each other. It is characterized in that: the semiconductor dielectric substrate is formed with two flat metallized through grooves, blind grooves or buried grooves that are perpendicular to its surface and separated by a dielectric partition wall S1 at a specific position, and the dielectric partition wall S1 constitutes the dielectric layer of the capacitor; Two parallel rectangular through grooves, blind grooves or buried grooves are inlaid with metal electrode plates P1, P2 that constitute the homoepitaxy of the capacitor body. The line extends to both ends of the dielectric partition wall S1 to form an electrode structure drawn from the MSM capacitor terminals L1 and L2, where L1 and L2 can be located on the same surface or different surfaces of the semiconductor dielectric layer, thus forming a vertical layout MSM capacitor equivalent Circuit configuration.

A preparation method for making the vertical layout MSM capacitor structure is characterized by comprising the steps of: making two flat metallized through grooves, blind grooves or buried grooves in a vertical layout parallel to each other on the semiconductor dielectric substrate, and The dielectric partition wall S1 constituting the insulating layer of the MSM capacitor; according to the interconnection relationship of the MSM capacitor structure in the vertical layout, the lead-out microstrip transmission line of the capacitor terminal is etched on the upper/lower metal layer of the dielectric partition wall S1 to form the MSM capacitor lead-out terminal L1 and L2, depositing an adhesion layer on the sidewalls and bottoms of the flat metallized through trenches, blind trenches or buried trenches, and depositing a diffusion barrier layer on the sidewalls and bottoms of the flat metallized through trenches, blind trenches or buried trenches; A seed layer is deposited on the diffusion barrier layers on the sidewalls and bottom of the flat metallized through grooves, blind grooves or buried grooves; electroplating filling metal in the grooves where the seed layer deposition is completed, if the sidewalls are metallized hollow grooves , the electroplating filling operation is not performed.

Compared with the prior art, the present invention has the following beneficial effects:

Aiming at the inherent shape and characteristics of the actual circuit/package substrate, the present invention produces two flat metallized through grooves, blind grooves or buried grooves at a specific position of the semiconductor dielectric substrate perpendicular to its surface and separated by the dielectric partition wall S1. The partition wall S1 constitutes the dielectric layer of the capacitor; two mutually parallel rectangular through grooves, blind grooves or buried grooves are inlaid with metal electrode plates P1 and P2 that constitute the homoepitaxial extension of the capacitor body, and the two metal electrode plates P1 and P2 pass through the semiconductor medium. The metal layer microstrip connection etched on the surface of the substrate is extended to the two ends of the dielectric partition wall S1 to form a vertical layout MSM capacitor structure. It can truly achieve integrated integration of embedded capacitors in the field of small and medium capacitance requirements. In particular, in addition to the interconnection metal and the semiconductor dielectric substrate material, other materials and processes may not be introduced, thereby achieving the beneficial purpose of reducing costs and controlling risks. At the same time, the present invention overcomes the problem that the capacitors in the existing semiconductor integration/package structure cannot be integrated three-dimensionally and effectively reduces the layout size in the XY direction.

Description of drawings

1 is a front view of a vertical layout MSM capacitor structure of the present invention;

Fig. 2 is the top view of Fig. 1;

3 is a schematic diagram of the vertical layout capacitor structure of the present invention for a blind slot flat panel;

4 is a schematic diagram of a single capacitor series interconnection structure;

5 is a schematic diagram of a single capacitor parallel interconnection structure;

FIG. 6 is a schematic diagram of a dual capacitor series interconnection structure;

7 is a schematic diagram of a parallel interconnection structure of dual capacitors;

FIG. 8 is a schematic diagram of a multi-layer stack structure of Embodiment 5 of the MSM capacitor structure of the present invention.

In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

Detailed ways

See Figure 1 and Figure 2. In an illustrative preferred embodiment described below, a vertical layout MSM capacitor structure includes: a multi-layer semiconductor dielectric substrate stack structure, which is closely attached to the surface of the semiconductor dielectric substrate, and metal layers G1, G2 that are not in communication with the capacitor plates, G1 and G2 can be metal surfaces of any shape, and can be connected or non-connected to each other. The semiconductor dielectric substrate is provided with two flat metallized through grooves, blind grooves or buried grooves that are perpendicular to its surface and separated by a dielectric partition wall S1 at a specific position, the dielectric partition wall S1 constitutes the dielectric layer of the capacitor; two parallel to each other Rectangular through grooves, blind grooves or buried grooves are inlaid with metal electrode plates P1 and P2 which constitute the homoepitaxial growth of the capacitor body. Both ends of the partition wall S1 extend to form an electrode structure drawn from the MSM capacitor lead-out terminals L1 and L2, wherein L1 and L2 can be located on the same surface or different surfaces of the semiconductor dielectric layer, thereby forming a vertical layout MSM capacitor equivalent circuit structure.

In an optional embodiment, Embodiment 1:

In the vertical MSM capacitor body structure, the two flat metallized through grooves, blind grooves or buried grooves are in a parallel relationship with each other. The sidewalls of the flat metallized through grooves, blind grooves or buried grooves can be metallized hollow structures or fully filled with metal. solid structure. The dielectric partition wall S1 can be a semiconductor dielectric layer sandwiched between two flat metallized through grooves, blind grooves or buried grooves and adjacent to the sidewalls. The semiconductor dielectric layer and the semiconductor dielectric substrate where it is located are of the same material and integrated Connect the capacitor terminal. L1 and L2 can be in the form of transmission lines such as microstrip line, stripline, coplanar waveguide, etc. Metal layers G1 and G2 that are not in communication with the capacitor plates can be used as ground or otherwise.

Example 2:

See Figure 3. The difference between this embodiment and Embodiment 1 is that the two parallel grooves are buried grooves, that is, one end of the grooves does not extend to communicate with the metal layer. The difference between this embodiment and the process steps of Embodiment 1 is that the process step of performing a buried trench-to-through trench conversion using a backside chemical mechanical polishing CMP process can be omitted.

Example 3:

4 and 5 are schematic front views of the vertical metal-semiconductor-metal MSM capacitor structure connected in series and parallel in an actual circuit, that is, as a demonstration of the actual layout usage of the capacitor structure. The series connection mode is characterized in that, as shown in Embodiment 1, the two capacitor lead-out ends are respectively connected to two parallel metal plate grooves, and the two lead-out ends can be located in the same metal layer, or can be located in different metal layers up and down, and the ground end is connected to the two. The grooves of the parallel metal plates are not connected. The parallel connection method is characterized in that the two capacitor lead-out ends are connected to one of the parallel metal plate grooves, the two lead-out ends can be located in the same metal layer, or can be located in different metal layers up and down, and the other parallel metal plate groove is connected to the ground end. This embodiment exemplifies the layout in which a single vertical metal-semiconductor-metal MSM capacitor performs functions such as DC blocking, filtering, and resonance in an actual circuit.

Example 4:

6 and 7 are a schematic front view of the two vertical metal-semiconductor-metal MSM capacitor structures interconnected in series in an actual circuit and a schematic top view of the parallel interconnection, that is, as a display of the actual layout usage of the capacitor structure . The feature of the series interconnection method is that each of the two capacitors provides a parallel metal plate groove, and communicates with each other through a transmission structure. The metal layer at the bottom of the slot plate; the two lead-out terminals are connected to the grooves of the remaining parallel metal plates, and can be located in the same metal layer or in different metal layers up and down. The parallel connection method is characterized in that each of the two capacitors provides a parallel metal plate groove, and is connected to each other through a transmission structure. The metal layer at the bottom of the slot plate; the two lead ends are respectively connected to the grooves of the parallel metal plates that have been connected to each other, and the two lead ends can be located in the same metal layer or in different metal layers up and down. This embodiment exemplifies the layout in which two or more vertical metal-semiconductor-metal MSM capacitors perform functions such as multi-stage filtering and parallel resonance in an actual circuit.

Example 5:

FIG. 8 is a schematic front view of the layout of the vertical metal-semiconductor-metal MSM capacitor structure in an actual multilayer semiconductor dielectric stack structure, ie, as a demonstration of the actual layout usage of the capacitor structure. The capacitor structure in this embodiment may be any structure layout and lead-out form in Embodiments 1-4, or may be a combination form of any capacitor structure in Embodiments 1-4. Each single-layer structure can be stacked by direct bonding or indirect bonding. The number of layers stacked up and down (N1≥0 or N2≥0, and an integer), stacking methods include but are not limited to thermocompression bonding, eutectic bonding bonding, solid-liquid diffusion bonding and other bonding processes. This embodiment exemplifies the morphological layout of the vertical metal-semiconductor-metal MSM capacitor structure in an actual integrated package design structure.

The present invention has been described in detail above through specific embodiments, but it is not intended to limit the present invention. Without departing from the principle, spirit and principle of the present invention, any modifications, equivalent replacements, deformations and improvements made by persons in the art should be included within the protection scope of the present invention.

Claims (10)

1. A vertical layout MSM capacitor structure, comprising: a multi-layer semiconductor dielectric substrate stack structure, which is closely attached to the surface of the semiconductor dielectric substrate, and the metal layers G1, G2, G1 and G2 that are not connected to each other are connected or disconnected with each other. The metal surface of any shape is characterized in that: a specific position of the semiconductor dielectric substrate is made with two flat metallized through grooves, blind grooves or buried grooves that are perpendicular to its surface and are separated by a dielectric partition wall S1, and the dielectric partition wall S1 constitutes The dielectric layer of the capacitor; two parallel rectangular through grooves, blind grooves or buried grooves are inlaid with metal electrode plates P1, P2 that constitute the homoepitaxy of the capacitor body, and the two metal electrode plates P1, P2 are etched through the surface of the semiconductor dielectric substrate The metal layer microstrip connection extends to both ends of the dielectric partition wall S1 to form an electrode structure drawn from the MSM capacitor terminals L1 and L2, where L1 and L2 are located on the same surface or different surfaces of the semiconductor dielectric layer, thus forming a vertical layout The MSM capacitor equivalent circuit structure. 2. vertical layout MSM capacitor structure as claimed in claim 1, it is characterized in that: two flat metallization through grooves, blind grooves or buried grooves of vertical MSM capacitor body structure are mutually parallel relationship, flat metallization through groove, blind groove Or the sidewall of the buried trench is a metallized hollow structure, or a solid structure filled with metal. 3. The vertical layout MSM capacitor structure of claim 1, wherein the dielectric partition wall S1 is a semiconductor dielectric layer sandwiched between two flat metallized through grooves, blind grooves or buried grooves and adjacent to the sidewalls, The semiconductor dielectric layer and the semiconductor dielectric substrate where it is located are of the same material, and are integrally connected to the capacitor lead-out terminals. 4. vertical layout MSM capacitor structure as claimed in claim 1 is characterized in that: L1 and L2 are microstrip lines, strip line, coplanar waveguide transmission line form, and the metal layers G1 and G2 that are not connected with the capacitor plate are used for land or other uses. 5 . The vertical layout MSM capacitor structure of claim 1 , wherein the two parallel grooves are buried grooves, one end of which is not extended to communicate with the metal layer. 6 . 6. vertical layout MSM capacitor structure as claimed in claim 1, it is characterized in that: two capacitor lead-out ends are connected to two parallel metal plate grooves respectively, and two lead-out ends are located in the same metal layer or are located in different metal layers up and down, the ground end It is not connected with the grooves of the two parallel metal plates: the lead-out terminals of the two capacitors are connected to one of the grooves of the parallel metal plates, and the other groove of the parallel metal plates is connected to the ground. 7. vertical layout MSM capacitor structure as claimed in claim 1 is characterized in that: two capacitors each provide a parallel metal plate groove, and realize mutual communication by transmission structure, and the transmission structure that plays the role of interconnection is located in the groove The metal layer at the top of the electrode plate or the metal layer at the bottom of the groove electrode plate; the two lead-out terminals are connected to the grooves of the remaining parallel metal electrode plates, and are located on the same metal layer or on different metal layers up and down. 8. vertical layout MSM capacitor structure as claimed in claim 1 is characterized in that: two capacitors each provide a parallel metal plate groove, and realize mutual communication by transmission structure, and the transmission structure that plays the role of interconnection is located in the groove The top metal layer of the electrode plate or the metal layer at the bottom of the groove electrode plate; the two lead-out ends are respectively connected to the respective parallel metal plate grooves that have been connected to each other, and the two lead-out ends can be located on the same metal layer or on different metal layers up and down. 9. vertical layout MSM capacitor structure as claimed in claim 1, it is characterized in that: capacitor structure is in arbitrary structure layout and lead-out form, or the mutual combination form of arbitrary capacitor structure, each single-layer structure is by direct bonding or indirect bonding The stacking is completed in the form of upper and lower stacking layers, N1≥0 or N2≥0, which is an integer, and the stacking method includes thermocompression bonding, eutectic bonding, and solid-liquid diffusion bonding. 10. A preparation method for making the vertical layout MSM capacitor structure according to claim 1, characterized in that it comprises the following steps: on the semiconductor dielectric substrate, two flat metallized through grooves, blind metallized through grooves, blind metallization grooves, and two parallel vertical layouts are made on the semiconductor dielectric substrate. slot or buried slot, and constitute the dielectric partition wall S1 of the MSM capacitor insulating layer; according to the interconnection relationship of the MSM capacitor structure in the vertical layout, the lead-out microstrip transmission line of the capacitor lead-out end is etched on the upper/lower metal layer of the dielectric partition wall S1 to form the described MSM capacitor lead-out terminals L1 and L2, deposit an adhesive layer on the sidewalls and bottom of the flat metallized through trenches, blind trenches or buried trenches, and deposit an adhesion layer on the sidewalls and bottoms of the flat metallized through trenches, blind trenches or buried trenches depositing a diffusion barrier layer; depositing a seed layer on the diffusion barrier layer on the sidewall and bottom of the flat metallized through groove, blind groove or buried groove; electroplating filling metal in the groove where the seed layer deposition is completed, if it is a side If the walls are metallized hollow recesses, the electroplating filling operation is not performed.

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