CN114566490A - MSM capacitor structure with vertical layout and manufacturing method thereof - Google Patents
MSM capacitor structure with vertical layout and manufacturing method thereof Download PDFInfo
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- CN114566490A CN114566490A CN202210075871.4A CN202210075871A CN114566490A CN 114566490 A CN114566490 A CN 114566490A CN 202210075871 A CN202210075871 A CN 202210075871A CN 114566490 A CN114566490 A CN 114566490A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
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Abstract
The invention discloses a vertical layout MSM capacitor structure and a manufacturing method thereof, which can be applied to various semiconductor integrated/packaging structures with medium and small capacitance values and miniaturization requirements. The capacitor comprises two flat metallized through grooves or blind grooves inserted into a semiconductor medium substrate, wherein the two flat metallized through grooves, blind grooves or buried grooves which are vertical to the surface of the semiconductor medium substrate and are separated by a medium partition wall S1 are formed at specific positions of the semiconductor medium substrate, and a medium partition wall of an MSM capacitor structure which is vertically distributed on the upper surface and the lower surface of the semiconductor medium substrate forms a medium layer of a capacitor; two rectangular through grooves, blind grooves or embedded grooves which are parallel to each other are embedded with metal electrode plates P1 and P2 which form homoepitaxy of a capacitor body, the two metal electrode plates extend to two ends of a dielectric partition wall S1 through metal layer microstrip connecting lines etched on the surface of a semiconductor dielectric substrate to form an electrode structure led out from MSM capacitor leading-out ends L1 and L2, and therefore the MSM capacitor equivalent circuit structure in vertical layout is formed.
Description
Technical Field
The invention relates to the technical field of microwave technology and wireless communication, in particular to an embedded integrated three-dimensional flat capacitor structure, which is a vertical capacitor structure representing metal-semiconductor-metal (MSM), namely MSM (metal-semiconductor-metal), and can be applied to various semiconductor integrated/packaging structures with medium and small capacitance values and miniaturization requirements.
Background
In the current 2D/2.5D/3D integrated circuit/package design, capacitors with different capacitance values and packages are widely applied to functional links such as decoupling, bypass, blocking, resonance, energy storage and the like. The conventional capacitor mainly includes: 1) electrolytic capacitors, tantalum capacitors, monolithic capacitors, ceramic capacitors and the like which are traditionally arranged on the surface of a plate or a packaging body; 2) the chip capacitor with the medium and small capacitance values is arranged in the cavity body and is convenient for interconnection or gold wire bonding; 3) depending on a Z-direction stacking MIM capacitor or a wafer-level integrated capacitor of a three-dimensional stacking/packaging structure, such as a low-temperature co-fired ceramic LTCC, a high-temperature co-fired ceramic HTCC, a printed circuit board PCB, a silicon-based adapter plate/MEMS stacking, a glass-based adapter plate/MEMS stacking and the like; 4) a vertically arranged metal-insulator-metal MIM capacitor. The type 1) capacitor mode aims at the requirements of the traditional plate-level circuit; the capacitor types 2), 3) and 4) mainly aim at the design requirements of three-dimensional packaging/three-dimensional integration miniaturization, such as system-in-package SiP, system-on-chip SoC, package antenna AiP and the like. However, the main contradiction of chip or module miniaturization compared to the Z-direction extension still focuses on XY-plane layout. Compared with the capacitor form of the 1) type and the capacitor forms of the 2) type and the 3) type, although the occupied area of the plane layout can be reduced to a certain extent in the application field of medium and small capacitance values and the miniaturization performance is improved, the calculation formula of the flat capacitor
The size of the parallel metal plate/layer is limited, which causes the inevitable contradiction between capacity value expansion and miniaturization. While the metal-insulator-metal (MIM) capacitor of the 4 th) solves the contradiction between capacitance value expansion and miniaturization, the fabrication of the insulator (I) layer in the MIM structure introduces additional processes and risks for the integrated three-dimensional integration technology based on semiconductors. Therefore, on the premise of ensuring that no additional material, preparation process and risk are introduced, the XY plane layout size of the capacitor is effectively reduced, and the requirements of circuit miniaturization and integrated high-performance integrated design are metThe key technology to be broken through is urgent at present.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a vertical layout metal-semiconductor-metal MSM capacitor structure with a simple structure, the capacitor structure can effectively reduce the XY plane size layout, and an intermediate semiconductor medium can keep the high-precision design requirement of the capacitor on the basis of being compatible with the existing integrated three-dimensional integration process. Therefore, the invention also relates to a preparation method of the metal-semiconductor-metal MSM capacitor structure.
The above object of the present invention can be achieved by a vertical layout MSM capacitor structure, comprising: the multilayer semiconductor dielectric substrate stacking structure is tightly attached to the surface of the semiconductor dielectric substrate, and the metal layers G1, G2, G1 and G2 which are not communicated with the capacitor plates can be metal surfaces with any shapes and can be communicated or not communicated with each other. The method is characterized in that: two flat metallized through grooves, blind grooves or buried grooves which are vertical to the surface of the semiconductor dielectric substrate and are separated by a dielectric partition wall S1 are formed at specific positions of the semiconductor dielectric substrate, and the dielectric partition wall S1 forms a dielectric layer of the capacitor; two rectangular through grooves, blind grooves or buried grooves which are parallel to each other are embedded with metal electrode plates P1 and P2 which form homoepitaxy of a capacitor body, the two metal electrode plates P1 and P2 extend towards two ends of a dielectric partition wall S1 through metal layer microstrip connecting lines etched on the surface of a semiconductor dielectric substrate to form an electrode structure led out from MSM capacitor leading-out ends L1 and L2, wherein L1 and L2 can be located on the same surface or different surfaces of the semiconductor dielectric layer, and therefore an MSM capacitor equivalent circuit structure in vertical layout is formed.
A preparation method for manufacturing the MSM capacitor structure with the vertical layout is characterized by comprising the following steps: two flat metallized through grooves, blind grooves or buried grooves which are mutually parallel and are vertically distributed are manufactured on the semiconductor medium substrate, and a medium partition wall S1 of an MSM capacitor insulating layer is formed; according to the interconnection relationship of the MSM capacitor structures which are vertically arranged, leading-out microstrip transmission lines of capacitor leading-out ends are etched on upper/lower metal layers of a dielectric partition wall S1 to form MSM capacitor leading-out ends L1 and L2, adhesion layers are deposited on the side walls and the bottoms of the flat metallized through grooves, the blind grooves or the buried grooves, and diffusion barrier layers are deposited on the side walls and the bottoms of the flat metallized through grooves, the blind grooves or the buried grooves; depositing a seed layer on the diffusion barrier layers on the side walls and the bottoms of the flat metallized through grooves, the blind grooves or the buried grooves; and electroplating filling metal in the groove after the seed layer deposition is finished, and if the groove is a side wall metalized hollow groove, not performing the electroplating filling operation.
Compared with the prior art, the invention has the following beneficial effects:
aiming at the inherent shape and characteristics of an actual circuit/packaging substrate, two flat metallized through grooves, blind grooves or buried grooves which are vertical to the surface of a semiconductor dielectric substrate and are separated by a dielectric partition wall S1 are manufactured at specific positions of the semiconductor dielectric substrate, and a dielectric layer of a capacitor is formed by the dielectric partition wall S1; two rectangular through grooves, blind grooves or buried grooves which are parallel to each other are embedded with metal electrode plates P1 and P2 which form homoepitaxy of a capacitor body, and the two metal electrode plates P1 and P2 extend and are led out to two ends of a dielectric partition wall S1 through metal layer microstrip connecting lines etched on the surface of a semiconductor dielectric substrate to form an MSM capacitor structure in vertical layout. The integrated integration of the embedded capacitor can be really realized in the field of medium and small capacitance value requirements. In particular, besides the interconnection metal and the semiconductor medium substrate material, other materials and processes do not need to be introduced, and the beneficial purposes of reducing the cost and controlling the risk are achieved. Meanwhile, the problems that the capacitor cannot be integrated in a three-dimensional mode and the layout size in the XY direction is effectively reduced in the conventional semiconductor integrated/packaging structure are solved.
Drawings
FIG. 1 is a front view of a vertical layout MSM capacitor structure of the present invention;
FIG. 2 is a top view of FIG. 1;
FIG. 3 is a schematic diagram of the structure of the vertical layout capacitor for the blind slot plate according to the present invention;
FIG. 4 is a schematic diagram of a single capacitor series interconnect structure;
FIG. 5 is a schematic diagram of a single capacitor parallel interconnect structure;
FIG. 6 is a schematic diagram of a dual capacitor series interconnection structure;
FIG. 7 is a schematic diagram of a dual capacitor parallel interconnect structure;
fig. 8 is a schematic diagram of a multi-layer stack structure of the MSM capacitor structure according to embodiment 5 of the present invention.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings in conjunction with specific embodiments.
Detailed Description
Refer to fig. 1 and 2. In an exemplary preferred embodiment described below, a vertical layout MSM capacitor structure includes: the multilayer semiconductor dielectric substrate stacking structure is tightly attached to the surface of the semiconductor dielectric substrate, and the metal layers G1, G2, G1 and G2 which are not communicated with the capacitor plates can be metal surfaces with any shapes and can be communicated or not communicated with each other. Two flat metallized through grooves, blind grooves or buried grooves which are vertical to the surface of the semiconductor dielectric substrate and are separated by a dielectric partition wall S1 are formed at specific positions of the semiconductor dielectric substrate, and the dielectric partition wall S1 forms a dielectric layer of the capacitor; two rectangular through grooves, blind grooves or buried grooves which are parallel to each other are embedded with metal electrode plates P1 and P2 which form homoepitaxy of a capacitor body, the two metal electrode plates P1 and P2 extend towards two ends of a dielectric partition wall S1 through metal layer microstrip connecting lines etched on the surface of a semiconductor dielectric substrate to form an electrode structure led out from MSM capacitor leading-out ends L1 and L2, wherein L1 and L2 can be located on the same surface or different surfaces of the semiconductor dielectric layer, and therefore an MSM capacitor equivalent circuit structure in vertical layout is formed.
In alternative embodiments, embodiment 1:
the two flat metallized through grooves, blind grooves or buried grooves of the vertical MSM capacitor body structure are in a mutually parallel relationship, and the side walls of the flat metallized through grooves, blind grooves or buried grooves can be in a metallized hollow structure or a metal fully-filled solid structure. The dielectric partition wall S1 may be a semiconductor dielectric layer sandwiched between two flat metallized through grooves, blind grooves or buried grooves and immediately adjacent to the sidewalls, the semiconductor dielectric layer and the semiconductor dielectric substrate are of the same material and integrally connected to the capacitor terminals. L1 and L2 may be in the form of microstrip lines, striplines, coplanar waveguides, or other transmission lines. The metal layers G1 and G2 that are not in communication with the capacitor plates may be used as ground or otherwise.
Example 2:
see fig. 3. The difference between this embodiment and embodiment 1 is that two parallel grooves are buried grooves, i.e. one end of each groove does not extend to communicate with the metal layer. This embodiment differs from embodiment 1 in that the trench-to-trench conversion process step using a backside chemical mechanical polishing CMP process can be eliminated.
Example 3:
fig. 4 and 5 are schematic front views of the vertical metal-semiconductor-metal MSM capacitor structure connected in series and in parallel in an actual circuit, that is, as an illustration of the actual layout usage of the capacitor structure. The series connection mode is characterized in that as shown in embodiment 1, the two capacitor leading-out ends are respectively connected with the two parallel metal electrode plate grooves, the two leading-out ends can be positioned on the same metal layer or different metal layers, and the ground end is not communicated with the two parallel metal electrode plate grooves. The parallel connection mode is characterized in that two capacitor leading-out ends are connected with one of the parallel metal pole plate grooves, the two leading-out ends can be positioned on the same metal layer or different metal layers, and the other parallel metal pole plate groove is connected with the ground end. This embodiment is an example of the layout of a single vertical metal-semiconductor-metal MSM capacitor that functions as a dc blocking, filtering, resonance, etc. in an actual circuit.
Example 4:
fig. 6 and 7 are schematic diagrams of a front view and a top view of a series interconnection and a parallel interconnection of two vertical metal-semiconductor-metal MSM capacitor structures in an actual circuit, namely, an illustration of an actual layout usage of the capacitor structures. The series interconnection mode is characterized in that the two capacitors are respectively provided with a parallel metal polar plate groove and are mutually communicated through a transmission structure, and the transmission structure which plays a mutual communication role can be positioned on a metal layer at the top of the polar plate of the groove and also can be positioned on a metal layer at the bottom of the polar plate of the groove; the two leading-out ends are connected with the grooves of the respective residual parallel metal pole plates, and can be positioned on the same metal layer or different metal layers. The parallel interconnection mode is characterized in that the two capacitors are respectively provided with a parallel metal polar plate groove and are mutually communicated through a transmission structure, and the transmission structure which plays a role in mutual communication can be positioned on a metal layer at the top of the polar plate of the groove and also can be positioned on a metal layer at the bottom of the polar plate of the groove; the two leading-out ends are respectively connected with the grooves of the parallel metal pole plates which are communicated with each other, and the two leading-out ends can be positioned on the same metal layer or different metal layers. This embodiment exemplifies the layout of two or more vertical metal-semiconductor-metal MSM capacitors functioning as multi-stage filtering, parallel resonance, etc. in an actual circuit.
Example 5:
fig. 8 is a schematic diagram of a layout front view of the vertical metal-semiconductor-metal MSM capacitor structure in an actual multi-layer semiconductor dielectric stack structure, which is an illustration of the actual layout usage of the capacitor structure. The capacitor structure in this embodiment may be any of the structure layouts and lead-out forms in embodiments 1 to 4, or may be a combination form of any of the capacitor structures in embodiments 1 to 4. The single-layer structures can be stacked in a direct bonding or indirect bonding mode, the number of layers (N1 is more than or equal to 0 or N2 is more than or equal to 0, and integers are taken) stacked up and down, and the stacking method comprises but is not limited to bonding processes such as hot-press bonding, eutectic bonding, solid-liquid diffusion bonding and the like. This embodiment exemplifies the morphological layout of the vertical metal-semiconductor-metal MSM capacitor structure in a practical integrated package design structure.
The present invention has been described in detail with reference to the specific embodiments, but the present invention is not limited thereto. Any modification, equivalent replacement, change and improvement made by persons skilled in the art without departing from the principle, spirit and principle of the invention shall fall within the protection scope of the invention.
Claims (10)
1. A vertical layout MSM capacitive structure comprising: the multilayer semiconductor dielectric substrate stacking structure is tightly attached to the surface of a semiconductor dielectric substrate, metal layers G1, G2, G1 and G2 which are not communicated with a capacitor plate are metal surfaces in any shapes which are communicated or not communicated with each other, and the multilayer semiconductor dielectric substrate stacking structure is characterized in that: two flat metallized through grooves, blind grooves or buried grooves which are vertical to the surface of the semiconductor dielectric substrate and are separated by a dielectric partition wall S1 are formed at specific positions of the semiconductor dielectric substrate, and the dielectric partition wall S1 forms a dielectric layer of the capacitor; two rectangular through grooves, blind grooves or buried grooves which are parallel to each other are embedded with metal electrode plates P1 and P2 which form homoepitaxy of a capacitor body, the two metal electrode plates P1 and P2 extend towards two ends of a dielectric partition wall S1 through metal layer microstrip connecting lines etched on the surface of a semiconductor dielectric substrate to form an electrode structure led out from MSM capacitor leading-out ends L1 and L2, wherein L1 and L2 are located on the same surface or different surfaces of the semiconductor dielectric layer, and therefore an MSM capacitor equivalent circuit structure in vertical layout is formed.
2. The vertically arranged MSM capacitor structure of claim 1, wherein: the two flat metallized through grooves, blind grooves or buried grooves of the vertical MSM capacitor body structure are in a mutually parallel relationship, and the side walls of the flat metallized through grooves, blind grooves or buried grooves are in a metallized hollow structure or a metal fully-filled solid structure.
3. The vertical layout MSM capacitor structure of claim 1 wherein: the dielectric partition wall S1 is a semiconductor dielectric layer sandwiched between two flat metallized through grooves, blind grooves or buried grooves and closely adjacent to the side walls, and the semiconductor dielectric layer and the semiconductor dielectric substrate are made of the same material and are integrally communicated with a capacitor leading-out end.
4. The vertically arranged MSM capacitor structure of claim 1, wherein: l1 and L2 are in the form of microstrip lines, striplines, coplanar waveguide transmission lines, and metal layers G1 and G2 that are not in communication with the capacitor plates are used as ground or for it.
5. The vertically arranged MSM capacitor structure of claim 1, wherein: the two parallel grooves are embedded grooves, and one end of each groove is not extended and is communicated with the metal layer.
6. The vertically arranged MSM capacitor structure of claim 1, wherein: the two capacitor leading-out ends are respectively connected with the two parallel metal pole plate grooves, the two leading-out ends are positioned on the same metal layer or different metal layers from top to bottom, and the ground end is not communicated with the two parallel metal pole plate grooves: the two capacitor leading-out ends are connected with one of the parallel metal pole plate grooves, and the other parallel metal pole plate groove is connected with the ground end.
7. The vertically arranged MSM capacitor structure of claim 1, wherein: the two capacitors are respectively provided with a parallel metal polar plate groove and are mutually communicated through a transmission structure, and the transmission structure which plays a mutual communication role is positioned on a metal layer at the top of the groove polar plate or a metal layer at the bottom of the groove polar plate; the two leading-out ends are connected with the grooves of the respective residual parallel metal pole plates and are positioned on the same metal layer or different metal layers.
8. The vertically arranged MSM capacitor structure of claim 1, wherein: the two capacitors are respectively provided with a parallel metal polar plate groove and are mutually communicated through a transmission structure, and the transmission structure which plays a mutual communication role is positioned on a metal layer at the top of the groove polar plate or a metal layer at the bottom of the groove polar plate; the two leading-out ends are respectively connected with the parallel metal pole plate grooves which are communicated with each other, and the two leading-out ends can be positioned on the same metal layer or different metal layers.
9. The vertically arranged MSM capacitor structure of claim 1, wherein: the capacitor structure is in any structural layout and lead-out form or any mutual combination form of the capacitor structures, the single-layer structures are stacked in a direct bonding or indirect bonding form, the number of the upper and lower stacked layers N1 is more than or equal to 0 or N2 is more than or equal to 0, integers are taken, and the stacking method comprises the processes of hot-press bonding, eutectic bonding and solid-liquid diffusion bonding.
10. A method for making the vertical layout MSM capacitor structure of claim 1 comprising the steps of: (ii) a Two flat metallized through grooves, blind grooves or buried grooves which are mutually parallel and are vertically distributed are manufactured on the semiconductor medium substrate, and a medium partition wall S1 of an MSM capacitor insulating layer is formed; according to the interconnection relationship of the MSM capacitor structures which are vertically arranged, leading-out microstrip transmission lines of capacitor leading-out ends are etched on upper/lower metal layers of a dielectric partition wall S1 to form MSM capacitor leading-out ends L1 and L2, adhesion layers are deposited on the side walls and the bottoms of the flat metallized through grooves, the blind grooves or the buried grooves, and diffusion barrier layers are deposited on the side walls and the bottoms of the flat metallized through grooves, the blind grooves or the buried grooves; depositing a seed layer on the diffusion barrier layers on the side walls and the bottoms of the flat metallized through grooves, the blind grooves or the buried grooves; and electroplating filling metal in the groove after the seed layer deposition is finished, and if the groove is a side wall metalized hollow groove, not performing the electroplating filling operation.
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