CN114512783A - Three-dimensional on-chip annular directional coupler based on coaxial through-silicon-via process - Google Patents
Three-dimensional on-chip annular directional coupler based on coaxial through-silicon-via process Download PDFInfo
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- CN114512783A CN114512783A CN202210033820.5A CN202210033820A CN114512783A CN 114512783 A CN114512783 A CN 114512783A CN 202210033820 A CN202210033820 A CN 202210033820A CN 114512783 A CN114512783 A CN 114512783A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P5/00—Coupling devices of the waveguide type
- H01P5/12—Coupling devices having more than two ports
- H01P5/16—Conjugate devices, i.e. devices having at least one port decoupled from one other port
- H01P5/18—Conjugate devices, i.e. devices having at least one port decoupled from one other port consisting of two coupled guides, e.g. directional couplers
Abstract
The invention relates to a three-dimensional on-chip annular directional coupler based on a coaxial through silicon via process, which comprises the following steps: the top wiring layer, the substrate layer and the bottom wiring layer are sequentially stacked from top to bottom, the top wiring layer is arranged on the upper surface of the substrate layer, the bottom wiring layer is arranged on the lower surface of the substrate layer, a top interconnection line is arranged in the top wiring layer, a plurality of TSV through holes and a plurality of coaxial TSV through holes vertically penetrate through the substrate layer, and a bottom interconnection line is arranged in the bottom wiring layer. The three-dimensional on-chip annular directional coupler based on the coaxial through-silicon-via process utilizes the coupling characteristic between the inner layer and the outer layer of the coaxial TSV and is alternately connected with the multilayer wiring of the upper part and the lower part of the substrate, the coupling part in the circuit topology is equivalent, the three-dimensionality of the structure between the 1 port and the 4 port is realized, the characteristic adjustment flexibility of the structure is higher compared with that of a traditional coupling microstrip line structure, and the influence of process limitations such as minimum line spacing is reduced.
Description
Technical Field
The invention belongs to the technical field of electronics, and particularly relates to a three-dimensional on-chip annular directional coupler based on a coaxial through-silicon-via process.
Background
The on-chip passive device technology can greatly improve the integral density of the system and shorten the signal path length between the chip and the passive device. However, with the reduction of the characteristic size of the microwave integrated circuit, the proportion of the wiring area occupied by the on-chip passive device is gradually increased, and the design flexibility and the application scene of the microwave integrated circuit are greatly influenced. In order to solve this problem, on-chip passive devices based on advanced three-dimensional packaging processes such as through-silicon via (TSV) technology and redistribution layer (rdl) technology have become a research focus, wherein the most widely applied is TSV-based three-dimensional spiral inductors, and besides, other passive device designs based on three-dimensional packaging processes are gradually receiving attention.
The directional coupler is used as an important component in a microwave communication system, and various parameters of the directional coupler are a key ring for restricting the characteristics of the whole system. The on-chip integrated directional coupler mainly adopts a microstrip line form in consideration of compatibility with a planar process, and mainly comprises two types according to different topological structures: the branch line and the annular directional coupler. The annular directional coupler has the advantages of simple manufacturing process, switchable common mode and differential mode output and the like, and is widely applied to application scenes of microwave electronic equipment, antenna feed and the like.
A number of compact annular directional coupler structures and layouts are disclosed in d.a. letavin in its published work. The design is adjusted on the basis of a classical structure, and the wiring space occupied by the original circular ring conductor loop is compressed by introducing a zigzag line structure, so that compact area layout is realized. This structure has disadvantages in that: the area of a blank position between the wirings can be only reduced by adopting a zigzag line scheme, the planar space occupied by the wirings is not reduced, and the minimum distance of the zigzag lines is limited by factors such as process capability, parasitic coupling capacitance between the wirings and the like; meanwhile, along with the rise of the working frequency band, the proportion of the minimum line spacing to the whole size is increased, and the compression effect of the zigzag line scheme on the area is gradually weakened; there is a limit to reducing the area of the ring coupler using this scheme.
Y.cao et al in the published papers disclose a planar microstrip ring coupler constructed using a short-circuited, cross-directional coupled line, in which a quarter-wavelength short-circuited, cross-directional coupled line is used to equivalently replace a three-quarter-wavelength transmission line in the conventional structure, so that the designed ring coupler has more compact wiring and larger bandwidth. This structure has disadvantages in that: the planar coupling line still needs an electrical size of a quarter wavelength, so that the coupling part of the planar coupling line needs to occupy more planar space in a conventional frequency band range; meanwhile, when the scheme is applied to the design of the on-chip annular coupler, the coupling characteristic of the on-chip annular coupler is limited by process factors such as minimum line spacing and the like.
Lu et al in their published papers disclose a three-dimensional branched line-type directional coupler structure based on through-silicon via process. The structure realizes the topological structure of the branch line type coupler through the combination of the conventional and coaxial TSV, and improves the integration density of the branch line type coupler on the basis of keeping larger working bandwidth. This structure has disadvantages in that: in the structure, the coaxial TSV only uses the inner conductor and the outer conductor as common interconnection, and the coupling characteristics between the inner layer and the outer layer of the coaxial TSV are not utilized to further optimize the topology and compress the electrical size of the structure; meanwhile, the scheme based on the double-layer stacked chip process and the TSV as the branch line is specially designed mainly for the branch line type coupler structure in the three-dimensional circuit scene, the design method and the structure are not suitable for constructing an on-chip integrated annular directional coupler, the branch line type coupler and the annular coupler have large difference in the aspects of phase difference, isolation and the like of output signals, and the application scenes cannot be replaced with each other.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a three-dimensional on-chip annular directional coupler based on a coaxial through silicon via process. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a three-dimensional on-chip annular directional coupler based on a coaxial through silicon via process, which comprises the following steps: the wiring structure comprises a top wiring layer, a substrate layer and a bottom wiring layer which are sequentially stacked from top to bottom, wherein the top wiring layer is arranged on the upper surface of the substrate layer, and the bottom wiring layer is arranged on the lower surface of the substrate layer;
the top wiring layer comprises a first top interconnection layer, a second top interconnection layer and a third top interconnection layer which are sequentially arranged from bottom to top, interlayer through holes are formed among the interconnection layers, a first top conductor, a second top conductor, a third top conductor and a fourth top conductor are arranged in the first top interconnection layer, a fifth top conductor and a sixth top conductor are arranged in the second top interconnection layer, and a first port, a second port, a third port and a fourth port are arranged in the third top interconnection layer;
the first port, the second port, the third port and the fourth port are correspondingly connected with the top first conductor, the top fifth conductor, the top third conductor and the top fourth conductor through the interlayer through holes respectively;
the top second conductor and the top sixth conductor are connected with a ground layer through the interlayer through hole, and the ground layer is located on the upper surface of the top wiring layer;
a plurality of TSV through holes and a plurality of coaxial TSV through holes vertically penetrate through the substrate layer;
the bottom wiring layer comprises a first bottom interconnection layer and a second bottom interconnection layer which are sequentially arranged from top to bottom, a first bottom conductor, a second bottom conductor, a third bottom conductor and a fourth bottom conductor are arranged in the first bottom interconnection layer, and a fifth bottom conductor is arranged in the second bottom interconnection layer; the bottom fifth conductor is located below the bottom fourth conductor;
the conductor in the top wiring layer is connected with the conductor in the bottom wiring layer through the TSV through holes and the coaxial TSV through holes to form a loop;
the bottom first conductor is respectively connected with the top first conductor and the top fifth conductor through two TSV through holes, the bottom second conductor is respectively connected with the top first conductor and the top fourth conductor through two TSV through holes, and the bottom third conductor is respectively connected with the top third conductor and the top fourth conductor through two TSV through holes;
the first end of the bottom fifth conductor and the first end of the bottom fourth conductor are correspondingly connected with the top fifth conductor and the top second conductor through one coaxial TSV through hole;
the second end of the bottom fifth conductor and the second end of the bottom fourth conductor are correspondingly connected with the top sixth conductor and the top third conductor through one coaxial TSV through hole.
In one embodiment of the present invention, the top first conductor, the top third conductor and the top fourth conductor are all L-shaped conductors, and the top second conductor is a rectangular conductor;
the top first conductor, the top second conductor, the top third conductor and the top fourth conductor are sequentially arranged at 4 vertex angles of a space rectangle in a clockwise direction, and the space rectangle is formed by the straight lines corresponding to the outermost edges of the top first conductor, the top second conductor, the top third conductor and the top fourth conductor.
In one embodiment of the present invention, the top fifth conductor is an L-shaped conductor, and the top sixth conductor is a rectangular conductor;
the top fifth conductor is located above the top second conductor and the top sixth conductor is located above the top third conductor.
In an embodiment of the present invention, the first port, the second port, the third port and the fourth port are respectively and correspondingly connected with corners of the top first conductor, the top fifth conductor, the top third conductor and the top fourth conductor through the interlayer via holes.
In one embodiment of the present invention, the bottom first conductor, the bottom second conductor, the bottom third conductor, the bottom fourth conductor, and the bottom fifth conductor are all rectangular conductors.
In one embodiment of the invention, the TSV through hole comprises a cylindrical conductor located in the center and a first liner layer surrounding the cylindrical conductor;
the coaxial TSV through hole comprises an inner conductor column, an intermediate medium layer, an outer conductor layer and a second liner layer which are sequentially arranged from inside to outside.
In an embodiment of the invention, the intermediate dielectric layer includes a third pad layer, an inter-conductor dielectric layer, and a fourth pad layer, which are sequentially disposed from inside to outside.
In one embodiment of the present invention, the first end of the bottom first conductor is connected to the first end of the top first conductor through the cylindrical conductor, and the second end is connected to the first end of the top fifth conductor through the cylindrical conductor;
the first end of the second conductor is connected with the second end of the top first conductor through the cylindrical conductor, and the second end of the second conductor is connected with the first end of the top fourth conductor through the cylindrical conductor;
the first end of the bottom third conductor is connected with the second end of the top fourth conductor through the cylindrical conductor, and the second end of the bottom third conductor is connected with the first end of the top third conductor through the cylindrical conductor;
the first end of the bottom fourth conductor is connected with the first end of the top second conductor through the outer conductor layer, and the first end of the bottom fifth conductor is connected with the second end of the top fifth conductor through the inner conductor pillar;
a second end of the bottom fourth conductor is connected to a second end of the top third conductor through the outer conductor layer, and a second end of the bottom fifth conductor is connected to a first end of the top sixth conductor through the inner conductor pillar;
and the second end of the top second conductor is connected with the ground layer through the interlayer through hole, and the second end of the top sixth conductor is connected with the ground layer through the interlayer through hole.
In one embodiment of the present invention, circular holes are provided at the first ends of the bottom fourth conductor and the top second conductor so that the inner conductor pillar penetrates through the bottom fourth conductor and the top second conductor;
round holes are formed in the second ends of the bottom fourth conductor and the top third conductor, so that the inner conductor columns penetrate through the bottom fourth conductor and the top third conductor.
In one embodiment of the present invention, the end of the conductor connected to the cylindrical conductor or the inner conductor pillar is provided in a circular shape or a rectangular shape.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention relates to a three-dimensional on-chip annular directional coupler based on a coaxial Through Silicon Via (TSV) process and a multilayer wiring process, which is a three-dimensional structure constructed on the basis of the TSV and the multilayer wiring process, wherein a three-dimensional conductor path which is embedded into a substrate and is arranged on the front side and the back side of the substrate in a zigzag manner greatly compresses a horizontal projection area occupied by the on-chip annular coupler, and the whole integration density of the three-dimensional on-chip annular directional coupler is far beyond a super-planar structure;
2. the three-dimensional on-chip annular directional coupler based on the coaxial through-silicon-via process utilizes the coupling characteristics between the inner layer and the outer layer of the coaxial TSV and is alternately connected with the multilayer wiring of the upper part and the lower part of the substrate, the coupling part in the circuit topology is equivalent, the three-dimensionality of the structure between 1 and 4 ports is realized, the characteristic adjustment flexibility of the structure is higher compared with that of the traditional coupling microstrip line structure, and the influence of process limitations such as minimum line spacing is reduced;
3. according to the three-dimensional on-chip annular directional coupler based on the coaxial through silicon via process, the multilayer wiring and TSV vertical interconnection structure is adopted, the four ports can be flexibly changed in port spacing or configured in different wiring layers according to specific application requirements, and the problem that the ports of a planar annular structure are fixed in position and far away from each other is solved.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a three-dimensional view of a three-dimensional on-chip annular directional coupler based on a coaxial through-silicon-via process according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view of a three-dimensional on-chip ring-shaped directional coupler based on a through-silicon-via-coaxial process according to an embodiment of the present invention;
FIG. 3 is a simplified equivalent circuit diagram of the topology employed by the present invention;
fig. 4 is an equivalent circuit diagram of a coaxial TSV via provided by an embodiment of the invention;
FIG. 5 is a cross-sectional view of a TSV array distribution provided by an embodiment of the present invention;
figure 6 is a schematic diagram of a top interconnect line provided by an embodiment of the present invention;
figure 7 is a schematic diagram of a bottom interconnect line provided by an embodiment of the invention.
Icon: 1-a top wiring layer; 11-a first top interconnect layer; 111-a top first conductor; 112 a top second conductor; 113-a top third conductor; 114-top fourth conductor; 12-a second top interconnect layer; 121-top fifth conductor; 122 a top sixth conductor; 13-a third top interconnect layer; 131-a first port; 132-a second port; 133-a third port; 134-fourth port; 14-interlayer via holes; 2 a substrate layer; 3-a bottom wiring layer; 31-a first bottom interconnect layer; 311-bottom first conductor; 312-a bottom second conductor; 313-a bottom third conductor; 314-bottom fourth conductor; 32-a second bottom interconnect layer; 321-bottom fifth conductor; 4-a ground plane; 5-TSV through holes; 51-cylindrical conductor; 52-first liner layer; 6-coaxial TSV through holes; 61-inner conductor columns; 62-an intermediate dielectric layer; 621-a third cushion layer; 622-inter-conductor dielectric layer; 623-a fourth cushion layer; 63-an outer conductor layer; 64-second liner layer.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the predetermined objects, a three-dimensional on-chip annular directional coupler based on a coaxial tsv process according to the present invention is described in detail below with reference to the accompanying drawings and the detailed description.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. While the present invention has been described in connection with the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Example one
Referring to fig. 1 and fig. 2 in combination, fig. 1 is a three-dimensional view of a three-dimensional on-chip annular directional coupler based on a coaxial through-silicon-via process according to an embodiment of the present invention; fig. 2 is a cross-sectional view of a three-dimensional on-chip ring-shaped directional coupler based on a coaxial through-silicon-via process according to an embodiment of the present invention. As shown in the figure, the three-dimensional on-chip annular directional coupler based on the coaxial tsv process of the embodiment is characterized by comprising: the wiring structure comprises a top wiring layer 1, a substrate layer 2 and a bottom wiring layer 3 which are sequentially stacked from top to bottom, wherein the top wiring layer 2 is arranged on the upper surface of the substrate layer 2, and the bottom wiring layer 3 is arranged on the lower surface of the substrate layer 2.
The top wiring layer 1 includes a first top interconnection layer 11, a second top interconnection layer 12 and a third top interconnection layer 13, which are sequentially arranged from bottom to top, an interlayer through hole 14 is arranged between the interconnection layers, a first top conductor 111, a second top conductor 112, a third top conductor 113 and a fourth top conductor 114 are arranged in the first top interconnection layer 11, a fifth top conductor 121 and a sixth top conductor 122 are arranged in the second top interconnection layer 12, and a first port 131, a second port 132, a third port 133 and a fourth port 134 are arranged in the third top interconnection layer 13.
Further, the first port 131, the second port 132, the third port 133 and the fourth port 134 are respectively connected to the top first conductor 111, the top fifth conductor 121, the top third conductor 113 and the top fourth conductor 114 through the interlayer via 14; the top second conductor 112 and the top sixth conductor 122 are connected to the ground layer 4 through the interlayer via 14, and the ground layer 4 is located on the upper surface of the top wiring layer 1.
In the present embodiment, the top first conductor 111, the top second conductor 112, the top third conductor 113, the top fourth conductor 114, the top fifth conductor 121, and the top sixth conductor 122 form a top interconnection line, as shown in fig. 6, and fig. 6 is a schematic top interconnection line provided by an embodiment of the present invention. Specifically, the top first conductor 111, the top third conductor 113, and the top fourth conductor 114 are all L-shaped conductors, and the top second conductor 112 is a rectangular conductor. The top first conductor 111, the top second conductor 112, the top third conductor 113 and the top fourth conductor 114 are sequentially arranged at 4 vertex angles of a space rectangle in the clockwise direction, and the space rectangle is formed by the straight lines corresponding to the outermost edges of the top first conductor 111, the top second conductor 112, the top third conductor 113 and the top fourth conductor 114 in a surrounding mode. The top fifth conductor 121 is an L-shaped conductor, and the top sixth conductor 122 is a rectangular conductor; the top fifth conductor 121 is located above the top second conductor 112 and the top sixth conductor 122 is located above the top third conductor 113.
In the present embodiment, the first port 131, the second port 132, the third port 133 and the fourth port 134 are respectively connected to the corners of the top first conductor 111, the top fifth conductor 121, the top third conductor 113 and the top fourth conductor 114 through the interlayer via 14.
Note that the first port 131, the second port 132, the third port 133, and the fourth port 134 serve as input ports or output ports of the ring-shaped directional coupler of the present embodiment. Alternatively, four ports may be provided in the first layer or the second layer of the top wiring layer 1.
Further, a plurality of TSV through holes 5 and a plurality of coaxial TSV through holes 6 are vertically arranged in the substrate layer 2 in a penetrating mode. As shown in fig. 5, fig. 5 is a cross-sectional view of a TSV array distribution provided by an embodiment of the invention. In the present embodiment, the TSV via 5 includes a cylindrical conductor 51 at the center and a first liner layer 52 surrounding the cylindrical conductor 51; the coaxial TSV via 6 includes an inner conductor pillar 61, an intermediate dielectric layer 62, an outer conductor layer 63, and a second liner layer 64, which are sequentially arranged from inside to outside. In this embodiment, the intermediate dielectric layer 62 includes a third pad layer 621, an inter-conductor dielectric layer 622, and a fourth pad layer 623 that are sequentially disposed from inside to outside.
Optionally, the first liner layer 52, the second liner layer 64, the third liner layer 621, and the fourth liner layer 623 are made of silicon dioxide, and the inter-conductor dielectric layer 622 is made of benzocyclobutene.
Further, the bottom wiring layer 3 includes a first bottom interconnection layer 31 and a second bottom interconnection layer 32 sequentially arranged from top to bottom, a bottom first conductor 311, a bottom second conductor 312, a bottom third conductor 313 and a bottom fourth conductor 314 are arranged in the first bottom interconnection layer 31, and a bottom fifth conductor 321 is arranged in the second bottom interconnection layer 32; the bottom fifth conductor 321 is located below the bottom fourth conductor 314.
In this embodiment, the bottom first conductor 311, the bottom second conductor 312, the bottom third conductor 313, the bottom fourth conductor 314, and the bottom fifth conductor 321 form a bottom interconnection line, as shown in fig. 7, and fig. 7 is a schematic diagram of the bottom interconnection line provided by the embodiment of the present invention. Specifically, the bottom first conductor 311, the bottom second conductor 312, the bottom third conductor 313, the bottom fourth conductor 314, and the bottom fifth conductor 321 are all rectangular conductors.
Further, the conductor in the top wiring layer 1 is connected with the conductor in the bottom wiring layer 3 through the plurality of TSV vias 5 and the plurality of coaxial TSV vias 6 to form a loop. The bottom first conductor 311 is connected to the top first conductor 111 and the top fifth conductor 121 through two TSV vias 5, the bottom second conductor 312 is connected to the top first conductor 111 and the top fourth conductor 114 through two TSV vias 5, and the bottom third conductor 313 is connected to the top third conductor 113 and the top fourth conductor 114 through two TSV vias 5. A first end of the bottom fifth conductor 321 and a first end of the bottom fourth conductor 314 are correspondingly connected with the top fifth conductor 121 and the top second conductor 112 through one coaxial TSV via 6; the second end of the bottom fifth conductor 321 and the second end of the bottom fourth conductor 314 are connected to the top sixth conductor 122 and the top third conductor 113, respectively, by one coaxial TSV via 6.
Specifically, the first end of the bottom first conductor 311 is connected to the first end of the top first conductor 111 through the cylindrical conductor 51, and the second end is connected to the first end of the top fifth conductor 121 through the cylindrical conductor 51; the first end of the second conductor 312 is connected to the second end of the top first conductor 111 through the cylindrical conductor 51, and the second end is connected to the first end of the top fourth conductor 114 through the cylindrical conductor 51; the first end of the bottom third conductor 313 is connected to the second end of the top fourth conductor 114 by a cylindrical conductor 51 and the second end is connected to the first end of the top third conductor 113 by a cylindrical conductor 51.
Further, a first end of the bottom fourth conductor 314 is connected to a first end of the top second conductor 112 through the outer conductor layer 63, and a first end of the bottom fifth conductor 321 is connected to a second end of the top fifth conductor 121 through the inner conductor post 61; a second end of the bottom fourth conductor 314 is connected to a second end of the top third conductor 113 through the outer conductor layer 63, and a second end of the bottom fifth conductor 321 is connected to a first end of the top sixth conductor 122 through the inner conductor post 61; the second end of the top second conductor 112 is connected to the ground layer 4 through the interlayer via 14, and the second end of the top sixth conductor 122 is connected to the ground layer 4 through the interlayer via 14.
In the present embodiment, circular holes are provided at the first ends of the bottom fourth conductor 314 and the top second conductor 112, so that the inner conductor pillar 61 penetrates through the bottom fourth conductor 314 and the top second conductor 112; circular holes are provided at the second end of the bottom fourth conductor 314 and the second end of the top third conductor 113 so that the inner conductor post 61 penetrates through the bottom fourth conductor 314 and the top third conductor 113.
Note that the end of the conductor connected to the cylindrical conductor 51 or the inner conductor post 61 is circular or rectangular. In the present embodiment, the top wiring layer 1 and the bottom wiring layer 3 are located in a conventional conductive layer, in other embodiments, the top wiring layer 1 and the bottom wiring layer 3 may also be located in a redistribution layer rdl (redistribution layer), and the connection order of each portion is adjusted accordingly without changing the lengths of conductors and TSVs between ports.
The three-dimensional on-chip annular directional coupler based on the coaxial through silicon via process is a three-dimensional structure constructed based on the TSV and the multilayer wiring process, a three-dimensional conductor path which is embedded into a substrate and is arranged on the front side and the back side of the substrate in a zigzag mode greatly compresses the horizontal projection area occupied by the on-chip annular coupler, and the whole integration density of the three-dimensional on-chip annular directional coupler is far beyond a super-planar structure.
The three-dimensional on-chip annular directional coupler based on the coaxial through-silicon-via process utilizes the coupling characteristic between the inner layer and the outer layer of the coaxial TSV and is alternately connected with the multilayer wiring of the upper part and the lower part of the substrate, the coupling part in the circuit topology is equivalent, the three-dimensionality of the structure between the 1 port and the 4 port is realized, the characteristic adjustment flexibility of the structure is higher compared with that of the traditional coupling microstrip line structure, and the influence of process limitations such as minimum line spacing is reduced.
Further, a simple equivalent circuit diagram of a topology adopted by the three-dimensional on-chip annular directional coupler based on the coaxial through-silicon-via process according to the present embodiment is specifically described, as shown in fig. 3, fig. 3 is the simple equivalent circuit diagram of the topology adopted according to the embodiment of the present invention, and the design idea of the annular directional coupler is that, by constructing a four-port annular loop, when a 2-port (3-port) is used as an input, outputs of a 1-port and a 3-port (2-port and 4-port) are equally divided into power and equal phase, and a 4-port (1-port) is an isolated port; when 1 port (4 ports) is used as input, the outputs of 2 ports and 4 ports (1 port and 3 ports) share power equally and have 180-degree phase difference, and 3 ports (2 ports) are isolated ports. Conversely, the signals can be superposed or subtracted by exchanging the input and output ports.
To achieve the above function, the electrical dimension length between 1 port to 2 ports, 2 port to 3 ports, and 3 port to 4 ports is set to be a quarter wavelength, and the impedance between each segment is set to be about 1.414Z0(Z0Is the port impedance); the electrical dimension length between 1 port and 4 ports in the original traditional topology is three-quarter wavelength, and the electrical dimension length can be reduced to equivalently convert the electrical dimension length into a coupling transmission line with a quarter wavelength and two opposite ends grounded, and the parity impedance of the coupling transmission line is about 0.586Z0And 3.413Z0. The optimized topology has a larger relative bandwidth in addition to a shorter electrical size.
In order to realize the topological structure, in this embodiment, each section of quarter-wave path is constructed by multilayer conductor wiring and TSV process, and a quarter-wave coupling transmission line is equivalent by alternately connecting coaxial TSVs and upper and lower coupling conductors. Fig. 4 shows an equivalent circuit of a coaxial TSV, where fig. 4 is an equivalent circuit diagram of a coaxial TSV via according to an embodiment of the present invention, the inner and outer conductors are coupled to each other through a parasitic capacitance and a mutual inductance, the capacitive coupling is mainly affected by the liner layer, the thickness of the dielectric layer, and the material characteristics of the intermediate layer, and the mutual inductance is mainly determined by the distance and the radius of the inner and outer conductors. The parasitic parameters are more complex than those of the traditional coaxial transmission line, and the design needs to be carried out by combining an equivalent circuit and electromagnetic simulation and combining specific process conditions.
Taking the target frequency of about 30GHz as an example, to explain a specific design scheme, the three-dimensional on-chip annular directional coupler based on the TSV process of this embodiment mainly implements a required annular loop through the top and bottom wiring layers and the TSV via embedded in the substrate, and compresses the electrical dimension length of the conventional structure through the broadside coupling of the multilayer wiring and the alternate connection of the coaxial TSVs.
In order to facilitate application and signal transmission, ports 1 to 4 are all arranged on the same layer and are led out from the top of the whole device; the paths between the port 1 and the port 2, the port 2 and the port 3, and the port 3 and the port 4 are set to be equal in length by constructing and sequentially connecting the top wiring layer, the TSV through holes, the coaxial TSV through holes and the bottom wiring layer, and in the embodiment, the paths are formed by sequentially connecting two sections of conducting wires and two TSV through holes, so that the overall equivalent electrical size length of the connecting structure is about one-quarter wavelength, and the equivalent impedance is about 1.414 times of the impedance of the ports by optimizing the size of the connecting structure; by optimizing the dimensions of the coaxial TSV vias and associated connections such that the overall equivalent electrical dimension length between 1 port to 4 ports is also approximately one quarter wavelength, the overall equivalent coupling characteristics satisfy parity impedances of approximately 0.586 to 3.413 times the port impedance. In addition to meeting performance requirements, the aspect ratio, the thickness of the liner layer and the like of the designed TSV and the coaxial TSV need to meet process capability.
Referring to fig. 6 in combination, in the present embodiment, the top first conductor 111 has an L-shape, the top second conductor 112 has a rectangular shape, the top third conductor 113 has an L-shape rotated by 270 degrees clockwise and has a terminal at its center to be connected to the third port 133, and the top fourth conductor 114 has an L-shape rotated by 90 degrees clockwise and has a terminal at its center, wherein L1＝L2＝L3＝L4The conductor width was set to 42 μm at 145 μm.
Referring to FIG. 7 in combination, in this embodimentIn the example, the bottom wiring layer 3 is wired by turning over the silicon substrate and performing rewiring layer process, and the first bottom interconnection layer 31 includes four conductors respectively located at the upper, lower, right and center of the plane, and the specific positions thereof are determined according to the connection relationship with the top wiring layer 1 and the TSV through hole; the second bottom interconnect layer 32 is provided with conductors on the right side of the plane and positioned directly below the conductors on the right side of the first bottom interconnect layer 31, forming broadside coupling, where L5＝185μm，L6The conductor width was set at 42 μm, 154 μm.
Referring collectively to FIG. 5, in the present embodiment, the radius R of the cylindrical conductor 511Thickness t of the first spacer layer 52 of 20 μm10.5 μm. Radius R of inner conductor post 612Outer diameter R of outer conductor layer 63 of 18 μm3Thickness t of the third liner layer 621 being 25 μm2A thickness t of the fourth liner layer 6233And a thickness t of the second pad layer 644Are all 0.5 μm, and the thickness of the dielectric layer between the conductors is 5 μm. The height of the TSV and the coaxial TSV is approximately equal to that of the substrate layer 2, and the substrate layer 2 is thinned to 300 mu m through a chemical mechanical polishing process.
The three-dimensional on-chip annular directional coupler based on the coaxial through-silicon-via process adopts a multilayer wiring and TSV vertical interconnection structure, and the four ports can be flexibly changed in port spacing or configured in different wiring layers according to specific application requirements, so that the problems that the ports of a planar annular structure are fixed in position and are far away from each other are solved.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or device comprising the element. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The directional or positional relationships indicated by "upper", "lower", "left", "right", etc., are based on the directional or positional relationships shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A three-dimensional on-chip annular directional coupler based on a coaxial through-silicon-via process is characterized by comprising: the wiring structure comprises a top wiring layer (1), a substrate layer (2) and a bottom wiring layer (3), wherein the top wiring layer (2) is arranged on the upper surface of the substrate layer (2), and the bottom wiring layer (3) is arranged on the lower surface of the substrate layer (2);
the top wiring layer (1) comprises a first top interconnection layer (11), a second top interconnection layer (12) and a third top interconnection layer (13) which are sequentially arranged from bottom to top, interlayer through holes (14) are arranged among the interconnection layers, a first top conductor (111), a second top conductor (112), a third top conductor (113) and a fourth top conductor (114) are arranged in the first top interconnection layer (11), a fifth top conductor (121) and a sixth top conductor (122) are arranged in the second top interconnection layer (12), and a first port (131), a second port (132), a third port (133) and a fourth port (134) are arranged in the third top interconnection layer (13);
the first port (131), the second port (132), the third port (133) and the fourth port (134) are respectively and correspondingly connected with the top first conductor (111), the top fifth conductor (121), the top third conductor (113) and the top fourth conductor (114) through the interlayer through hole (14);
the top second conductor (112) and the top sixth conductor (122) are connected with a ground layer (4) through the interlayer through hole (14), and the ground layer (4) is located on the upper surface of the top wiring layer (1);
a plurality of TSV through holes (5) and a plurality of coaxial TSV through holes (6) vertically penetrate through the substrate layer (2);
the bottom wiring layer (3) comprises a first bottom interconnection layer (31) and a second bottom interconnection layer (32) which are sequentially arranged from top to bottom, a first bottom conductor (311), a second bottom conductor (312), a third bottom conductor (313) and a fourth bottom conductor (314) are arranged in the first bottom interconnection layer (31), and a fifth bottom conductor (321) is arranged in the second bottom interconnection layer (32); the bottom fifth conductor (321) is located below the bottom fourth conductor (314);
the conductor in the top wiring layer (1) is connected with the conductor in the bottom wiring layer (3) through the TSV through holes (5) and the coaxial TSV through holes (6) to form a loop;
the bottom first conductor (311) is connected with the top first conductor (111) and the top fifth conductor (121) through two TSV vias (5), the bottom second conductor (312) is connected with the top first conductor (111) and the top fourth conductor (114) through two TSV vias (5), and the bottom third conductor (313) is connected with the top third conductor (113) and the top fourth conductor (114) through two TSV vias (5);
a first end of the bottom fifth conductor (321) and a first end of the bottom fourth conductor (314) are correspondingly connected with the top fifth conductor (121) and the top second conductor (112) through one coaxial TSV via (6);
and the second end of the bottom fifth conductor (321) and the second end of the bottom fourth conductor (314) are correspondingly connected with the top sixth conductor (122) and the top third conductor (113) through one coaxial TSV through hole (6).
2. The three-dimensional on-chip loop directional coupler based on the coaxial through-silicon-via process as claimed in claim 1, wherein the top first conductor (111), the top third conductor (113) and the top fourth conductor (114) are all L-shaped conductors, and the top second conductor (112) is a rectangular conductor;
the top first conductor (111), the top second conductor (112), the top third conductor (113) and the top fourth conductor (114) are sequentially arranged at 4 vertex angles of a spatial rectangle according to a clockwise direction, and the spatial rectangle is formed by the straight lines corresponding to the outermost edges of the top first conductor (111), the top second conductor (112), the top third conductor (113) and the top fourth conductor (114) in an enclosing manner.
3. The three-dimensional on-chip annular directional coupler based on the coaxial through-silicon-via process as claimed in claim 2, wherein the top fifth conductor (121) is an L-shaped conductor and the top sixth conductor (122) is a rectangular conductor;
the top fifth conductor (121) is located above the top second conductor (112), and the top sixth conductor (122) is located above the top third conductor (113).
4. The three-dimensional on-chip ring-shaped directional coupler based on the coaxial through-silicon-via process as claimed in claim 3, wherein the first port (131), the second port (132), the third port (133) and the fourth port (134) are respectively connected with the corners of the top first conductor (111), the top fifth conductor (121), the top third conductor (113) and the top fourth conductor (114) through the interlayer via (14).
5. The three-dimensional on-chip loop directional coupler based on the coaxial through-silicon-via process as claimed in claim 4, wherein the bottom first conductor (311), the bottom second conductor (312), the bottom third conductor (313), the bottom fourth conductor (314) and the bottom fifth conductor (321) are all rectangular conductors.
6. The three-dimensional on-chip annular directional coupler based on the through-silicon-via-coax process of claim 1, wherein the TSV via (5) comprises a centrally located cylindrical conductor (51) and a first liner layer (52) surrounding the cylindrical conductor (51);
the coaxial TSV (through silicon via) through hole (6) comprises an inner conductor column (61), an intermediate medium layer (62), an outer conductor layer (63) and a second liner layer (64) which are sequentially arranged from inside to outside.
7. The three-dimensional on-chip annular directional coupler based on the coaxial through-silicon-via process as claimed in claim 6, wherein the intermediate dielectric layer (62) comprises a third pad layer (621), an inter-conductor dielectric layer (622) and a fourth pad layer (623) which are sequentially arranged from inside to outside.
8. The three-dimensional on-chip loop directional coupler based on the coaxial through-silicon-via process as claimed in claim 6, wherein a first end of the bottom first conductor (311) is connected to a first end of the top first conductor (111) through the cylindrical conductor (51), and a second end is connected to a first end of the top fifth conductor (121) through the cylindrical conductor (51);
the first end of the second conductor (312) is connected with the second end of the top first conductor (111) through the cylindrical conductor (51), and the second end is connected with the first end of the top fourth conductor (114) through the cylindrical conductor (51);
the first end of the bottom third conductor (313) is connected with the second end of the top fourth conductor (114) through the cylindrical conductor (51), and the second end of the bottom third conductor is connected with the first end of the top third conductor (113) through the cylindrical conductor (51);
a first end of the bottom fourth conductor (314) is connected to a first end of the top second conductor (112) through the outer conductor layer (63), and a first end of the bottom fifth conductor (321) is connected to a second end of the top fifth conductor (121) through the inner conductor pillar (61);
a second end of the bottom fourth conductor (314) is connected to a second end of the top third conductor (113) through the outer conductor layer (63), and a second end of the bottom fifth conductor (321) is connected to a first end of the top sixth conductor (122) through the inner conductor pillar (61);
the second end of the top second conductor (112) is connected with the ground layer (4) through the interlayer through hole (14), and the second end of the top sixth conductor (122) is connected with the ground layer (4) through the interlayer through hole (14).
9. The three-dimensional on-chip annular directional coupler based on the coaxial through-silicon-via process as claimed in claim 8, wherein a first end of the bottom fourth conductor (314) and a first end of the top second conductor (112) are provided with circular holes so that the inner conductor pillar (61) penetrates through the bottom fourth conductor (314) and the top second conductor (112);
round holes are arranged at the second end of the bottom fourth conductor (314) and the second end of the top third conductor (113) so that the inner conductor pillar (61) penetrates through the bottom fourth conductor (314) and the top third conductor (113).
10. The three-dimensional on-chip annular directional coupler based on the coaxial through-silicon-via process as claimed in claim 9, wherein the end of the conductor connected with the cylindrical conductor (51) or the inner conductor pillar (61) is provided in a circular or rectangular shape.
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