CN112087214A - TSV coupling and RDL interconnection on-chip passive balun and manufacturing process - Google Patents
TSV coupling and RDL interconnection on-chip passive balun and manufacturing process Download PDFInfo
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- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/42—Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
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- H—ELECTRICITY
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- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
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Abstract
The invention discloses an on-chip passive balun with TSV coupling and RDL interconnection and a manufacturing process. The TSV coupling units are formed by capacitively coupling two TSVs. The top interconnecting wire is arranged at the top of the silicon substrate, the RDL interconnecting wire is arranged at the bottom of the silicon substrate, and each section of the RDL interconnecting wire consists of two parallel rectangular conductors. And the top interconnection lines, the coupling units and the RDL interconnection lines are connected to form a zigzag balun total coupling path. The invention can be used for realizing the function of the balun circuit for converting a single-ended unbalanced signal into a double-ended balanced output signal, and has the advantages of higher integration density, smaller vertical interconnection crosstalk and noise and wide selectable frequency range compared with the prior art.
Description
Technical Field
The invention belongs to the technical field of electronics, and further relates to an on-chip passive balun interconnected with a Through Silicon Via (TSV) (through Silicon Via) coupling and a redistribution layer (RDL) (redistribution layer) in the technical field of electronic devices and a manufacturing process thereof. The invention can be used as an independent device to realize the conversion from an unbalanced input signal to a balanced output signal, and can also be integrated in a radio frequency/microwave integrated circuit to realize the functions of push-pull amplification, double-balanced frequency mixing and balanced amplification.
Background
Balun (Balun) is a generic name of a class of three-port electronic devices, and has a main function of converting an unbalanced input signal into a balanced output signal, and under an ideal condition, two balanced output ends have the same amplitude and 180 ° phase difference, so that Balun (Balun) is often integrated in a circuit structure with a differential input requirement, such as a double balanced mixer, a push-pull amplifier and the like, and is widely applied to the application fields of wireless communication, remote signal transmission and the like. The traditional balun device can be realized by adopting different structures such as a transformer, a transmission line, a power divider and the like according to different frequency band ranges, processes and performance requirements. The Marchand type transmission line balun has the characteristics of large working bandwidth, excellent balance performance and easiness in integration, and is widely applied to microwave frequency bands.
The patent document "LTCC-based combined two-way power divider" (application No. 201910161349.6, application publication No. CN 109786919 a) applied by Nanjing university of technology discloses a Marchand type balun circuit with a planar spiral structure. The on-chip balun with the planar structure realizes the circuit function of the balun through the capacitive coupling characteristic between two adjacent spiral lines. This structure has disadvantages in that: because the balun is of a planar structure, when the balun is integrated in a radio frequency/microwave integrated circuit, a large amount of layout space is occupied, so that the overall assembly area of a system is increased, and the application of the balun device in a high integration density scene is limited. When the structure is integrated in a system through vertical stacked packaging, additional wiring and through holes are needed, and more signal crosstalk and noise are introduced.
A process for manufacturing a Marchand type Balun on chip circuit is disclosed in the paper "D-band Frequency double with Marchand band Structure" (conference name: IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), site: Nanjing, China, time: 12.12.2019), published by Xin Wang, Jincai Wen, Lingling Sun. The balun circuit is manufactured by adopting a standard CMOS process, and has the advantages of strong compatibility of the CMOS process, convenience for integration with other devices, high process maturity and low overall cost. However, the manufacturing process still has the disadvantages that: the balun on the chip manufactured by the CMOS process can realize wiring only by utilizing a metal layer area on the top of the front side of the silicon substrate, so that the space utilization rate is low; and the wiring size such as thickness, line width and line spacing in the region is severely restricted by the process conditions, and the frequency range and performance of the balun circuit are affected.
Disclosure of Invention
The invention aims to provide a TSV (through silicon via) coupled and RDL (remote data link) interconnected on-chip passive balun and a manufacturing process thereof aiming at the defects in the prior art, and aims to solve the problems that the application of the conventional balun structure is limited in a high integration density scene, the vertical interconnection crosstalk and noise are large, and the frequency band and performance selection are limited.
The idea of realizing the purpose of the invention is that a coupling unit structure is formed through the capacitive coupling effect among the TSVs, so as to increase the equivalent coupling path length on the premise of not changing the wiring area and density, and improve the integration level of a circuit and a system; by introducing a bottom RDL interconnection structure, the coupling unit is vertically connected with the top metal layer to form a three-dimensional balun structure, the input and the output of the balun structure can be positioned at the top or the bottom of the silicon substrate, and the balun structure is correspondingly arranged aiming at different application scenes, so that crosstalk and noise introduced by additional vertical interconnection can be reduced.
The invention designs an on-chip passive balun with TSV coupling and RDL interconnection, which comprises a silicon substrate, and a plurality of groups of top interconnection lines, two grounding through holes, a plurality of groups of coupling units formed by two-to-two capacitive coupling of TSV and a plurality of groups of bottom RDL interconnection lines which are sequentially arranged on the silicon substrate; the top of the silicon substrate is provided with a plurality of groups of interconnecting wires, each group consists of three discontinuous top interconnecting wires, and each section consists of two parallel rectangular conductors; the bottom of the silicon substrate is provided with a plurality of groups of RDL interconnecting wires, each group is composed of three discontinuous sections of RDL interconnecting wires at the bottom, and each section is composed of two parallel rectangular conductors; the multiple groups of top interconnection lines, the coupling units and the RDL interconnection lines are connected to form a zigzag balun total coupling path; the balance input end is connected with the third top interconnection line of the rightmost group to form an L-shaped input path; an opening is formed in the middle of one rectangular conductor of the second section of top interconnection line in the middle group, and the unbalanced output end is led out from two sides of the open end; the first grounding through hole is connected to the first section of top interconnection line of the leftmost group, and the second grounding through hole is connected to the third section of top interconnection line of the rightmost group.
Compared with the prior art, the invention has the following advantages:
firstly, as the coupling units formed by coupling TSV in pairs are added below the top metal layer, and the RDL interconnection layer at the bottom of the silicon substrate is added, the coupling units can prolong the length of a coupling path to improve the integration density, and the RDL interconnection layer does not occupy the layout space of a wiring layer, so that the problems of large layout space occupation and limited application in a high-integration-density scene in the prior art are solved, and the high-integration-density integrated circuit has the advantage of higher integration density.
Secondly, as the top interconnection layer, the TSV coupling units and the bottom RDL interconnection layer are vertically connected to form the three-dimensional balun structure, unbalanced input and balanced output of the balun circuit can be arranged at the top or the bottom of the silicon substrate according to different application scenes, and the problem that additional wiring and through holes are added to introduce interconnection crosstalk and noise is solved, so that the three-dimensional balun structure has the advantage of smaller vertical interconnection crosstalk and noise.
Thirdly, as the TSV manufacturing process and the RDL manufacturing process are added in the balun manufacturing process, the problems that the wiring space utilization rate of the existing balun manufacturing process is low, and the frequency range and the performance are limited are solved, so that the balun manufacturing process has the advantages of being high in space utilization rate and wide in selectable frequency range.
Drawings
FIG. 1 is a schematic diagram of a three-dimensional structure of a balun according to the present invention;
FIG. 2 is a schematic cross-sectional view of a balun according to the present invention;
FIG. 3 is a schematic diagram of an equivalent circuit of a Marchand type balun of the present invention;
FIG. 4 is a schematic cross-sectional view of a top interconnect layer of the present invention;
fig. 5 is a schematic cross-sectional view of a bottom RDL interconnect layer of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Referring to fig. 1, the present invention includes a silicon substrate 15, and a plurality of sets of top interconnection lines, two ground vias 10 and 11, a plurality of sets of TSV coupling units, and a plurality of sets of bottom RDL interconnection lines sequentially disposed on the silicon substrate 15. Each TSV coupling unit comprises two adjacent TSVs, coupling effect is formed between the TSVs through parasitic effect, and capacitive coupling plays a main role; TSV is formed by a very thin layer of SiO2The shape of the solid copper column wrapped by the insulating layer can be cylindrical, cuboid or truncated cone. The top interconnection lines are positioned on the top of the silicon substrate, each group consists of three discontinuous top interconnection lines, and each section consists of two parallel rectangular conductors; the multiple groups of RDL interconnecting lines are positioned at the bottom of the silicon substrate, each group is composed of three discontinuous bottom RDL interconnecting lines, and each section is also composed of two parallel rectangular conductors.
The top interconnection line, the coupling unit and the RDL interconnection line are sequentially connected to form a zigzag balun total coupling path: the total coupling path can be formed by one or more W-shaped sub-coupling paths, and the single sub-coupling paths are formed by sequentially connecting a first section of top interconnection line 1, a first coupling unit 4, a first section of RDL interconnection line 8, a second coupling unit 5, a second section of top interconnection line 2, a third coupling unit 6, a second section of RDL interconnection line 9, a fourth coupling unit 7 and a third section of top interconnection line 3. The W-shaped coupling path can also be converted to an M-shaped path by exchanging the shapes and connection orders of the top interconnect line and the RDL interconnect line. The total length of the coupling path is mainly determined by the frequency band range of the designed balun, and the longer the coupling path, the lower the working frequency band.
The input and output port of the balun comprises a balanced input end 12 and two balanced output ends 13 and 14, wherein the balanced input end 12 is led out from the top interconnection line 3 of the rightmost group. Two unbalanced output terminals 13 and 14 are led out from two sides of the middle opening of the top interconnection line 2 of the middle group, and two grounding through holes 10 and 11 are respectively connected with the top interconnection lines on the leftmost side and the rightmost side and are used for connecting a circuit common ground.
The structure of the present invention is mainly different from the planar balun of the prior art in that: the planar balun structure mainly utilizes the coupling effect between interconnection lines in the metal layer, and no matter the coupling is formed by the wide side or the narrow side of the metal line, a large amount of layout wiring space is occupied; the TSV is located in the substrate which cannot be wired originally, the equivalent coupling path length is improved through coupling between the TSV on the premise that wiring of the interconnection layer is not increased, namely, a part of horizontal plane space occupied originally is converted to a vertical plane, and the whole integration level of the circuit is equivalently improved. Meanwhile, because the balun of the invention is of a three-dimensional structure, the input and the output can be arranged at the top of a conventional substrate or at the bottom of the substrate optionally, and the balun can be better applied to special application scenes such as vertical stacked packaging and the like by combining a three-dimensional packaging process, and because additional leads and through holes are required to be added to the planar balun structure, more signal crosstalk and noise can be introduced.
Referring to fig. 2, the silicon substrate may be divided from top to bottom into a top interconnect region 16, an active region 17, a substrate 18 and an RDL interconnect region 19. The top interconnection area 16 includes a top interconnection line and a top dielectric layer, the active area 17 is a reserved area for manufacturing active devices, the TSV is located between the top interconnection area 16 and the RDL interconnection area 19, and the RDL interconnection area 19 includes a bottom RDL interconnection line and a bottom dielectric layer.
The structure of the invention realizes the function of a Marchand type balun circuit, and an equivalent circuit of the Marchand type balun circuit refers to an attached figure 3. The structure of the present invention can be viewed as being formed entirely of two sections of 1/4 λ electrical length of coupled transmission lines connected in series, where λ is the wavelength at the center frequency. One side of the coupling transmission line is an unbalanced input part, wherein one end of the coupling transmission line is connected with the input, and the other end of the coupling transmission line is open-circuited. The other side of the coupled transmission line is provided with two unbalanced output parts which are respectively composed of a section of 1/4 lambda transmission line, one end of each section of transmission line is connected with the output, and the other end of each section of transmission line is grounded. A Marchand balun converts the input to balanced outputs 180 ° out of phase and of equal magnitude, each balanced output port having 1/2, about-3 dB, of the input power, without taking into account non-ideal effects such as conductor and substrate losses.
The center frequency of the on-chip balun embodiment of the present invention is 60GHz, and its dimensions and interconnection layout are as follows:
the diameter of TSV is 8 μm, the length is 80 μm, and the aspect ratio is 10: 1;
the conductor pattern of the top interconnect layer is shown in fig. 4, where L1 ═ 420 μm, L2 ═ 80 μm, L3 ═ 140 μm, L4 ═ 80 μm, W1 ═ 17.5 μm, W2 ═ 17.5 μm, D1 ═ 35 μm, and D2 ═ 8.8 μm;
a bottom RDL interconnect layer diagram refers to fig. 5, where W3 ═ 10 μm, W4 ═ 10 μm, L5 ═ 158 μm, and L6 ═ 158 μm.
The manufacturing method of the on-chip balun is implemented according to the following steps:
the manufacturing mainly comprises three steps, namely manufacturing the TSV coupling unit, the top interconnection layer and the bottom RDL interconnection layer in sequence:
etching two adjacent through holes on the top of a silicon substrate by an etching process, wherein the diameter of each TSV is 8 micrometers, and the distance between the TSV and the through holes is 5 micrometers; sequentially depositing SiO on the outer side wall of the through hole by a chemical vapor deposition process2The insulating layer, the Ti seed layer and the Cu protective layer are filled with copper in the through hole through an electroplating method to form a complete TSV coupling unit;
secondly, manufacturing conductor patterns and through hole patterns on a silicon substrate through a copper Damascus process, wherein the conductor patterns are rectangles which are parallel to each other in pairs to form a top interconnection line structure, the shape of the top interconnection line structure is shown in figure 4, the through hole patterns are positioned on the upper layer of the conductor patterns, the diameter of the through hole patterns is 5 mu m, grounding through holes are formed, and then SiO is deposited on the through hole patterns2Forming a top dielectric layer;
step three, constructing a bottom RDL interconnection line: adding a substrate carrier on the top of the silicon substrate, then inverting the substrate carrier, thinning the silicon substrate to 80 microns in thickness through a chemical mechanical polishing process, and constructing a bottom interconnection line on the bottom of the silicon substrate through an RDL (remote description language) process: firstly, forming two-by-two parallels by photoetching and etching processWith reference to fig. 5, and electroplating 10 μm copper to form the bottom RDL interconnect structure, followed by deposition of SiO thereon2And forming a bottom dielectric layer.
The center frequency of the constructed embodiment is 60GHz, the phase balance degree is less than 10 degrees and the amplitude balance degree is less than 1dB in the frequency band range of 40GHz-110GHz, and the conventional use requirements are met; its planar electric size is about 0.001 lambda2And is far smaller than the plane structure balun under the same working frequency band.
Claims (4)
1. A TSV coupled and RDL interconnected on-chip passive balun comprises a silicon substrate (15), and a plurality of sections of top interconnection lines and two grounding through holes (10) and (11) which are sequentially arranged on the silicon substrate (15), and is characterized by further comprising a plurality of groups of coupling units formed by two-to-two capacitive coupling of TSVs and a plurality of sections of bottom RDL interconnection lines; the top of the silicon substrate (15) is provided with a plurality of groups of interconnecting wires, each group consists of three discontinuous top interconnecting wires, and each section consists of two parallel rectangular conductors; the bottom of the silicon substrate (15) is provided with a plurality of groups of RDL interconnecting wires, each group consists of two discontinuous sections of RDL interconnecting wires at the bottom, and each section consists of two parallel rectangular conductors; the multiple groups of top interconnection lines, the coupling units and the RDL interconnection lines are connected to form a zigzag balun total coupling path; the balance input end (12) is connected with the third section of top interconnection line (3) to form an L-shaped input path; an opening is formed in the middle of one rectangular conductor of the second top interconnection line (2) of the middle group, and the unbalanced output ends (13) and (14) are led out from two sides of the opening; the first grounding through hole (10) is connected to the first top interconnecting line (1) of the leftmost group, and the second grounding through hole (11) is connected to the third top interconnecting line (3) of the rightmost group.
2. The TSV coupled and RDL interconnected on-chip passive balun according to claim 1, characterized in that the total balun coupling path is formed by connecting single or multiple W-shaped sub-coupling paths in series, wherein each sub-path is formed by connecting a first section of top interconnection line (1), a first coupling unit (4), a first section of RDL interconnection line (8), a second coupling unit (5), a second section of top interconnection line (2), a third coupling unit (6), a second section of RDL interconnection line (9), a fourth coupling unit (7) and a third section of top interconnection line (3) in sequence; the W-shaped sub-coupling path can also be converted into an M-shaped path by exchanging the shapes and connection orders of the top interconnection lines (1), (2), (3) and the RDL interconnection lines (8), (9).
3. The passive balun on a chip with TSV coupling and RDL interconnection as claimed in claim 1, wherein the TSVs in the four coupling units are solid copper cylinders with cylindrical, rectangular parallelepiped or truncated cone shape wrapped by an insulating layer.
4. A TSV coupling and RDL interconnection on-chip passive balun manufacturing process is characterized in that a TSV structure is constructed through etching, chemical vapor deposition and electroplating processes, and an RDL interconnection line is constructed at the bottom of a silicon substrate (15) through chemical mechanical polishing, photoetching and etching processes, wherein the manufacturing process of the balun comprises the following steps:
step 1, constructing a coupling unit: etching two adjacent through holes on the top of the silicon substrate (15) by an etching process, and sequentially depositing SiO on the outer side walls of the through holes by a chemical vapor deposition process2The insulating layer, the Ti seed layer and the Cu protective layer are filled with copper in the through hole through an electroplating method to form a complete coupling unit;
step 2, constructing a top interconnection line: manufacturing conductor patterns and through hole patterns on a plane where the tops of the coupling units are located through a copper damascene process, wherein the conductor patterns are rectangles which are parallel in pairs to form a top interconnection line structure, the through hole patterns are located on the upper layer of the conductor patterns to form a grounding through hole structure, and then depositing an insulating medium on the grounding through hole structure;
step 3, constructing a bottom RDL interconnection line: adding a substrate carrier on the top of a silicon substrate (15), inverting the substrate carrier, thinning the silicon substrate (15) to a specified thickness through a chemical mechanical polishing process, forming two parallel rectangular wire grooves on the bottom of the silicon substrate (15) through photoetching and etching processes, electroplating copper to form a bottom RDL interconnection line structure, and depositing an insulating medium on the bottom RDL interconnection line structure.
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Cited By (4)
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| CN114430097A (en) * | 2021-12-01 | 2022-05-03 | 西安电子科技大学 | Through-silicon-via type open-ended resonant ring band-stop filter for three-dimensional integrated circuit |
| CN114512783A (en) * | 2022-01-12 | 2022-05-17 | 西安电子科技大学 | Three-dimensional on-chip annular directional coupler based on coaxial through-silicon-via process |
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| CN114141472A (en) * | 2021-01-19 | 2022-03-04 | 西安电子科技大学 | High-integration high-shielding transformer structure based on through holes |
| CN114141472B (en) * | 2021-01-19 | 2024-01-16 | 西安电子科技大学 | High-integration high-shielding transformer structure based on penetrating through holes |
| CN114430097A (en) * | 2021-12-01 | 2022-05-03 | 西安电子科技大学 | Through-silicon-via type open-ended resonant ring band-stop filter for three-dimensional integrated circuit |
| CN114512783A (en) * | 2022-01-12 | 2022-05-17 | 西安电子科技大学 | Three-dimensional on-chip annular directional coupler based on coaxial through-silicon-via process |
| CN114512783B (en) * | 2022-01-12 | 2022-11-08 | 西安电子科技大学 | Three-dimensional on-chip annular directional coupler based on coaxial through-silicon-via process |
| CN117525784A (en) * | 2023-11-14 | 2024-02-06 | 安徽蓝讯通信科技有限公司 | LTCC miniaturized millimeter wave filtering-power division-balun module |
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