CN111817677A - High-pass filter based on three-dimensional capacitance and inductance and preparation method - Google Patents
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- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
Abstract
The invention belongs to the technical field of semiconductors, and particularly relates to a high-pass filter based on three-dimensional capacitance and inductance and a preparation method thereof. According to the high-pass filter, the capacitor inductor has a three-dimensional structure and is simultaneously integrated in the TSV; the method comprises the steps that a plurality of groups of separated capacitance inductors exist on a substrate, the capacitance and the inductance are connected in series to form a high-pass filter through electrodes of the capacitance and the inductance, signals are input at a capacitance end, and signals are output from an inductance end; and the frequency of the high-pass filter is adjusted by designing parameters of the capacitors and the inductors and connecting different capacitors and inductors through rewiring. The invention can effectively reduce the area occupied by the high-pass filter, integrates the high-pass filter near a chip in a three-dimensional integrated system, effectively shortens interconnection delay and reduces interconnection loss, and greatly improves the integration level.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a high-pass filter based on a three-dimensional capacitor inductor and a preparation method thereof.
Background
With the advent of the intelligent age, the demand for integration of integrated circuits has increased, but the feature size of devices has approached physical limits. In order to further improve the performance and the integration level, some researchers can greatly improve the functional density of the chip by integrating the chip with a heterogeneous system in a three-dimensional direction. However, in the three-dimensional heterogeneous system integration process, the size of each component seriously affects the size of system integration. In particular, some planar passive devices, such as filters, etc., are large in size and occupy a large planar area of the system. The three-dimensional capacitive inductor is vertically prepared in the substrate of silicon and other types, and the electrodes are only connected on the surface, so that the size of the filter is greatly reduced, the functional density of silicon in the vertical direction is effectively improved, and powerful technical support is provided for realizing three-dimensional heterogeneous integration, and the three-dimensional capacitive inductor has very important significance.
At present, filters required by three-dimensional heterogeneous system integration are all planar, and are only interconnected with other devices by silicon through holes (TSV), so that only a small part of area is reduced, and the filters really occupy silicon surfaces or larger areas of the filters. Therefore, the high-pass filter based on the TSV three-dimensional capacitance and inductance is very promising for research and business.
Disclosure of Invention
The invention aims to provide a three-dimensional capacitance and inductance based high-pass filter with small area and high integration level and a preparation method thereof.
The invention provides a high-pass filter based on three-dimensional capacitance and inductance, which comprises: the method comprises the following steps that a plurality of groups of separated capacitor inductors on a substrate are connected in series through electrodes of the capacitor and the inductor, signals are input at a capacitor end, signals are output from an inductor end, and the frequency of a high-pass filter is adjusted through designing parameters of the capacitor and the inductor, rewiring and connecting different capacitors and inductors; wherein, three-dimensional capacitance inductance is integrated in the silicon through-hole simultaneously, includes:
a substrate formed with a through-silicon via;
the three-dimensional capacitor is formed on the side wall of the silicon through hole and sequentially comprises a first metal layer, a second insulating layer and a second metal layer;
the three-dimensional inductor is formed by rewiring of center filling metal and plane thick metal of the silicon through hole;
a first insulating layer is arranged between the side wall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is arranged between the three-dimensional capacitor and the three-dimensional inductor.
In the device of the present invention, preferably, the second insulating layer is made of a high-K dielectric material, and the first insulating layer and the third insulating layer are made of silicon oxide or silicon nitride.
In the device of the present invention, preferably, the first metal layer and the second metal layer are Cu, TiN, or Cr.
In the device of the present invention, preferably, the substrate is made of high-resistance silicon, glass, BT resin, or a flexible substrate.
In the device of the present invention, preferably, the adjusting the frequency of the high-pass filter by designing parameters of capacitance and inductance and rewiring different capacitances and inductances includes:
designing inductance parameters: the inductance is adjusted by adjusting the number of the through silicon vias, changing the arrangement mode of the through silicon vias and the relative position of the through silicon vias of the ground wire;
designing a capacitance parameter: the capacitance is adjusted by improving the dielectric constant of the middle medium of the through silicon via side wall capacitor and preparing a multi-layer side wall capacitor structure;
and the capacitors with different areas and the inductance coils with different numbers are connected by wiring.
The invention also provides a preparation method of the high-pass filter based on the three-dimensional capacitance and inductance, which comprises the following steps:
etching a substrate to form a blind hole;
forming a first insulating layer in the blind holes and on the surface of the substrate;
forming each layer of the three-dimensional capacitor on the first insulating layer, wherein the steps of depositing a first metal layer, a second insulating layer and a second metal layer in sequence, removing redundant second insulating layers and redundant second metal layers through photoetching and etching to expose partial surfaces of the first metal layers, and removing redundant first metal layers through photoetching and etching to expose partial surfaces of the first insulating layers;
forming a third insulating layer so as to cover the second metal layer, the first metal layer and the first insulating layer;
electroplating metal, removing redundant metal by chemical mechanical polishing and dry etching, and only keeping the center filling metal in the blind hole as a part of the three-dimensional inductor;
respectively windowing the first metal layer and the second metal layer, and manufacturing a test or connection bonding pad; manufacturing a test or connection bonding pad of the three-dimensional inductor on the surface of the metal filled in the center of the blind hole;
temporarily bonding the front pattern of the protective substrate, carrying out mechanical grinding, polishing and dry etching on the back of the substrate to expose a back silicon through hole, and removing part of the first insulating layer, the first metal layer, the second insulating layer and the second metal layer at the bottom of the silicon through hole by dry etching until the center filling metal is exposed;
carrying out back insulation, photoetching and windowing, then depositing thick metal and etching to form interconnection, and forming a planar thick metal rewiring part of the three-dimensional inductor;
removing the temporary bonding to obtain a general substrate based on the three-dimensional capacitance and inductance; and connecting the capacitor and the inductor in series, inputting a signal at a capacitor end, and outputting a signal from an inductor end to obtain the high-pass filter based on the three-dimensional capacitor inductor.
In the preparation method of the present invention, preferably, the second insulating layer is a high-K dielectric material.
In the preparation method of the present invention, preferably, the first metal layer and the second metal layer are Cu, TiN, or Cr.
In the preparation method of the invention, preferably, the substrate is high-resistance silicon, glass, BT resin or flexible substrate.
In the preparation method, preferably, the frequency of the high-pass filter is adjusted by designing parameters of the capacitor and the inductor and re-wiring and connecting different capacitors and inductors, and the method specifically comprises the following steps:
designing inductance parameters: the inductance is adjusted by adjusting the number of the through silicon vias, changing the arrangement mode of the through silicon vias and the relative position of the through silicon vias of the ground wire;
designing a capacitance parameter: the capacitance is adjusted by improving the dielectric constant of the middle medium of the through silicon via side wall capacitor and preparing a multi-layer side wall capacitor structure;
and the capacitors with different areas and the inductance coils with different numbers are wired and connected, so that the frequency of the high-pass filter is adjusted.
The high-pass filter based on the three-dimensional capacitance and inductance can greatly reduce the occupied area of the filter. And the three-dimensional integrated circuit can be integrated near a chip in three-dimensional integration, so that the interconnection delay is effectively shortened, the interconnection loss is reduced, and the integration level is greatly improved.
Drawings
Fig. 1 is a flow chart of a method for preparing a high-pass filter based on three-dimensional capacitance and inductance.
FIGS. 2 to 14 show the structural schematic diagrams of the steps of the high-pass filter based on the three-dimensional capacitance and inductance.
Fig. 15 is a schematic diagram of a layout of a high-pass filter based on three-dimensional capacitance inductance.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly and completely understood, the technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. The described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Furthermore, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details. Unless otherwise specified below, each part in the device may be formed of a material known to those skilled in the art, or a material having a similar function developed in the future may be used.
The high-pass filter based on the three-dimensional capacitance inductor is provided with the three-dimensional capacitance inductor, the three-dimensional capacitance inductor value of the high-pass filter can be adjusted, electrodes of the capacitance inductor of the substrate are separately prepared, the capacitance and the inductor are connected in series, signals are input at a capacitance end, and signals are output from an inductor end.
The following will further describe the technical solution of the present invention by taking a method for preparing a three-dimensional capacitance and inductance based high-pass filter on a high-resistance silicon substrate as an example with reference to fig. 1 to 14. Fig. 1 is a flow chart of a method for manufacturing a three-dimensional capacitive-inductive high-pass filter, and fig. 2 to 14 are schematic structural diagrams of steps of the three-dimensional capacitive-inductive high-pass filter.
Step S1, forming blind vias by etching on the substrate. Specifically, high-resistance silicon is selected as the substrate 200, and a pattern is exposed thereon as a lithography original alignment pattern by using a standard optical lithography process. And (3) photoetching the thin photoresist to manufacture a through silicon via pattern, and etching a blind hole 201 with the thickness of 200 microns and the diameter of 50 microns by using a deep silicon etching method to obtain the structure shown in figure 2.
In step S2, silicon dioxide is formed as the first insulating layer 202 on the above structure by thermal oxidation, and the resulting structure is as shown in fig. 3. The thickness of the silicon dioxide is preferably 500nm, and the thicker insulating layer can effectively reduce the capacitance and the inductance brought by the substrate. Then, 200nm silicon nitride is deposited by chemical vapor deposition (PECVD) to relieve the stress of the silicon dioxide, although other methods of relieving the stress may be used.
Step S3, as shown in fig. 4 to 5, forming each layer of the three-dimensional capacitor on the first insulating layer, including depositing the first metal layer 203, the second insulating layer 204, and the second metal layer 205 in sequence, and removing the redundant second insulating layer 204 and the redundant second metal layer 205 by photolithography and etching to expose part of the surface of the first metal layer 203, and removing the photoresist. And then, removing the redundant first metal layer 203 by photoetching, exposing part of the surface of the first insulating layer 202, and removing the photoresist. The first metal layer and the second metal layer are preferably metals such as Cu, TiN, and Cr. The second insulating layer is preferably HfO2And high-K dielectric materials. The first metal layer, the second metal layer and the second insulating layer can be prepared by Atomic Layer Deposition (ALD), sputtering and the like.
In step S4, a third insulating layer 206 is formed to cover the second metal layer 205, the first metal layer 203 and the first insulating layer 202, and the resulting structure is shown in fig. 6.
Step S5, deposit a seed layer and plate metal 207, as shown in fig. 7. Then, the chemical mechanical polishing is performed to remove most of the metal Cu, then, the annealing is performed to remove the stress between the Cu and the silicon dioxide, then, the dry etching is performed to remove the residual Cu and the protruding Cu in the hole, only the center filling metal 207 in the blind hole is remained to be used as a part of the three-dimensional inductor, and the obtained structure is shown in fig. 8.
In step S6, windows are opened on the first metal layer 203 and the second metal layer 205, respectively, to manufacture testing or connection pads 208 and 209, i.e. the external capacitor electrode and the internal capacitor electrode, and the resulting structure is shown in fig. 9.
In step S7, a test or connection pad 210 of the three-dimensional inductor, i.e., an inductor electrode, is formed on the surface of the metal 207 filled in the center of the blind via.
In step S8, the transparent glass 212 is temporarily bonded to the front surface of the substrate 200 by the temporary bonding paste 211, so as to protect the front surface pattern, and the resulting structure is shown in fig. 10. The back of the substrate 200 was mechanically ground and polished to remove 300 microns thick silicon (the total thickness of the silicon substrate was 525 microns), stopping at 25 microns from the bottom of the blind via, resulting in the structure shown in fig. 11. Then, dry etching is performed to expose the back silicon through hole, and dry etching is performed to remove a part of the first insulating layer 202, the first metal layer 203, the second insulating layer 204 and the second metal layer 205 at the bottom of the silicon through hole until the center filling metal 207 is exposed, so that the structure is shown in fig. 12.
Step S9, performing back insulation, performing photolithography and etching to form a window, depositing thick metal, and etching to form an interconnection, thereby forming a planar thick metal rewiring portion 213 of the three-dimensional inductor, and the resulting structure is shown in fig. 13.
Step S10, removing the temporary bond, and molding the universal silicon substrate, the resulting structure is shown in fig. 14.
And step S11, connecting the capacitance and the inductance in series or in parallel through wire bonding or wiring, and adding the required resistance through thick metal rewiring to obtain the required high-pass filter. As shown in fig. 15, the capacitive inner electrode 208 and the inductive electrode 210 are connected in series, and a signal is input from the capacitive inner electrode 208 and output from the other inductive electrode 210, thereby forming a high-pass filter. The inductance can be adjusted by adjusting the number of the TSVs, changing the arrangement mode of the TSVs and the relative position of the ground wire TSVs; and the dielectric constant of the TSV side wall capacitor intermediate medium is improved, and a multilayer side wall capacitor structure is prepared to adjust the capacitor. Thus, the frequency of the filter can be adjusted.
As shown in fig. 14 and 15, the three-dimensional capacitance-inductance-based high-pass filter of the present invention has a three-dimensional capacitance-inductance, and the electrodes of the capacitance-inductance of the substrate are separated, and the capacitance inner electrode 208 is connected in series with the inductance electrode 210, and a signal is input from the capacitance inner electrode 208 and output from the other inductance electrode 210. Wherein, three-dimensional capacitive inductance includes: a substrate 200 formed with through-silicon vias; and the three-dimensional capacitor is formed on the side wall of the through silicon via and sequentially comprises a first metal layer 203, a second insulating layer 204 and a second metal layer 205. A three-dimensional inductor, which is composed of a center filling metal 207 of a through silicon via and a plane thick metal rewiring 213; a first insulating layer 202 is disposed between the sidewall of the through-silicon via and the three-dimensional capacitor, and a third insulating layer 206 is disposed between the three-dimensional capacitor and the three-dimensional inductor.
The high pass filter is frequency adjustable. The frequency of the high-pass filter is adjusted by designing parameters of the capacitors and the inductors and connecting different capacitors and inductors through rewiring. The inductance value can be adjusted by adjusting the number of the TSVs, changing the arrangement mode of the TSVs and the relative position of the ground wire TSVs. The capacitance value can be adjusted by improving the dielectric constant of the TSV side wall capacitor intermediate medium and preparing a multi-layer side wall capacitor structure. And the capacitors with different areas and the inductance coils with different numbers are connected by wiring.
Preferably, the second insulating layer is a high-K dielectric material, such as HfO2And the like. The first metal layer and the second metal layer are made of Cu, TiN, Cr and other metals. The substrate can be made of high-resistance silicon, glass, Bismaleimide Triazine (BT) resin, flexible substrate and the like. The first insulating layer and the third insulating layer may be silicon oxide, silicon nitride, or the like. The center-fill metal is preferably Cu, W, or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (10)
1. A high-pass filter based on three-dimensional capacitance inductance is characterized by comprising a plurality of groups of three-dimensional capacitance inductances on a substrate, wherein the capacitance and the inductance are connected in series by rewiring electrodes of the capacitance and the inductance, a signal is input at a capacitance end, and a signal is output from an inductance end;
the frequency of the high-pass filter is adjusted by designing parameters of the capacitors and the inductors and connecting different capacitors and inductors through rewiring; wherein, three-dimensional capacitance inductance is integrated in the silicon through-hole simultaneously, includes:
a substrate formed with a through-silicon via;
the three-dimensional capacitor is formed on the side wall of the silicon through hole and sequentially comprises a first metal layer, a second insulating layer and a second metal layer;
the three-dimensional inductor is formed by rewiring of center filling metal and plane thick metal of the silicon through hole;
a first insulating layer is arranged between the side wall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is arranged between the three-dimensional capacitor and the three-dimensional inductor.
2. The three-dimensional capacitive-inductor based high-pass filter according to claim 1, wherein the second insulating layer is a high-K dielectric material, and the first insulating layer and the third insulating layer are silicon oxide or silicon nitride.
3. The three-dimensional capacitive-inductor based high-pass filter according to claim 1, wherein the first metal layer and the second metal layer are Cu, TiN or Cr.
4. The three-dimensional capacitive-inductance-based high-pass filter according to claim 1, wherein the substrate is high-resistance silicon, glass, BT resin or flexible substrate.
5. The three-dimensional capacitance and inductance based high-pass filter according to claim 1, wherein the adjusting of the frequency of the high-pass filter by designing parameters of capacitance and inductance and rewiring different capacitances and inductances specifically comprises:
designing inductance parameters: the inductance is adjusted by adjusting the number of the through silicon vias, changing the arrangement mode of the through silicon vias and the relative position of the through silicon vias of the ground wire;
designing a capacitance parameter: the capacitance is adjusted by improving the dielectric constant of the middle medium of the through silicon via side wall capacitor and preparing a multi-layer side wall capacitor structure;
and the capacitors with different areas and the inductance coils with different numbers are connected by wiring.
6. A preparation method of a high-pass filter based on a three-dimensional capacitance inductor is characterized by comprising the following specific steps:
etching a substrate to form a blind hole;
forming a first insulating layer in the blind holes and on the surface of the substrate;
forming each layer of the three-dimensional capacitor on the first insulating layer, wherein the steps of depositing a first metal layer, a second insulating layer and a second metal layer in sequence, removing redundant second insulating layers and redundant second metal layers through photoetching and etching to expose partial surfaces of the first metal layers, and removing redundant first metal layers through photoetching and etching to expose partial surfaces of the first insulating layers;
forming a third insulating layer so as to cover the second metal layer, the first metal layer and the first insulating layer;
electroplating metal, removing redundant metal by chemical mechanical polishing and dry etching, and only keeping the center filling metal in the blind hole as a part of the three-dimensional inductor;
respectively windowing the first metal layer and the second metal layer, and manufacturing a test or connection bonding pad;
manufacturing a test or connection bonding pad of the three-dimensional inductor on the surface of the metal filled in the center of the blind hole;
temporarily bonding the front pattern of the protective substrate, carrying out mechanical grinding, polishing and dry etching on the back of the substrate to expose a back silicon through hole, and removing part of the first insulating layer, the first metal layer, the second insulating layer and the second metal layer at the bottom of the silicon through hole by dry etching until the center filling metal is exposed;
carrying out back insulation, photoetching and windowing, then depositing thick metal and etching to form interconnection, and forming a planar thick metal rewiring part of the three-dimensional inductor;
removing the temporary bonding to obtain a general substrate based on the three-dimensional capacitance and inductance;
and connecting the capacitor and the inductor in series, inputting a signal at a capacitor end, and outputting a signal from an inductor end to obtain the high-pass filter based on the three-dimensional capacitor inductor.
7. The method for preparing the three-dimensional capacitance and inductance based high-pass filter according to claim 6, wherein the second insulating layer is a high-K dielectric material.
8. The method for preparing the three-dimensional capacitance and inductance based high-pass filter according to claim 6, wherein the first metal layer and the second metal layer are Cu, TiN or Cr.
9. The method for preparing the three-dimensional capacitance and inductance based high-pass filter according to claim 6, wherein the substrate is high-resistance silicon, glass, BT resin or flexible substrate.
10. The method for preparing the high-pass filter based on the three-dimensional capacitance and inductance is characterized in that the frequency of the high-pass filter is adjusted by designing parameters of the capacitance and the inductance and connecting different capacitances and inductances through rewiring; the method specifically comprises the following steps:
designing inductance parameters: the inductance is adjusted by adjusting the number of the through silicon vias, changing the arrangement mode of the through silicon vias and the relative position of the through silicon vias of the ground wire;
designing a capacitance parameter: the capacitance is adjusted by improving the dielectric constant of the middle medium of the through silicon via side wall capacitor and preparing a multi-layer side wall capacitor structure;
the capacitors with different areas and the inductance coils with different numbers are wired and connected;
thereby adjusting the frequency of the high pass filter.
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| WO2022222124A1 (en) * | 2021-04-23 | 2022-10-27 | 京东方科技集团股份有限公司 | Substrate integrated with passive device and preparation method therefor |
| CN114285387A (en) * | 2021-12-09 | 2022-04-05 | 电子科技大学 | Small LC filter and preparation method thereof |
| CN114285387B (en) * | 2021-12-09 | 2023-05-09 | 电子科技大学 | Small LC filter and preparation method thereof |
| WO2023163810A1 (en) * | 2022-02-28 | 2023-08-31 | Qualcomm Incorporated | Capacitor embedded 3d resonator for broadband filter |
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