JP5005856B2 - Method of forming an inductor for a high performance integrated circuit overlaying a surface of a semiconductor substrate - Google Patents

Description

[0001]
This application is a continuation-in-part of US patent application Ser. No. 09 / 216,791, filed Dec. 21, 1998.
[0002]
BACKGROUND OF THE INVENTION
The present invention relates to the manufacture of high performance integrated circuits (ICs), and more particularly, by reducing high frequency electrical components (e.g., inductors) on the surface of a semiconductor substrate by reducing electromagnetic losses typically experienced at the surface of the semiconductor substrate. It relates to a method of manufacturing.
[0003]
[Prior art and problems to be solved by the invention]
A constant emphasis in semiconductor technology is to produce semiconductor devices with improved performance at a low cost. These key developments over the years have resulted in extreme miniaturization of semiconductor devices, which is made possible by a combination of semiconductor processes and constant advances in semiconductor materials and high-performance new device designs. It was. Most of the semiconductor devices manufactured today are intended to process digital data. However, there are many semiconductor designs and approaches that are aimed at incorporating analog functionality into elements that process digital and analog data simultaneously, or elements that can be used to process only analog data. One of the major problems in manufacturing analog processing circuits (using digital processing procedures and equipment) is that many of the elements used for analog circuits are generally sub-micron due to their large size. It is not easy to integrate into a device having a characteristic size close to the above range. The main elements that cause these problems are capacitors and inductors. This is because all of these elements are considerably larger in the case of a normal analog processing circuit.
[0004]
The inductor of the present invention is generally applicable in the field of the latest mobile communication applications using a compact high-frequency device. While constant improvements to the performance characteristics of this device have been achieved over the years, further improvements have been made to reduce device power consumption, reduce device size, increase available frequencies, and lower noise levels. The emphasis will be on improvement. One of the main uses of semiconductor devices in the field of mobile communications is in the manufacture of radio frequency (RF) amplifiers. An RF amplifier includes many standard elements. A main element of a general RF amplifier is a tuning circuit including an inductive element and a capacitive element. The tuning circuit depends on the values of the inductive and capacitive elements and, depending on these values, forms a frequency-dependent impedance, which makes the tuning circuit high for signals of a certain frequency. Impedance or low impedance can be provided. Thus, the tuning circuit can reject or pass the analog signal component based on the frequency of the analog signal component, and can further amplify the analog signal component. In this manner, the tuning circuit can be used as a filter for removing or removing a signal at a specific frequency, or for removing noise from a circuit component intended for analog signal processing. The tuning circuit can also be used to create a high electrical impedance by using the LC resonance of the circuit and thereby reduce the effects of parasitic capacitance that is part of the circuit. One of the problems that arise when fabricating inductors on the surface of a semiconductor substrate is high due to self-resonance caused by the parasitic capacitance between the (spiral) inductor and its underlying substrate. The use of inductors at frequencies is limited. In designing such an inductor, it is important to reduce electrostatic coupling between the fabricated inductor and the lower substrate.
[0005]
At high frequencies, the electromagnetic field generated by the inductor generates eddy currents in the lower silicon substrate. Since the silicon substrate is a resistive conductor, eddy currents consume electromagnetic energy and thus energy loss increases, resulting in a lower Q value for the capacitor. This is the main reason for the low Q value of the capacitor, so the resonant frequency of 1 / √ (LC) only limits the upper frequency limit. In addition, eddy currents induced by the inductor interfere with the performance of circuits that are physically very close to the capacitor.
[0006]
As already pointed out, one of the important elements used in making high frequency analog semiconductor elements is an inductor that forms part of an LC resonant circuit. In view of the high device density commonly found in semiconductor devices and the resulting intense use of the substrate surface area, inductors are manufactured for inductors while maintaining a high Q value for the inductor. It must incorporate the miniaturization of the required surface area. In general, an inductor manufactured on the surface of a substrate has a spiral shape, whereby a spiral-shaped object is formed in a plane parallel to the plane of the substrate. Conventional methods used to make inductors on the surface of a substrate are subject to several contracts. Most inductors with high Q values form part of a hybrid element structure or monolithic microwave integrated circuit (MMIC), or are made as discrete elements, but such fabrication is common in integrated circuits Integration into a simple manufacturing process is not easy. What can be said clearly is that by creating a circuit for the purpose of analog data manipulation and analog data storage on one monolithic semiconductor substrate, combining digital data manipulation and digital data storage functions, Many important advantages are achieved. Such advantages include reduced manufacturing costs and reduced power consumption of combined functions. However, due to the spiral shape of the inductor fabricated on the surface of the semiconductor substrate or the physical size of the line ductor, parasitic capacitance occurs between the inductor wiring and the lower substrate, causing A loss of electromagnetic energy is caused in the resistive silicon substrate on the side. These parasitic capacitances have a significant adverse effect on the functionality of the fabricated LC circuit by sharply reducing the resonant frequency of the tuning circuit being used. More seriously, the electromagnetic field generated by the inductor generates eddy currents in the lower resistive silicon substrate, which causes significant energy loss and lowers the Q value of the inductor.
[0007]
Inductor performance parameters are generally expressed as inductor quality (Q) factors. The quality factor Q of the inductor is defined as Q = Es / El, where Es is the energy stored in the reactive part of the device and El is the energy lost in the reactive part of the device. The higher the quality of the element, the closer the resistance value of the element approaches zero, and the Q factor of the element approaches infinity. In the case of an inductor made with a silicon substrate overlaid, the electromagnetic energy created by the inductor is lost primarily in the underlying resistive silicon substrate and in the metal wire being made to form the inductor. . The quality factor for the element is different from the quality associated with the filter or resonator. For a device, the quality factor serves as a measure of the purity of the reactance (or susceptance) of the device. The purity of reactance (or susceptance) may be reduced due to resistive silicon substrate, metal wire resistance, and dielectric loss. In practical arrangements, there are always some physical resistors that dissipate energy, thereby reducing the recoverable energy. The quality factor Q is a dimensionless value. When the Q value is greater than 100, the discrete inductor mounted on the surface of the printed circuit board is considered to have extremely high performance. For inductors that form part of an integrated circuit, the Q factor is typically in the range of about 3-10.
[0008]
When creating an inductor on a monolithic substrate on which additional semiconductor elements are fabricated, the upper limit of the cutoff frequency that can be achieved for inductors using conventional silicon processes due to the parasitic capacitance that occurs as part of this fabrication Is limited. For many applications, this limitation is unacceptable. Depending on the frequency at which the LC circuit is designed to resonate, a fairly large value of quality factor (eg 50 or more) must be obtained. In this regard, the prior art is limited to obtaining higher quality factor values as separate units and integrating these separate units and surrounding device functions. This negates the advantages obtained when using a monolithic structure in which the inductor and surrounding elements are made on one and the same semiconductor substrate. Non-monolithic approaches also require additional wiring to interconnect assembly sub-components, which introduces additional parasitic capacitance and resistive losses throughout the interconnecting network have. In many RF amplifier applications (eg battery powered applications), power consumption is an important point and should be as low as possible. Although increasing the power consumption can compensate to some extent for the effects of parasitic capacitance and resistive power loss, this approach also has limitations. With the rapid spread of wireless applications (such as mobile phones), there is a need for an immediate solution to these problems. Wireless communication is a rapidly expanding market, and the integration of RF integrated circuits is one of the most important issues. One approach is to significantly increase the operating frequency, for example in the range of 10-100 GHz. At such high frequencies, the quality factor values obtained from silicon-based inductors are significantly reduced. For applications in such a frequency range, monolithic inductors using materials other than silicon as the base for making inductors have been studied. Such a monolithic inductor is manufactured using, for example, sapphire or GaAs. These inductors have significantly less substrate loss than their counterparts using silicon (no eddy currents and hence no loss of electromagnetic energy), and thus inductors with much higher Q values are obtained. These inductors also have lower parasitic capacitance and thus have the ability to operate at higher frequencies. However, there is still a need to make silicon based inductors when more complex applications are required. For various applications, approaches using base materials other than silicon have proved too complex and inefficient, for example GaAs as a medium for fabricating semiconductor devices still has to be solved. There are technical challenges that must be addressed. GaAs has been shown to be a semi-insulating material at high frequencies, reducing electromagnetic losses that occur on the surface of the GaAs substrate and increasing the Q value of inductors fabricated on the GaAs surface. However, since a GaAs RF chip is expensive, a process that does not require the use of a GaAs RF chip is advantageous in terms of cost.
[0009]
Many different approaches have been attempted to incorporate the inductor into the semiconductor environment without sacrificing device performance due to substrate loss. One of these approaches is to selectively remove the silicon under the inductor by etching (using micromachining), thereby removing the effects of resistive energy loss and parasitic capacitance on the substrate. is there. Another method is to use multiple layers of metal (eg, aluminum) interconnects or copper damascene interconnects.
[0010]
Another approach uses a high resistivity silicon substrate, thereby reducing resistive loss in the silicon substrate. Resistive substrate loss at the surface of the lower substrate forms a major factor in determining the Q value of the silicon inductor. Furthermore, bias wells are arranged under the spiral conductor, and this is also intended to reduce induction loss on the surface of the substrate. A more complex approach is to create an active inductive element that simulates the electrical characteristics of the inductor when used in an active circuit. However, this approach consumes much power due to the simulated inductor and generates noise that is unacceptable for low power, high frequency applications. Both of these approaches have the common goal of increasing the quality (Q) value of the inductor and reducing the surface area required to make the inductor. The most important point in this regard is electromagnetic energy loss due to electromagnetically induced eddy currents in the silicon substrate.
[0011]
Reducing the integrated circuit geometry reduces the cost per die and improves some performance. Metal connections that connect integrated circuits to other circuits or system elements have become relatively important and, along with further miniaturization of ICs, have increasingly negative effects on circuit performance. ing. The parasitic capacitance and resistance of the metal interconnect increases, which significantly degrades chip performance. Most important in this regard is the voltage drop along the power and ground buses and the RC delay of the critical signal path. Attempting to reduce resistance by using wider metal lines results in greater capacitance of these wires.
[0012]
The latest method for fabricating an inductor on the surface of a semiconductor substrate is to fabricate the inductor under a passivation layer using a fine-line technique. However, this indicates that the physical distance between the fabricated inductor and the substrate surface on which the inductor is fabricated is extremely small (typically less than 10um), which results in large electromagnetic losses on the silicon substrate. Therefore, the Q value of the inductor is lowered. By increasing the distance between the inductor and the semiconductor surface, the electromagnetic field in the silicon substrate can be decreased inversely proportional to the distance, and the Q value of the inductor can be increased. Therefore, by creating an inductor that overlays the passivation layer (by post-passivation method), and additionally, creating an inductor on the surface of a thick dielectric (e.g. polymer) layer deposited or adhered on the surface of the passivation layer Thus, the Q value of the inductor can be increased. Furthermore, the parasitic resistance can be reduced by using a wide and thick metal to make the inductor. The method of the present invention applies these principles of post-passivation inductor fabrication, where the inductor is fabricated on a thick dielectric layer using a thicker and wider metal.
[0013]
U.S. Pat. No. 5,212,403 (Nakanishi) discloses a method of forming wiring connections for logic circuits depending on the length of the wiring connections on the inside and outside (in the wiring board on the chip).
[0014]
US Pat. No. 5,501,006 (Gehman, Jr. et al.) Discloses a structure incorporating an insulating layer between an integrated circuit (IC) and a wiring board. Distribution lead leads connect the IC bonding pads to the substrate bonding pads.
[0015]
U.S. Pat.No. 5,055,907 (Jacobs) is an extended integration that allows circuits to be integrated across chip boundaries by forming thin film multilayer wiring decals on support substrates and chips. A semiconductor structure is disclosed. However, this patent document is different from the present invention.
[0016]
US Pat. No. 5,106,461 (Volfson et al.) Discloses a multilayer interconnect structure comprising alternating combinations of polyimide (dielectric) and metal on an IC in a TAB structure.
[0017]
US Pat. No. 5,635,767 (Wenzel et al.) Discloses a method for reducing RC delay by PBGA isolating multiple metal layers.
US Pat. No. 5,686,764 (Fulcher) discloses a flip-chip substrate that reduces RC delay by isolating the power supply from the 1/0 trace.
[0018]
US Pat. No. 6,008,102 (Alfored et al.) Discloses a spiral inductor that uses two metal layers connected by a bias.
US Pat. No. 5,372,967 (Sundaram et al.) Discloses a helical inductor.
[0019]
US Pat. No. 5,576,680 (Ling) and US Pat. No. 5,884,990 (Burghartz et al.) Disclose other helical inductor designs.
[0020]
[Means for Solving the Problems]
A primary object of the present invention is to improve the RF performance of high performance integrated circuits.
Another object of the present invention is to provide a method for producing an inductor having a high Q value.
[0021]
Another object of the present invention is to replace a GaAs chip with a silicon chip as a base for producing an inductor having a high Q value.
Still another object of the present invention is to widen the frequency range of inductors fabricated on the surface of a silicon substrate.
[0022]
Yet another object of the present invention is to produce a high quality passive electrical device that overlays the surface of a silicon substrate.
In this continuation application, in a post-passivation sequence, a thick layer of dielectric is added over the passivation layer, and a wide and thick metal line is added over the thick layer of dielectric. The present invention extends this partially continued application to a wider range by further fabricating high quality electrical elements (e.g., inductors, capacitors, or resistors) on the passivation layer or on the surface of the thick dielectric layer. Yes. The method of the present invention further provides a method for mounting discrete passive electrical elements at a distance substantially away from the underlying silicon surface.
[0023]
This continuation-in-part application discloses an integrated circuit structure in which a re-distribution layer and an interconnect metal layer are made in a dielectric layer on the surface of a conventional IC. A passivation layer is deposited on the dielectric of the redistribution layer and the interconnect metal layer, and a thicker polymer layer is deposited on the surface of the passivation layer. In the present invention, high quality electrical elements are made on the surface of a thick polymer layer.
[0024]
The present invention is, among other things, manufacturing inductors using semiconductor device manufacturing methods and manufacturing procedures well known in the art (manufacturing high-Q inductors on the surface of a semiconductor substrate). Is focused on). Since the inductor of the present invention is of high quality, it can be used for high frequency applications while minimizing power loss. The present invention further addresses the fabrication of capacitors and resistors on the surface of a silicon substrate [the main objective of the method of the present invention for fabricating capacitors and resistors is therefore to form these in the underlying silicon substrate. It is to reduce the parasitic capacitances commonly caused by the device].
[0025]
Referring to FIG. 1 for a more specific description, a cross section of one embodiment of the present application is shown. Transistors and other elements (not shown in FIG. 1) are attached to the surface of the silicon substrate 10. The surface of the substrate 10 is covered with a dielectric layer 12, so that the dielectric layer 12 is deposited in the surface of the substrate 10 and on the elements mounted on the substrate 10. Conductive interconnect lines 11 are provided inside the layer 12, and these lines connect to the semiconductor elements supplied on the surface of the substrate 10.
[0026]
Layer 14 (two examples are shown) shows all of the metal and dielectric layers normally made on the dielectric layer 12, so the layer 14 shown in FIG. A plurality of dielectric layers, insulating layers, etc., and the conductive interconnect lines 13 constitute a network of electrical connections made throughout the layer 14. Electrical contacts 16 overlay layer 14 and are present on the surface of layer 14. These electrical contacts 16 may be, for example, bonding pads that reliably form electrical interconnects for transistors and other elements supplied on the surface of the substrate 10. These electrical contacts 16 are interconnection points within the IC assembly that need to be further connected to surrounding circuitry. A passivation layer 18 (eg, formed of silicon nitride) is deposited on layer 14 to prevent the lower layer from moisture and contamination.
[0027]
An important step of the application begins with depositing a thick polyimide layer 20 (depositing on the surface of layer 18). Access to electrical contact 16 must be provided, so that the pattern of openings 22, 36, and 38 is etched through polyimide layer 20 and passivation layer 18, and the pattern of openings 22, 36, and 38 is Align with the pattern. The electrical contacts 16 are electrically extended to the surface of the layer 20 by openings 22/36/38 made in the polyimide layer 20.
[0028]
The material used for the deposition of layer 20 is polyimide, but the material that can be used for this layer is not limited to polyimide and includes any known polymer (eg, SiClxOy). The above polyimide is a preferred material to be used for the method of the present invention in making the thick polymer layer 20. Examples of polymers that can be used include silicons, carbons, fluorides, chlorides, oxygens, parylene or Teflon, polycarbonate (PC), polystyrene (PS ), Polyoxide (PO), poly polooxide (PPO), and benzocyclobutene (BCB).
[0029]
Electrical contact with the contacts 16 can be ensured by filling the openings 22/36/38 with a conductive material. The upper surface 24 of these metal conductors is included in the openings 22/36/38 and can be used to connect the IC to its environment and further integrate into the surrounding electrical circuitry. This latter description allows the semiconductor elements attached to the surface of the substrate 10 to be further connected to surrounding elements and circuits via conductive interconnects contained in the openings 22/36/38. Is the same as saying. Interconnect pads 26 and 28 are formed on the surface 24 of the metal interconnect received in openings 22, 36, and 38. These pads 26 and 28 may be designs having any width and thickness as long as they can accommodate specific circuit design requirements. One pad can be used as a flip chip pad, for example. Other pads can be used for power distribution or as ground terminals or signal buses. For example, as shown in FIG. 1, the following connections can be made into pads: pad 26 can function as a flip chip pad and pad 28 can function as a flip chip pad Alternatively, it can be connected to a power source, ground terminal, or electrical signal bus. There is no connection between the pad size shown in FIG. 1 and the possible electrical connections that this pad can use. The pad size, standard practice, and constraints on designing the electrical circuit determine whether an electrical connection can be obtained for which a given pad is useful.
[0030]
The following description relates to the size and number of contacts 16 in FIG. Since these contacts 16 are located on a thin dielectric (layer 14 in FIG. 1), the pad size should not be too large. This is because a large capacitance is generated when the pad size is large. In addition, a large pad size interferes with the routing capability of the metal layer. Therefore, it is preferable to keep the size of the pad 16 relatively small. However, the size of the pad 16 is further directly related to the aspect ratio of the bias 22/36/38. In view of the etching and filling, the acceptable aspect ratio is about 5. Based on these considerations, the size of the contact pad 16 is on the order of 0.5 um to 30 um, and the exact size depends on the thickness of the layers 18 and 20.
[0031]
This application does not limit the number of contact pads that can be incorporated into a design, and this number depends on package design requirements. Layer 18 in FIG. 1 may be a general IC passivation layer.
[0032]
The most commonly used passivation layers in the state of the art are plasma enhanced CVD (PECVD) oxide layers and plasma enhanced CVD nitride layers. In forming the passivation layer 18, about 0.2um. Of PECVD oxide layer is deposited first, followed by about 0.7um. Of nitride layer. The passivation layer 18 is extremely important because it protects the device wafer from ionic contamination by moisture and foreign matter. It is very important to place this layer between the sub-micron process (for integrated circuits) and the tens-micron process (for interconnected metallization structures). This is because a cheaper process with less stringent clean room requirements is possible for the process of making interconnected metallized structures.
[0033]
Layer 20 is a thick polymer (eg, polyimide) dielectric layer having a thickness (after curing) greater than 2 um. The range of polymer thickness can be from 2um to 150um, depending on the electrical design requirements.
[0034]
For the deposition of the layer 20, it is possible to use, for example, polyimide HD2732 or 2734 made by Hitachi-DuPont. The polyimide can be spin-on coated and can be cured. After spin-on coating, the polyimide is cured at 400 ° C. for 1 hour in a vacuum or nitrogen atmosphere. In order to obtain a thicker polyimide, the polyimide film is coated and cured several times.
[0035]
Another material that can be used to make layer 20 is a polymer of benzocyclobutene (BCB). This polymer is currently manufactured industrially, for example by Dow Chemical Company, and it has recently become clear that it can be used in place of general polyimide applications.
[0036]
There are various opinions regarding the dimensions of the openings 22, 36, and 38. The aspect ratio of the opening is determined by the dimension when the opening and the dielectric thickness are combined. This aspect ratio creates a problem with via etch process and metal filling capability. As a result, the diameter for opening 22/36/38 may range from about 0.5 um. To 30 um., And the height for opening 22/36/38 may range from about 2 um. To 150 um. The aspect ratio of the openings 22/36/38 is designed so that the via can be filled with the metal. Vias can be filled with CVD metal (eg, CVD tungsten or CVD copper), with electroless nickel, or with electroplated copper, using a damascene metal filling method.
[0037]
The application can be further expanded by applying multiple polymer (eg polyimide) layers and can be adapted to a wider variety of applications. The function of the structure shown in FIG. 1 can be further expanded by depositing a second polyimide layer on the pre-deposited layer 20 and overlaying the pads 26 and 28. Additional contacts that can be interconnected to pads 26 and 28 can be made on the surface of the second polyimide layer by selective etching and metal deposition. Additional polyimide layers and contact pads made thereon can be customized for specific applications, and the expanded use of multiple polyimide layers greatly increases the versatility and usefulness of this continuation-in-part application.
[0038]
Figure 1 illustrates the basic design advantages of this continuation-in-part application. These advantages allow a submicron fine line passing in close proximity to the metal layer 14 and the contact 16 to extend upward 30 through the metal interconnect 36, which extension extends to the metal interconnect 28. Continue in direction 32 in the horizontal plane and return downward 34 through the metal interconnect 38. The functions and structures of the passivation layer 18 and the insulating layer 20 are as described above. The basic design advantage of the present invention is that the thin wire interconnects are “elevate” or “fan-out”, and these interconnects are taken from the micro and sub-micro levels. It is to be removed to the level of metal interconnects (which have much larger dimensions and thus have lower resistance and capacitance, are easier to manufacture and are more cost effective). This aspect of the present application does not include any aspect of performing line re-distribution and thus has the inherent property of simplicity. Thus, this aspect further increases the importance of this application in that it allows micro and sub-micro wiring to be accessed at the level of wide and thick metals. Interconnects 20, 36, and 38 rise through the passivation layer and the polymer (e.g. polyimide) dielectric layer, continue to extend over a distance on a wide and thick metal level, and wide and thick metal levels The fine level metal is interconnected by continuing to extend down through the passivation layer and the polymer (eg polyimide) dielectric layer from 1 to the fine metal level. The extension made in this way need not be limited to extending to a specific type of fine metal interconnect point 16 (e.g., signal or power or ground) that includes wide and thick metal lines 26 and 28. . The types of interconnects that can be reliably provided are constrained by the laws of physics and electron optics, and the limiting factors are resistance, propagation delay, RC constant, and other It may be a conventional electrical constraint factor such as a factor. The present application is important in that the continuation-in-part application gives a much wider tolerance in that these laws can be applied, and in doing so, regarding the use and use of the integrated circuit and the circuit The result is a considerably expanded range for adapting to a wide and thick metal environment.
[0039]
FIG. 2 illustrates how the basic interconnect aspect of this continuation application is not only how to raise a fine metal to a wide and thick metal plane according to the present invention, but also on the surface of a thick polyimide layer 20. It shows how it can be expanded to add inductors. The inductor is fabricated in a plane that is parallel to the surface of the substrate 10 and is separated from the surface of the substrate 10 by the combined height of the layers 12, 14, 18, and 20. FIG. 2 shows a cross section 40 of the inductor when cut in a plane perpendicular to the surface of the substrate 10. Wide and thick metals also contribute to energy loss savings due to resistance. In addition, low resistivity metals (eg, gold, silver, and copper) can be applied using electroplating methods.
[0040]
FIG. 3 shows a top view of the inductor 42 fabricated on the surface of the dielectric layer 20. The section 40 of the inductor in FIG. 2 is a view taken along line 2-2 ′ in FIG. The methods used to make the inductor 42 use conventional methods for treating metals (eg, gold, copper, etc.) and electroplating or metal sputtering.
[0041]
FIG. 4 shows a top view of the inductor 44, which is further isolated from the surface of the substrate 10 by adding a layer 44 of ferromagnetic material. Openings are made in the layer of ferromagnetic material 44 for the conductors 34 and 38, and the layer 44 can be measured experimentally and the type of material used and the layer [shown in the cross section of FIG. Is deposited using conventional methods to a thickness that is influenced and to some extent depends on the thickness of the ferromagnetic material (e.g., used to overlay the ferromagnetic material (e.g., layer 20)). It is. The surface area of the ferromagnetic material layer 44 generally extends over the surface of the layer 18 so that the inductor 40 is aligned with the layer 44 and overlays the layer 44, with the surface area of the layer 44 slightly beyond these boundaries. Providing further improvements in that the surface of the substrate 10 is shielded from the electromagnetic field of the inductor 42 (FIG. 3).
[0042]
FIG. 5 shows, for the sake of clarity, a simplified cross section of a substrate and a layer made on the surface of the substrate according to the method of the present invention. The highlighted area is as defined above. That is,
-10 is the silicon substrate,
-12 is a dielectric layer deposited on the surface of the substrate,
-14 is an interconnect layer that includes interconnect lines, bias, and contacts;
-16 are contacts on the surface of the interconnect layer 14,
-18 is a passivation layer in which an opening accessible by the contact 16 is made,
-20 is a thick polymer layer, and
Reference numeral 21 denotes a conductive plug provided through the polyimide layer 20.
[0043]
The thick polymer layer 20 can be applied in liquid form on the surface of the passivation layer 18, or can be laminated by applying a dry film on the surface of the passivation layer 18. The bias required for the production of the conductive plug 21 can be produced by a conventional photolithographic method, or can be produced by using a laser (drill) technique.
[0044]
As is clear from the above description, the arrangement of layers shown in the cross section of FIG. 5 is such that additional electrical elements such as conductors and capacitors are electrically connected to the surface of the polyimide layer 20 and to the conductive plug 21. It is built so that it can be manufactured in a state in contact with. The dielectric layer 12 in the cross section shown in FIG. This is because the layer 14 is an Intra Level Dielectric (ILD) layer on which the layer 12 can be easily integrated.
[0045]
For the cross section shown in FIG. 6, the same layers as described with respect to FIG. 5 are also provided for this cross section. Further shown is an upper layer 17 of the silicon substrate 10 containing active semiconductor elements. In addition, a cross section of an inductor 19 fabricated on the surface of the passivation layer 18 is shown. Again, it is emphasized that the ohmic resistance of the metal used for the inductor 19 must be as low as possible. For this reason, for the formation of the inductor 19, it is preferable to use a thick layer of gold, for example. A thick layer of gold has been shown to increase the Q value of inductor 19 from about 5 to about 20 for 2.4 GHz applications, which means that the Q value of inductor 19 has been significantly improved. Show.
[0046]
FIG. 7 shows a cross section of the capacitor fabricated on the surface of the substrate 10. A layer 14 containing conductive interconnect lines and contacts is fabricated on the surface of the substrate 10, a passivation layer 18 is deposited on the surface of the layer 14, and an opening accessible to the contact pad 16 is formed on the passivation layer 18. It is made inside.
[0047]
As is well known, a capacitor includes a lower plate, an upper plate, and a dielectric layer that separates the upper and lower plates. These components of the capacitor can be easily identified from the cross section shown in FIG. 7 as follows.
-42 is a conductive layer that forms the lower plate of the capacitor,
-44 is a conductive layer that forms the upper plate of the capacitor,
-46 is a dielectric layer that isolates the upper plate of the capacitor from the lower plate.
[0048]
It should be noted that the capacitor is fabricated on the surface of the passivation layer 18, as can be seen from the cross section shown in FIG. 7, so this method of fabricating the capacitor is a post-passivation processing sequence and be called. The processing conditions and materials that can be used to make the individual layers 42, 44 and 46 have already been described and therefore need not be described in further detail here.
[0049]
The important points are the various thicknesses to which the three layers 42, 44 and 46 can be deposited, as follows.
-The thickness of the passivation layer 18 is about 0.1-0.3um,
-The thickness of the conductive material layer 42 is about 0.5-20um,
-The thickness of the dielectric layer 44 is about 500-10,000 angstroms, and
-The thickness of the conductive material layer 46 is about 0.5-20um.
[0050]
The capacitor produced by the post-passivation method shown in the cross section in FIG.
-Reduce the parasitic capacitance between the capacitor and the lower silicon substrate,
-Allows the use of a thick layer of conductive material (this reduces the resistance of the capacitor; this is particularly important in wireless applications) and
-High dielectric material (e.g. TiO) against the dielectric between the upper and lower plates of the capacitor ₂ And Ta ₂ O _Five (As a result, the capacitance value of the capacitor is higher).
[0051]
FIG. 8 shows a three-dimensional view of the inductor 19 fabricated on the surface of the passivation layer 18. The emphasis in Figure 8 is
-23, the bias being made in the thick polymer layer of Fig. 5 for the upper and lower level interconnects of the inductor metal,
-25, ie the bottom metal of the inductor, and
-27, ie upper metal for inductor
It is.
[0052]
FIG. 9 is made on the surface of the pavation layer by first depositing a thick layer of polyimide, then depositing a polymer layer thereon, and creating a bias 23 in the thick layer of polymer 20 (FIG. 5). 3D shows a three-dimensional view of the inductor. FIG. 9 shows a polyimide layer 29 in addition to the layers highlighted above. The inductor 19 is made by building up a bias 23 made in the bottom metal 25 of the inductor 19, the top metal 27 of the inductor, and a layer 20 (preferably containing polyimide) 20 (FIG. 5). The
[0053]
FIG. 10 shows a cross section when a capacitor is formed on the surface of the substrate 10 as shown in FIG. However, in the cross-section shown in FIG. 10, a thick polyimide layer 20 is deposited on the surface of the passivation layer 18, and a pattern baking process and etching is performed to create a contact pad 16 accessible through the thick polyimide layer 20. Processing has been applied. The thick polymer layer 20 displaces most of the capacitor. That is, the lower plate 42, the upper plate 44, and the dielectric 46 are pushed away from the surface of the substrate 10 by a distance equal to the thickness of the layer 20. As mentioned above, the polyimide thickness range may vary from 2um. To 150um., Depending on the electrical design requirements. This description applies to the cross section shown in FIG. 10 as well, so that the main layer of the capacitor can be pushed away from the surface of the substrate 10 over a distance of 2 μm to 150 μm. As a result, the distance between the capacitor and the underlying silicon substrate will be greatly increased, and thus obviously the parasitic capacitance will be greatly reduced.
[0054]
FIG. 11 shows a cross-section of the substrate 10 when the passivation layer 18 is attached on the surface of the substrate 10 and a resistor is formed on the surface of the passivation layer. As is well known, a resistor is made by connecting two points with a substance that creates an electrical resistance to the passage of current. Two portions which are part of the resistance shown in cross section in FIG. 11 are contact pads 16 formed on the surface of the interconnect layer 14. Resistors were made according to the method of the present invention by interconnecting the two contact pads and creating a layer 48 between the two contact pads that is disposed on the surface of the passivation layer 18. To produce layer 48, a high resistivity material (e.g., TaN, silicon nitride, phosphosilicate glass (PSG), silicon oxynitride, aluminum, aluminum oxide (Al _x O _y ), Tantalum, niobium, or molybdenum]. The dimensions (eg, thickness, length, and width) of the layer 48 of high resistivity material vary depending on the application and are therefore not specified here. The resistor shown in the cross section in FIG. 11 is fabricated on the surface of the passivation layer 18 by the post-passivation method, as in the case of the capacitors in FIGS.
[0055]
FIG. 12 shows a cross section of the substrate 10, with an interconnect layer 14 formed on the surface of the substrate. A passivation layer 18 is deposited on the interconnect metal layer 14 and a thick polyimide layer 20 is deposited on the surface of the passivation layer 18. Resistor 48 is fabricated on the surface of polyimide layer 20. Resistor 48 is fabricated with two contact pads 16 connected to a thin metal layer having a high resistivity. By increasing the distance between the resistor body and the substrate surface (by increasing the thickness of the polyimide layer 20), the parasitic capacitance between the resistor body and the substrate is reduced, and thus improved resistance Components can be obtained (reduction of parasitic capacitance loss, improvement of high frequency performance).
[0056]
A further application of the post-passivation method of the present invention is illustrated in FIGS. 13 and 14, with an emphasis on creating a ball contact between the contact pad 16 and an overlying electrical element (e.g., a discrete inductor). I put it. Most of the layers of FIG. 13 from the surface of the substrate 10 upwards are identified using the same reference numbers used above for the three layers. What has not yet been identified in FIG.
-50, contact plugs, formed through a thick polymer layer 20
-52, the conventional method of selective solder deposition (electroplating or ball mounting on the surface of the plug 50, flux on the deposited solder, and flowing the solder to form the contact ball 52) Contact balls that are formed on the surface of the contact plug 50 using, and
-54, cross-section of discrete electrical elements (eg inductors, discrete capacitors or resistors)
It is.
[0057]
FIG. 14 shows a cross-section of the silicon substrate 10, with a discrete electrical element 54 mounted on the substrate surface, and contact balls 56 are used, thereby providing a gap between the substrate 10 and the electrical element 54. The distance is a considerable value. A contact ball is inserted into the opening made in the passivation layer 18 and this (relatively large) contact ball 56 provides a considerable degree of isolation between the surface of the substrate 10 and the discrete electrical element 54. Bring.
[0058]
The method shown in FIGS. 13 and 14 is
The passive element 54 has been removed at a considerable distance from the surface of the substrate 10, and
-Instead of mounting discrete passive elements 54 on the surface of a printed circuit board (PCB), in the present invention, passive elements 54 closer to semiconductor elements can be mounted.
It shows that.
[0059]
The following points have been emphasized throughout the methods and procedures that have been described with reference to the embodiments shown in cross-section in the accompanying drawings:
-Further removing passive components from the silicon substrate, thereby reducing the negative effects caused by the substrate due to the electromagnetic losses it receives,
-The post-passivation method of the present invention allows the selection of discrete element design parameters, which results in a decrease in the resistance of the discrete capacitor and the discrete inductor. This becomes even clearer from the following comparison between the prior art method and the method of the present invention.
[0060]
The prior art requires the fabrication of the inductor and the use of thin metal, which requires the inductor to have a wider coil, which increases the surface area required for the inductor, and thus the parasitic nature of the inductor. The capacitance increases, which causes eddy current loss at the substrate surface.
[0061]
In contrast, the present invention allows the use of thick metal since the passive component metal is removed from the (thin metal) interconnect layer 14 (by the thick polymer layer), and thus the surface required for the inductor. Less area is required, and the resistivity of the inductor is reduced, which increases the Q value of the inductor.
[0062]
While preferred embodiments of the invention have been described and described in detail, various modifications may be made by those skilled in the art without departing from the spirit of the invention and without departing from the scope of the claims. It goes without saying that it is possible.
Embodiments of the present invention are as follows.
[0063]
1. A method of forming an inductor for a high-performance integrated circuit that overlays a surface of a semiconductor substrate,
(a) supplying a semiconductor substrate having an electrical contact provided on the semiconductor element in or on the active surface of the semiconductor substrate into or on the surface where the semiconductor element is fabricated;
(b) producing an overlying interconnect metallization structure comprising one or more layers of interconnects on the active surface of the semiconductor substrate, wherein the layers of interconnects are electrically contacted; Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the overlying interconnect metallization structure, at least one of the electrical contacts One of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the overlaying interconnect metallization structure, the metal line or the contacts or the At least one of the conductive biases contacts at least one of the electrical contacts provided in the semiconductor element in or on the surface of the substrate;
c) depositing a passivation layer on the overlying interconnect metallization structure;
d) an insulating / separating polymer layer on the passivation layer that is substantially thicker than the passivation layer and substantially thicker than the dielectric intermediate layer used to fabricate the interconnect metallization structure; Adhering to;
e) the electricity provided in or on the surface of the overlying interconnected metallization structure through the insulation / separation polymer layer and through the passivation layer to form openings. Exposing at least a pair of contacts;
f) filling the opening with a conductive material to create a metal contact through the opening; and
g) forming the inductor on the surface of the insulating / separating polymer layer, wherein the inductor is provided in or on the surface of the overlying interconnected metallization structure; Connected to at least a pair of;
Including said method.
[0064]
2. The method of claim 1, wherein the size of the electrical contacts provided in or on the surface of the overlaying interconnected metallized structure ranges from about 0.3 um. To about 50 um.
[0065]
3 The electrical contact provided in or on the surface of the metallization structure for interconnection to be overlaid is sputtered aluminum, CVD tungsten, CVD copper, electroplated gold, electroplated silver, electroplated copper, electroless 2. The method according to 1 above, comprising a material selected from the group comprising gold and electroless nickel.
[0066]
4. The method of claim 1, wherein the inductor is embedded in a dielectric and further covered by a passivation layer.
5. The method according to 4 above, wherein the dielectric is a low-K dielectric.
[0067]
One or more layers of ferromagnetic material overlaying the passivation layer, the thickness being greater than about 2,000-50,000 angstroms and the surface area being greater than the surface area over which the inductor substantially overlays the insulating polymer layer The method according to claim 1, wherein one or more layers of the ferromagnetic material are inserted between the surface of the passivation layer and the insulating / separating polymer layer deposited thereon by adding
[0068]
7. The method according to 1 above, wherein the inductor is a spiral design and is produced on the surface of the insulating / separating polymer layer and in a plane parallel to the surface of the insulating / separating polymer layer.
[0069]
8. The method according to 1 above, wherein the inductor is produced using a damascene patterning method.
9. The method according to 1 above, wherein the inductor is produced using a photographic printing method and a photolithography method.
[0070]
10. A method for forming a capacitor for a high-performance integrated circuit on a surface of a semiconductor substrate, comprising a top plate, a bottom plate, and a dielectric layer inserted between the top plate and the bottom plate,
(a) supplying a semiconductor substrate having an electrical contact provided on the semiconductor element in or on the active surface of the semiconductor substrate into or on the surface where the semiconductor element is fabricated;
(b) producing an overlying interconnect metallization structure comprising one or more layers of interconnects on the active surface of the semiconductor substrate, wherein the layers of interconnects are electrically contacted; Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the overlaying interconnect metallization structure, at least of the electrical contacts One in contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the overlaid interconnect metallization structure, the metal lines or the contacts or At least one of the conductive biases contacts at least one of the electrical contacts provided on the semiconductor element in or on the surface of the substrate; The electrical contacts provided on the surface of the overlaying interconnected metallization structure are divided into even and odd pairs of adjacent contact locations so that one electrical contact can belong to only one pair. ;
(c) depositing a passivation layer on the overlying interconnect metallization structure;
(d) performing a pattern baking process and an etching process on the passivation layer to form an opening in the passivation layer, wherein at least one opening is in or on the surface of the interconnected metallized structure for overlaying Overlaying at least one flat contact of the electrical contact provided thereon;
(e) attaching a first layer of a conductive material on the surface of the passivation layer including the opening made in the passivation layer;
(f) applying a pattern baking process and an etching process to the first conductive material layer, and at least one of the even-numbered electrical contacts provided in or on the surface of the interconnected metallization structure to be overlaid Making an opening in one and making the bottom plate of the capacitor;
(g) depositing a dielectric layer on the surface of the first conductive material layer including the opening for at least one of the even electrical contacts;
(h) performing a pattern baking process and an etching process on the dielectric layer, creating an opening in the dielectric layer for at least one of the even-numbered electrical contacts, and providing at least one of the even-numbered electrical contacts Making the dielectric layer partially exposed and inserted between the top and bottom plates;
(i) depositing a second conductive material layer on a surface of the dielectric layer including at least one opening made in the dielectric layer; and
(j) performing a pattern baking process and an etching process on the second conductive material layer to produce the upper plate of the capacitor;
Including said method.
[0071]
11 As an additional processing step performed after the step of pattern baking and etching the passivation layer,
Attaching an insulating / separating polymer layer on the surface of the passivation layer that has been subjected to the pattern baking / etching treatment including the opening formed in the passivation layer; and
Patterning and etching the insulating / separating polymer layer to form at least one opening aligned with at least one of the even-numbered electrical contacts on the surface of the overlaid interconnect metallization structure; A process for producing a polymer layer for insulation and separation;
The method according to 10 above, comprising:
[0072]
12. The method according to 11 above, wherein the thickness of the insulating / separating polymer layer after curing is in the range of about 1.0 to 150 um.
13. The method of claim 11, wherein the insulating / separating polymer layer is spin-on coated and cured.
[0073]
14. A method of forming a resistor for a high performance integrated circuit on a surface of a semiconductor substrate, comprising:
(a) supplying a semiconductor substrate having an electrical contact provided on the semiconductor element in or on the active surface of the semiconductor substrate into or on the surface where the semiconductor element is fabricated;
(b) producing an overlying interconnect metallization structure comprising one or more layers of interconnects on the active surface of the semiconductor substrate, wherein the layers of interconnects are electrically contacted; Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the overlaying interconnect metallization structure, at least of the electrical contacts One in contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the overlaid interconnect metallization structure, the metal lines or the contacts or At least one of the conductive biases contacts at least one of the electrical contacts provided on the semiconductor element in or on the surface of the substrate. ;
(c) depositing a passivation layer on the overlying interconnect metallization structure;
(d) performing a pattern baking process and an etching process on the passivation layer to form an opening in the passivation layer, wherein at least two of the openings are in the surface of the overlying interconnect metallization structure. Overlay at least a pair of provided electrical contacts;
(e) depositing a conductive material layer on a surface of the passivation layer including the opening made in the passivation layer; and
(f) subjecting the conductive material layer to pattern baking and etching to produce a conductive material layer interconnected with at least a pair of the openings made in the passivation layer, and producing the resistor; Process;
Including said method.
[0074]
15. A method of forming a resistor for a high performance integrated circuit on a surface of a semiconductor substrate, comprising:
(a) supplying a semiconductor substrate having an electrical contact provided on the semiconductor element in or on the active surface of the semiconductor substrate into or on the surface where the semiconductor element is fabricated;
(b) producing an overlying interconnect metallization structure comprising one or more layers of interconnects on the active surface of the semiconductor substrate, wherein the layers of interconnects are electrically contacted; Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the overlaying interconnect metallization structure, at least of the electrical contacts One in contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the overlaid interconnect metallization structure, the metal lines or the contacts or At least one of the conductive biases contacts at least one of the electrical contacts provided on the semiconductor element in or on the surface of the substrate. ;
(c) depositing a passivation layer on the overlying interconnect metallization structure;
(d) performing a pattern baking process and an etching process on the passivation layer to form an opening in the passivation layer, wherein at least two of the openings are in the surface of the overlying interconnect metallization structure. Overlay and partially expose at least a pair of electrical contacts provided;
(e) a step of attaching an insulating / separating polymer layer on the surface of the passivation layer that has been subjected to the pattern baking / etching treatment including the opening formed in the passivation layer;
(f) A pattern baking process and an etching process are performed on the insulating / separating polymer layer to form at least a pair of openings in the insulating / separating polymer layer aligned with at least the pair of openings formed in the passivation layer. And partially exposing at least a pair of electrical contacts provided in the surface of the overlaying interconnect metallization structure;
(g) attaching a conductive material layer on the surface of the insulating / separating polymer layer including the opening formed in the insulating / separating polymer layer; and
(h) subjecting the conductive material layer to pattern baking and etching to produce a conductive material layer interconnected with at least one of the openings formed in the passivation layer, and producing the resistor; Process;
Including said method.
[0075]
16 The passivation layer includes a plasma enhanced CVD (PECVD) oxide layer having a thickness in the range of about 0.15 to 2.0 um., And a PECVD nitridation having a thickness in the range of about 0.5 to 2.0 um. On the oxide layer. 16. The method according to 15 above, wherein a physical layer is attached.
[0076]
17. The method according to 15, wherein the insulating / separating polymer layer comprises a polymer of polyimide or benzocyclobutene (BCB).
18. The method according to 15 above, wherein the thickness of the insulating / separating polymer layer after curing is in the range of about 1.0 to 150 um.
[0077]
19. The method of claim 15, wherein the insulating and separating polymer layer is spin-on coated and cured.
20. The method according to 19, wherein the insulating / separating polymer layer is subjected to a plurality of spin-on coating and curing processes.
[0078]
21. A method of mounting discrete electrical components on a surface of a semiconductor substrate,
(a) supplying a semiconductor substrate having an electrical contact provided on the semiconductor element in or on the active surface of the semiconductor substrate into or on the surface where the semiconductor element is fabricated;
(b) producing an overlying interconnect metallization structure comprising one or more layers of interconnects on the active surface of the semiconductor substrate, wherein the layers of interconnects are electrically contacted; Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the overlaying interconnect metallization structure, at least of the electrical contacts One in contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the overlaid interconnect metallization structure, the metal lines or the contacts or At least one of the conductive biases contacts at least one of the electrical contacts provided on the semiconductor element in or on the surface of the substrate. ;
(c) depositing a passivation layer on the overlying interconnect metallization structure;
(d) performing a pattern baking process and an etching process on the passivation layer to form an opening in the passivation layer, wherein at least two of the openings are in the surface of the overlying interconnect metallization structure. Overlaying at least one pair of provided electrical contacts and providing at least one pair of electrical contacts to the passivation layer;
(e) a step of attaching an insulating / separating polymer layer on the surface of the passivation layer that has been subjected to the pattern baking / etching treatment including the opening formed in the passivation layer;
(f) A pattern baking process and an etching process are performed on the insulating / separating polymer layer to form at least a pair of openings in the insulating / separating polymer layer aligned with at least a pair of electrical contacts provided in the passivation layer. Process;
(g) A conductive material layer is selectively attached on the surface of at least one pair of electrical contacts provided to the passivation layer, and the opening formed in the insulating / separating polymer layer is filled, and the insulating / separating method is performed. Creating a conductive plug through the protective polymer layer, wherein the conductive plug overlays at least a pair of electrical contacts provided to the passivation layer;
(h) a step of selectively producing a solder layer on the surface of the conductive plug;
(i) placing the discrete electrical component over the selectively fabricated solder layer and the selective electrical component so that the discrete electrical component is aligned with the selectively fabricated solder layer; Placing in alignment with the solder layer produced on; and
(j) Flowing the selectively produced solder layer and producing solder balls for connecting the discrete electrical component and the conductive plug in the insulating / separating polymer layer, thereby the discrete electrical component And a pair of electrical contacts in the passivation layer;
Including said method.
[0079]
22. The method of claim 21, wherein the insulating / separating polymer layer comprises a polymer of polyimide or benzocyclobutene (BCB).
23. The method according to 21 above, wherein the thickness of the insulating / separating polymer layer after curing is in the range of about 1.0 to 150 um.
[0080]
24. The method of claim 21, wherein the insulating / separating polymer layer is subjected to a plurality of spin-on coating and curing processes.
25. The method of claim 21, wherein the discrete electrical component is selected from the group comprising a resistor, a capacitor, and an inductor.
[0081]
26 A method of mounting discrete electrical components on the surface of a semiconductor substrate,
(a) supplying a semiconductor substrate having an electrical contact provided on the semiconductor element in or on the active surface of the semiconductor substrate into or on the surface where the semiconductor element is fabricated;
(b) producing an overlying interconnect metallization structure comprising one or more layers of interconnects on the active surface of the semiconductor substrate, wherein the layers of interconnects are electrically contacted; Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the overlaying interconnect metallization structure, at least of the electrical contacts One in contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the overlaid interconnect metallization structure, the metal lines or the contacts or At least one of the conductive biases contacts at least one of the electrical contacts provided on the semiconductor element in or on the surface of the substrate. ;
(c) depositing a passivation layer on the overlying interconnect metallization structure;
(d) performing a pattern baking process and an etching process on the passivation layer to form an opening in the passivation layer, wherein at least two of the openings are in the surface of the overlying interconnect metallization structure. Overlaying at least one pair of provided electrical contacts and providing at least one pair of electrical contacts to the passivation layer;
(e) a step of selectively producing a solder layer on the surface of at least a pair of electrical contacts in the passivation layer;
(f) placing the discrete electrical component on the selectively fabricated solder layer and in order that electrical contacts of the discrete electrical component are aligned with the selectively fabricated solder layer; Placing in alignment with the selectively produced solder layer; and
(g) flowing the selectively produced solder layer, and producing a solder ball that connects the discrete electrical component and at least a pair of electrical contacts in the passivation layer;
Including said method.
[0082]
27. The method of claim 26, wherein the discrete electrical component is selected from the group comprising resistors, capacitors, and inductors.
28 (a) a semiconductor substrate in or on the surface on which the semiconductor element is fabricated, having electrical contacts provided on the semiconductor element in or on the active surface of the semiconductor substrate;
(b) an overlying interconnect metallization structure comprising one or more layers of interconnects on the active surface of the substrate, wherein the interconnect layers are interconnected with electrical contacts on the overlay Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the connecting metallization structure, wherein at least one of the electrical contacts is the overlay In contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the interconnecting metallization structure, and at least of the metal lines or the contacts or the conductive bias One contacts at least one of the electrical contacts provided in the semiconductor element in or on the surface of the substrate;
(c) a passivation layer deposited on the overlying interconnect metallization structure;
(d) insulation / separation deposited on the passivation layer that is substantially thicker than the passivation layer and substantially thicker than the dielectric intermediate layer used to fabricate the interconnect metallization structure; Polymer layer for; and
(e) through the insulating / separating polymer layer and through the passivation layer to expose at least one pair of the electrical contacts provided in or on the surface of the overlying interconnecting metallization structure. An opening to be formed, wherein the opening is filled with a conductive material to create a metal contact through the opening;
Is formed on the surface of the insulating / separating polymer layer, and is connected to at least a pair of the electrical contacts provided in or on the surface of the overlying interconnecting metallization structure, Inductors for high-performance integrated circuits that overlay the surface of a semiconductor substrate.
[0083]
29. The inductor of claim 28, wherein the size of the electrical contact provided in or on the surface of the overlying interconnecting metallization structure ranges from about 0.3 um. To about 50 um.
[0084]
30. The passivation layer includes a plasma enhanced CVD (PECVD) oxide layer having a thickness in the range of about 0.15-2.0 um., And a PECVD nitridation having a thickness in the range of about 0.5-2.0 um. Over the oxide layer. 29. The inductor according to 28 above, wherein a material layer is attached.
[0085]
31. The inductor according to 28, wherein the insulating / separating polymer layer comprises a polymer of polyimide or benzocyclobutene (BCB).
32. The inductor according to 28, wherein the thickness of the insulating / separating polymer layer after curing is in the range of about 1.0 to 150 um.
[0086]
33. The inductor of claim 28, wherein the insulating / separating polymer layer is spin-on coated and cured.
34. The inductor according to 28, wherein the insulating / separating polymer layer is subjected to a plurality of processes of spin-on coating and curing.
[0087]
35 The electrical contacts provided in or on the surface of the overlying interconnected metallization structure are sputtered aluminum, CVD tungsten, CVD copper, electroplated gold, electroplated copper, electroplated silver, electroless 28. The inductor according to 28, comprising a material selected from the group including gold and electroless nickel.
[0088]
36. The inductor of claim 28, wherein the inductor is embedded in a dielectric and further covered by a passivation layer.
37 The above dielectric material, wherein the dielectric material is a low-K dielectric material.
Inductor described.
[0089]
One or more ferromagnetic materials overlying the passivation layer, wherein the thickness is greater than about 2-50 kilo angstroms and the surface area is greater than the surface area over which the inductor substantially overlays the insulating polymer layer. 29. The inductor of claim 28, wherein one or more layers of the ferromagnetic material are inserted between the surface of the passivation layer and the insulating / separating polymer layer deposited thereon by adding a layer. .
[0090]
39. The inductor according to 28, wherein the inductor is a spiral design and is produced on a surface of the insulating / separating polymer layer and in a plane parallel to the surface of the insulating / separating polymer layer.
[0091]
40. The inductor according to 28, wherein the inductor is manufactured using a damascene patterning method.
41. The inductor as described in 28 above, wherein the inductor is produced by using a photo printing method and a photo etching method.
[0092]
42. A capacitor for a high performance integrated circuit on a surface of a semiconductor substrate, comprising a top plate, a bottom plate, and a dielectric layer inserted between the top plate and the bottom plate,
(a) a semiconductor substrate in or on the surface where the semiconductor element is fabricated, having electrical contacts provided on the semiconductor element in or on the active surface of the semiconductor substrate;
(b) an overlying interconnect metallization structure including one or more layers of interconnects on the active surface of the substrate, wherein the interconnect layers are interconnected with electrical contacts overlaid with the overlay. Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the connecting metallization structure, wherein at least one of the electrical contacts is the overlay In contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the interconnecting metallization structure, and at least of the metal lines or the contacts or the conductive bias One contacts and overlays at least one of the electrical contacts provided on the semiconductor element in or on the surface of the substrate The electrical contacts provided on the surface of the interconnecting metallization structure are divided into even and odd pairs of adjacent contact points, whereby one electrical contact can belong to only one pair;
(c) a passivation layer deposited on the overlying interconnect metallization structure;
(d) at least one flat surface of the electrical contact provided in or on the surface of the overlying interconnect metallization structure, wherein an opening made in the passivation layer, wherein at least one opening is provided. Overlay contacts;
(e) a first layer of a conductive material deposited on the surface of the passivation layer including the openings made in the passivation layer;
(f) an opening made in the first conductive material layer for at least one of the even-numbered electrical contacts provided in or on the surface of the overlying interconnecting metallization structure, Sometimes the first conductive material layer forms the bottom plate of the capacitor;
(g) a dielectric layer deposited on the surface of the first conductive material layer including the opening for at least one of the even electrical contacts;
(h) an opening in the dielectric layer with respect to at least one of the even-numbered electrical contacts, wherein the opening partially exposes at least one of the even-numbered electrical contacts, and the upper plate and the Constituting the dielectric layer inserted between the bottom plate; and
(i) a second conductive material layer deposited on the surface of the dielectric layer including at least one opening made in the dielectric layer;
And the upper plate of the capacitor is produced by subjecting the second conductive material layer to pattern baking and etching.
[0093]
43 On the passivation layer subjected to the pattern baking / etching treatment,
An insulating / separating polymer layer deposited on the surface of the passivation layer that has been subjected to the pattern baking / etching treatment including the opening formed in the passivation layer; and
At least one opening made in the insulating and separating polymer layer aligned with at least one of the even number of electrical contacts on the surface of the overlaying interconnect metallization structure;
43. The capacitor according to 42 above, further comprising:
[0094]
44. The passivation layer includes a plasma enhanced CVD (PECVD) oxide layer having a thickness in the range of about 0.15 to 2.0 um., And a PECVD nitridation having a thickness in the range of about 0.5 to 2.0 um. Over the oxide layer. 43. The capacitor according to 42 above, wherein a physical layer is attached.
[0095]
45. The capacitor according to 43, wherein the insulating / separating polymer layer includes a polymer of polyimide or benzocyclobutene (BCB).
46. The capacitor as described in 43 above, wherein the thickness of the insulating / separating polymer layer after curing is in the range of about 1.0 to 150 μm.
[0096]
47. The insulating and separating polymer layer is spin-on coated and cured, 43 The method described.
48 (a) a semiconductor substrate in or on the surface on which the semiconductor element is fabricated, having electrical contacts provided on the semiconductor element in or on the active surface of the semiconductor substrate;
(b) an overlying interconnect metallization structure including one or more layers of interconnects on the active surface of the substrate, wherein the interconnect layers are interconnected with electrical contacts overlaid with the overlay. Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the connecting metallization structure, wherein at least one of the electrical contacts is the overlay In contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the interconnecting metallization structure, and at least of the metal lines or the contacts or the conductive bias One contacts at least one of the electrical contacts provided in the semiconductor element in or on the surface of the substrate;
(c) a passivation layer deposited on the overlying interconnect metallization structure;
(d) openings made in the passivation layer, wherein at least two of the openings overlay at least a pair of the electrical contacts provided in the surface of the overlaid interconnect metallization structure;
(e) a layer of conductive material deposited on the surface of the passivation layer including the openings made in the passivation layer; and
(f) a layer of conductive material that interconnects at least a pair of the openings made in the passivation layer, thereby creating a resistor;
A resistor for high performance integrated circuits on the surface of a semiconductor substrate.
[0097]
49. The passivation layer includes a plasma enhanced CVD (PECVD) oxide layer having a thickness in the range of about 0.15 to 2.0 um., And a PECVD nitridation having a thickness in the range of about 0.5 to 2.0 um. Over the oxide layer. 49. The resistor of claim 48, wherein a physical layer is attached.
[0098]
50 (a) a semiconductor substrate in or on the surface on which the semiconductor element is fabricated, having electrical contacts provided on the semiconductor element in or on the active surface of the semiconductor substrate;
(b) an overlying interconnect metallization structure including one or more layers of interconnects on the active surface of the substrate, wherein the interconnect layers are interconnected with electrical contacts overlaid with the overlay. Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the connecting metallization structure, wherein at least one of the electrical contacts is the overlay In contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the interconnecting metallization structure, and at least of the metal lines or the contacts or the conductive bias One contacts at least one of the electrical contacts provided in the semiconductor element in or on the surface of the substrate;
(c) a passivation layer deposited on the overlying interconnect metallization structure;
(d) openings formed in the passivation layer, wherein at least two of the openings overlay at least a pair of electrical contacts provided in the surface of the overlying interconnected metallization structure, and a portion Exposed to light;
(e) an insulating / separating polymer layer deposited on the surface of the passivation layer that has been subjected to the pattern baking / etching treatment including the opening formed in the passivation layer;
(f) the insulation being aligned with at least one pair of openings made in the passivation layer and partially exposing at least one pair of electrical contacts provided in a surface of the overlying interconnect metallization structure; At least a pair of openings in the separating polymer layer;
(g) a layer of conductive material deposited on the surface of the insulating / separating polymer layer including the opening made in the insulating / separating polymer layer; and
(h) a layer of conductive material that interconnects at least a pair of the openings made in the passivation layer, thereby creating a resistor;
A resistor for high performance integrated circuits on the surface of a semiconductor substrate.
[0099]
51. The passivation layer includes a plasma enhanced CVD (PECVD) oxide layer with a thickness in the range of about 0.15 to 2.0 um., And a PECVD nitridation with a thickness in the range of about 0.5 to 2.0 um. On the oxide layer. The resistor according to 50, wherein a physical layer is attached.
[0100]
52. The resistor according to 50, wherein the insulating / separating polymer layer includes a polymer of polyimide or benzocyclobutene (BCB).
53. The resistor according to 50, wherein the thickness of the insulating / separating polymer layer after curing is in the range of about 1.0 to 150 um.
[0101]
54. The resistor of claim 50, wherein the insulating and separating polymer layer is spin-on coated and cured.
55. The resistor according to 50, wherein the insulating / separating polymer layer is subjected to a plurality of processing steps of spin-on coating and curing.
[0102]
56 Discrete electrical components on the surface of the semiconductor substrate,
(a) a semiconductor substrate in or on the surface where the semiconductor element is fabricated, having electrical contacts provided on the semiconductor element in or on the active surface of the semiconductor substrate;
(b) an overlying interconnect metallization structure including one or more layers of interconnects on the active surface of the substrate, wherein the interconnect layers are interconnected with electrical contacts overlaid with the overlay. Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the connecting metallization structure, wherein at least one of the electrical contacts is the overlay In contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the interconnecting metallization structure, and at least of the metal lines or the contacts or the conductive bias One contacts at least one of the electrical contacts provided in the semiconductor element in or on the surface of the substrate;
(c) a passivation layer deposited on the overlying interconnect metallization structure;
(d) Openings made in the passivation layer, wherein at least two of the openings overlay at least a pair of electrical contacts provided in the surface of the overlying interconnected metallization structure, and at least a pair Providing electrical contact to the passivation layer;
(e) an insulating / separating polymer layer deposited on the surface of the passivation layer that has been subjected to the pattern baking / etching treatment including the opening formed in the passivation layer;
(f) at least a pair of openings formed in the insulating / separating polymer layer, aligned with at least a pair of electrical contacts provided in the passivation layer;
(g) a layer of conductive material selectively deposited on at least a pair of surfaces of the electrical contacts provided to the passivation layer, wherein the openings made in the insulating / separating polymer layer are filled; A conductive plug is made through the insulating / separating polymer layer, and the conductive plug overlays at least a pair of electrical contacts provided to the passivation layer; and
(h) a solder layer selectively produced on the surface of the conductive plug;
Wherein the discrete electrical component is over the selectively fabricated solder layer and the selection such that electrical contacts of the discrete electrical component are aligned with the selectively fabricated solder layer. Solder that is arranged in an aligned manner with the solder layer that has been manufactured in order to connect the conductive plug in the insulating / separating polymer layer and the discrete electrical component in which the selectively manufactured solder layer is flowed The discrete electrical component in which a ball is produced, thereby connecting a pair of electrical contacts in the passivation layer and the discrete electrical component.
[0103]
57. The passivation layer includes a plasma enhanced CVD (PECVD) oxide layer having a thickness in the range of about 0.15 to 2.0 um., And a PECVD nitridation having a thickness in the range of about 0.5 to 2.0 um. Over the oxide layer. 57. The discrete electrical component according to 56 above, wherein a physical layer is attached.
[0104]
58. The discrete electrical component of 56, wherein the insulating / separating polymer layer includes a polymer of polyimide or benzocyclobutene (BCB).
59. The discrete electrical component according to 56, wherein the thickness of the insulating / separating polymer layer after curing is in the range of about 1.0 to 150 um.
[0105]
60. The discrete electrical component of claim 56, wherein the insulating / separating polymer layer is spin-on coated and cured.
61. The discrete electrical component according to 56, wherein the insulating / separating polymer layer is subjected to a plurality of spin-on coating and curing processes.
[0106]
62. The discrete electrical component of item 56, wherein the discrete electrical component is selected from the group comprising a resistor, a capacitor, and an inductor.
63 Discrete electrical components mounted on the surface of a semiconductor substrate,
(a) a semiconductor substrate in or on the surface where the semiconductor element is fabricated, having electrical contacts provided on the semiconductor element in or on the active surface of the semiconductor substrate;
(b) an overlying interconnect metallization structure including one or more layers of interconnects on the active surface of the substrate, wherein the interconnect layers are interconnected with electrical contacts overlaid with the overlay. Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the connecting metallization structure, wherein at least one of the electrical contacts is the overlay In contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the interconnecting metallization structure, and at least of the metal lines or the contacts or the conductive bias One contacts at least one of the electrical contacts provided in the semiconductor element in or on the surface of the substrate;
(c) a passivation layer deposited on the overlying interconnect metallization structure;
(d) Openings made in the passivation layer, wherein at least two of the openings overlay at least a pair of electrical contacts provided in the surface of the overlying interconnected metallization structure, and at least a pair Providing electrical contact to the passivation layer; and
(e) a solder layer selectively deposited on the surface of at least one pair of electrical contacts in the passivation layer;
Wherein the discrete electrical component is over the selectively deposited solder layer and the selection so that electrical contacts of the discrete electrical component are aligned with the selectively deposited solder layer. Disposed in alignment with the selectively applied solder layer, the selectively applied solder layer is flowed, and at least a pair of electrical contacts in the passivation layer and the discrete electrical component are connected, Discrete electrical equipment.
[0107]
64. The passivation layer includes a plasma enhanced CVD (PECVD) oxide layer having a thickness in the range of about 0.15 to 2.0 um., And a PECVD nitridation having a thickness in the range of about 0.5 to 2.0 um. Over the oxide layer. 64. The discrete electrical component of item 63, wherein a physical layer is attached.
[0108]
65. The discrete electrical component of item 63, wherein the discrete electrical component is selected from the group comprising a resistor, a capacitor, and an inductor.
66. The method of claim 1, wherein the inductor is made to overlay the surface of the passivation layer so that no polyimide layer is applied.
[0109]
67. The method of claim 1, wherein the inductor is a helical structure that overlays a polymer layer, the polymer layer overlaying a passivation layer.
[0110]
68. The method of claim 1, wherein the inductor is a spiral structure overlying a passivation layer so that no polyimide layer is applied.
69. The method according to 11 above, wherein the insulating / separating polymer layer is a dry laminate film.
[0111]
70. The method according to 15, wherein the insulating / separating polymer layer is a dry laminate film.
71. The method of claim 21, wherein the solder balls are made by electroplating, screen printing, and ball mounting.
[0112]
72. The method according to 21 above, wherein the insulating / separating polymer layer is a dry laminate film.
73. The method according to 28, wherein the insulating / separating polymer layer is a dry laminate film.
[0113]
74 The inductor is a spiral design and is made on the surface of the insulating / separating polymer layer and in a plane parallel to the surface of the insulating / isolating polymer layer, whereby the polymer layer is passivated. 29. The inductor of claim 28, which is deposited on the surface of the layer.
[0114]
75 The inductor is a spiral design and is fabricated on the surface of the insulating / separating polymer layer and in a plane parallel to the surface of the insulating / separating polymer layer, whereby the polymer layer is made of polyimide. 29. The inductor of claim 28, wherein the inductor is deposited on a surface of the layer, whereby the polyimide layer is deposited on the surface of the passivation layer.
[0115]
76. The capacitor according to 43, wherein the insulating / separating polymer layer is a dry laminate film.
77. The resistor according to 50, wherein the insulating / separating polymer layer is a dry laminate film.
[0116]
78 The discrete electrical component described in 56 above, wherein the insulating / separating polymer layer is a dry laminate film.
[Brief description of the drawings]
FIG. 1 shows a cross-section of an inventive interconnection scheme according to this continuation-in-part application.
FIG. 2 shows a cross-section when this partial continuation application is expanded that an inductor is fabricated on the surface of a thick polyimide layer.
FIG. 3 shows a top view of an inductor made according to the method of the present invention.
FIG. 4 shows a cross section of the layer overlaying the substrate, where an inductive is fabricated on the surface of the thick polyimide layer, and ferromagnetic material is used to insulate the inductor from the underlying silicon substrate. Additional layers have been added.
FIG. 5 shows a cross-section when a plurality of layers produced on the substrate surface and the substrate are simplified according to the method of the present continuation-in-part application.
FIG. 6 shows the cross section of FIG. 5 when an inductor is added over the passivation layer.
FIG. 7 shows a cross section when a passivation layer is deposited on the surface of the substrate and a capacitor is formed on the surface of the passivation layer.
FIG. 8 shows a three-dimensional view of an inductor made on the surface of a passivation layer by creating a bias in a thick polymer layer.
FIG. 9 shows a three-dimensional view of an inductor made in a thick polymer layer deposited on the surface of a thick polyimide layer.
FIG. 10 shows a cross-section when a passivation layer is deposited on the surface of the substrate, a thick polyimide layer is deposited on the passivation layer, and a capacitor is fabricated on the surface of the thick polyimide layer. ing.
FIG. 11 shows a cross section when a passivation layer is deposited on the surface of the substrate and a resistor is fabricated on the surface of the passivation layer.
FIG. 12 shows a cross-section when a passivation layer is deposited on the surface of the substrate, a thick polyimide layer is deposited on the passivation layer, and a resistor is fabricated on the surface of the thick polyimide layer. Show.
FIG. 13 shows that a discrete electrical element is mounted on the surface of a silicon substrate and contact balls are used so that the distance between the substrate and the electrical element is considerable and thick. The cross section is shown when a polyimide layer is used.
FIG. 14 shows a discrete electrical element mounted on the surface of a silicon substrate, using thick contact balls, resulting in a considerable distance between the substrate and the electrical element; The cross section in the case where the polyimide layer is not used is shown.

Claims (78)

A method of forming an inductor for a high performance integrated circuit that overlays a surface of a semiconductor substrate, comprising:
(a) supplying a semiconductor substrate having an electrical contact provided on the semiconductor element in or on the active surface of the semiconductor substrate into or on the surface where the semiconductor element is fabricated;
(b) producing an overlying interconnect metallization structure comprising one or more layers of interconnects on the active surface of the semiconductor substrate, wherein the layers of interconnects are electrically contacted; Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the overlying interconnect metallization structure, at least one of the electrical contacts One of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the overlaying interconnect metallization structure, the metal line or the contacts or the At least one of the conductive biases contacts at least one of the electrical contacts provided in the semiconductor element in or on the surface of the substrate;
( c) depositing a passivation layer on the overlying interconnect metallization structure;
( d) an insulating / separating polymer layer substantially thicker than the passivation layer and substantially thicker than a dielectric intermediate layer used to fabricate the interconnect metallization structure; Depositing on top;
(e) forming a ferromagnetic layer between the passivation layer and the insulating / separating polymer layer;
through the (f) the insulation and separation polymer layer and the ferromagnetic layer, and the by forming an opening through the passivation layer, on the surface during or surface of the interconnect metallization structures for the overlay Exposing at least a pair of the electrical contacts provided;
(g ) filling the opening with a conductive material to produce a metal contact through the opening; and
(h ) forming the inductor on the surface of the insulating / separating polymer layer, wherein the inductor is provided in or on the surface of the overlying interconnected metallization structure; Connected to at least a pair of contacts;
Including said method. The method of claim 1, wherein the size of the electrical contacts provided in or on the surface of the overlaying interconnect metallization structure ranges from about 0.3 um. To about 50 um. The electrical contacts provided in or on the surface of the overlying interconnected metallization structure are sputtered aluminum, CVD tungsten, CVD copper, electroplated gold, electroplated silver, electroplated copper, electroless gold And a substance selected from the group comprising electroless nickel. The method of claim 1, wherein the inductor is embedded in a dielectric and further covered by a passivation layer. 5. The method of claim 4, wherein the dielectric is a low-K dielectric. One or more layers of ferromagnetic material overlying the passivation layer having a thickness greater than about 2,000-50,000 angstroms and a surface area greater than the surface area over which the inductor substantially overlays the insulating polymer layer. The method according to claim 1, wherein one or more layers of the ferromagnetic material are inserted between the surface of the passivation layer and the insulating / separating polymer layer deposited thereon by addition. 2. The method according to claim 1, wherein the inductor is a spiral design and is made on a surface of the insulating / separating polymer layer and in a plane parallel to the surface of the insulating / isolating polymer layer. The method of claim 1, wherein the inductor is fabricated using a damask patterning method. The method of claim 1, wherein the inductor is fabricated using a photo printing method and a photo etching method. A method for forming a capacitor for a high-performance integrated circuit on a surface of a semiconductor substrate, comprising a top plate, a bottom plate, and a dielectric layer inserted between the top plate and the bottom plate,
(a) supplying a semiconductor substrate having an electrical contact provided on the semiconductor element in or on the active surface of the semiconductor substrate into or on the surface where the semiconductor element is fabricated;
(b) producing an overlying interconnect metallization structure comprising one or more layers of interconnects on the active surface of the semiconductor substrate, wherein the layers of interconnects are electrically contacted; Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the overlaying interconnect metallization structure, at least of the electrical contacts One in contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the overlaid interconnect metallization structure, the metal lines or the contacts or At least one of the conductive biases contacts at least one of the electrical contacts provided on the semiconductor element in or on the surface of the substrate; The electrical contacts provided on the surface of the overlaying interconnected metallization structure are divided into even and odd pairs of adjacent contact locations so that one electrical contact can belong to only one pair. ;
(c) depositing a passivation layer on the overlying interconnect metallization structure;
(d) performing a pattern baking process and an etching process on the passivation layer to form an opening in the passivation layer, wherein at least one opening is in or on the surface of the interconnected metallized structure for overlaying Overlaying at least one flat contact of the electrical contact provided thereon;
(e) attaching a first layer of a conductive material on the surface of the passivation layer including the opening made in the passivation layer;
(f) applying a pattern baking process and an etching process to the first conductive material layer, and at least one of the even-numbered electrical contacts provided in or on the surface of the interconnected metallization structure to be overlaid Making an opening in one and making the bottom plate of the capacitor;
(g) depositing a dielectric layer on the surface of the first conductive material layer including the opening for at least one of the even electrical contacts;
(h) performing a pattern baking process and an etching process on the dielectric layer, creating an opening in the dielectric layer for at least one of the even-numbered electrical contacts, and providing at least one of the even-numbered electrical contacts Making the dielectric layer partially exposed and inserted between the top and bottom plates;
(i) depositing a second conductive material layer on a surface of the dielectric layer including at least one opening made in the dielectric layer; and
(j) performing a pattern baking process and an etching process on the second conductive material layer to produce the upper plate of the capacitor;
Including said method. As an additional processing step performed after the step of pattern baking and etching the passivation layer,
Depositing an insulating / separating polymer layer on the surface of the passivation layer that has been subjected to the pattern baking / etching treatment including the opening formed in the passivation layer; and pattern baking to the insulating / separating polymer layer Processing and etching to create at least one opening in the insulating / separating polymer layer that aligns with at least one of the even-numbered electrical contacts on the surface of the overlaid interconnect metallization structure;
The method of claim 10, comprising: 12. The method of claim 11, wherein the thickness of the insulating / separating polymer layer after curing ranges from about 1.0 to 150 um. 12. The method of claim 11, wherein the insulating and separating polymer layer is spin-on coated and cured. A method for forming a resistor for a high performance integrated circuit on a surface of a semiconductor substrate, comprising:
(a) supplying a semiconductor substrate having an electrical contact provided on the semiconductor element in or on the active surface of the semiconductor substrate into or on the surface where the semiconductor element is fabricated;
(b) producing an overlying interconnect metallization structure comprising one or more layers of interconnects on the active surface of the semiconductor substrate, wherein the layers of interconnects are electrically contacted; Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the overlaying interconnect metallization structure, at least of the electrical contacts One in contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the overlaid interconnect metallization structure, the metal lines or the contacts or At least one of the conductive biases contacts at least one of the electrical contacts provided on the semiconductor element in or on the surface of the substrate. ;
(c) depositing a passivation layer on the overlying interconnect metallization structure;
(d) performing a pattern baking process and an etching process on the passivation layer to form an opening in the passivation layer, wherein at least two of the openings are in the surface of the overlying interconnect metallization structure. Overlay at least a pair of provided electrical contacts;
(e) depositing a conductive material layer on a surface of the passivation layer including the opening made in the passivation layer; and
(f) subjecting the conductive material layer to pattern baking and etching to produce a conductive material layer interconnected with at least a pair of the openings made in the passivation layer, and producing the resistor; Process;
Including said method. A method for forming a resistor for a high performance integrated circuit on a surface of a semiconductor substrate, comprising:
(a) supplying a semiconductor substrate having an electrical contact provided on the semiconductor element in or on the active surface of the semiconductor substrate into or on the surface where the semiconductor element is fabricated;
(b) producing an overlying interconnect metallization structure comprising one or more layers of interconnects on the active surface of the semiconductor substrate, wherein the layers of interconnects are electrically contacted; Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the overlaying interconnect metallization structure, at least of the electrical contacts One in contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the overlaid interconnect metallization structure, the metal lines or the contacts or At least one of the conductive biases contacts at least one of the electrical contacts provided on the semiconductor element in or on the surface of the substrate. ;
(c) depositing a passivation layer on the overlying interconnect metallization structure;
(d) performing a pattern baking process and an etching process on the passivation layer to form an opening in the passivation layer, wherein at least two of the openings are in the surface of the overlying interconnect metallization structure. Overlay and partially expose at least a pair of electrical contacts provided;
(e) a step of attaching an insulating / separating polymer layer on the surface of the passivation layer that has been subjected to the pattern baking / etching treatment including the opening formed in the passivation layer;
(f) A pattern baking process and an etching process are performed on the insulating / separating polymer layer to form at least a pair of openings in the insulating / separating polymer layer aligned with at least the pair of openings formed in the passivation layer. And partially exposing at least a pair of electrical contacts provided in the surface of the overlaying interconnect metallization structure;
(g) attaching a conductive material layer on the surface of the insulating / separating polymer layer including the opening formed in the insulating / separating polymer layer; and
(h) subjecting the conductive material layer to pattern baking and etching to produce a conductive material layer interconnected with at least one of the openings formed in the passivation layer, and producing the resistor; Process;
Including said method. The passivation layer includes a plasma enhanced CVD (PECVD) oxide layer having a thickness in the range of about 0.15-2.0 um., And a PECVD nitride having a thickness in the range of about 0.5-2.0 um. Over the oxide layer. 16. A method according to claim 15, wherein the layer is applied. 16. The method of claim 15, wherein the insulating and separating polymer layer comprises a polymer of polyimide or benzocyclobutene (BCB). 16. The method of claim 15, wherein the thickness of the insulating / separating polymer layer after curing ranges from about 1.0 to 150 um. 16. The method of claim 15, wherein the insulating and separating polymer layer is spin-on coated and cured. 20. The method of claim 19, wherein the insulating / separating polymer layer is subjected to multiple processing steps of spin-on coating and curing. A method of mounting discrete electrical components on a surface of a semiconductor substrate,
(a) supplying a semiconductor substrate having an electrical contact provided on the semiconductor element in or on the active surface of the semiconductor substrate into or on the surface where the semiconductor element is fabricated;
(b) producing an overlying interconnect metallization structure comprising one or more layers of interconnects on the active surface of the semiconductor substrate, wherein the layers of interconnects are electrically contacted; Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the overlaying interconnect metallization structure, at least of the electrical contacts One in contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the overlaid interconnect metallization structure, the metal lines or the contacts or At least one of the conductive biases contacts at least one of the electrical contacts provided on the semiconductor element in or on the surface of the substrate. ;
(c) depositing a passivation layer on the overlying interconnect metallization structure;
(d) performing a pattern baking process and an etching process on the passivation layer to form an opening in the passivation layer, wherein at least two of the openings are in the surface of the overlying interconnect metallization structure. Overlaying at least one pair of provided electrical contacts and providing at least one pair of electrical contacts to the passivation layer;
(e) a step of attaching an insulating / separating polymer layer on the surface of the passivation layer that has been subjected to the pattern baking / etching treatment including the opening formed in the passivation layer;
(f) A pattern baking process and an etching process are performed on the insulating / separating polymer layer to form at least a pair of openings in the insulating / separating polymer layer aligned with at least a pair of electrical contacts provided in the passivation layer. Process;
(g) forming a ferromagnetic layer between the passivation layer and the insulating / separating polymer layer, wherein the opening penetrates the ferromagnetic layer;
( h ) selectively depositing a conductive material layer on the surface of at least a pair of electrical contacts provided to the passivation layer, filling the opening formed in the insulating / separating polymer layer, and Creating a conductive plug through the protective polymer layer, wherein the conductive plug overlays at least a pair of electrical contacts provided to the passivation layer;
( i ) selectively producing a solder layer on the surface of the conductive plug;
( j ) placing the discrete electrical component on the selectively fabricated solder layer and the selective electrical component so that the discrete electrical component is aligned with the selectively fabricated solder layer; Placing in alignment with the solder layer produced in
( k ) Flowing the selectively produced solder layer and producing solder balls in the insulating / separating polymer layer for connecting the discrete electrical component and the conductive plug, thereby producing the discrete electrical component. And a pair of electrical contacts in the passivation layer;
Including said method. 23. The method of claim 21, wherein the insulating / separating polymer layer comprises a polymer of polyimide or benzocyclobutene (BCB). 23. The method of claim 21, wherein the thickness of the insulating / separating polymer layer after curing ranges from about 1.0 to 150 um. 22. The method of claim 21, wherein the insulating / separating polymer layer is subjected to multiple processing steps of spin-on coating and curing. 24. The method of claim 21, wherein the discrete electrical component is selected from the group comprising a resistor, a capacitor, and an inductor. A method of mounting discrete electrical components on a surface of a semiconductor substrate,
(a) supplying a semiconductor substrate having an electrical contact provided on the semiconductor element in or on the active surface of the semiconductor substrate into or on the surface where the semiconductor element is fabricated;
(b) producing an overlying interconnect metallization structure comprising one or more layers of interconnects on the active surface of the semiconductor substrate, wherein the layers of interconnects are electrically contacted; Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the overlaying interconnect metallization structure, at least of the electrical contacts One in contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the overlaid interconnect metallization structure, the metal lines or the contacts or At least one of the conductive biases contacts at least one of the electrical contacts provided on the semiconductor element in or on the surface of the substrate. ;
(c) depositing a passivation layer on the overlying interconnect metallization structure;
(d) performing a pattern baking process and an etching process on the passivation layer to form an opening in the passivation layer, wherein at least two of the openings are in the surface of the overlying interconnect metallization structure. Overlaying at least one pair of provided electrical contacts and providing at least one pair of electrical contacts to the passivation layer;
(e) a step of selectively producing a solder layer on the surface of at least a pair of electrical contacts in the passivation layer;
(f) forming a ferromagnetic layer on the passivation layer, wherein the opening penetrates the ferromagnetic layer;
( g ) placing the discrete electrical component on the selectively fabricated solder layer and in order to align the electrical contacts of the discrete electrical component with the selectively fabricated solder layer; Placing in alignment with the selectively produced solder layer; and
( h ) flowing the selectively produced solder layer, and producing a solder ball that connects the discrete electrical component and at least a pair of electrical contacts in the passivation layer;
Including said method. 27. The method of claim 26, wherein the discrete electrical component is selected from the group comprising a resistor, a capacitor, and an inductor. (a) a semiconductor substrate in or on the surface on which the semiconductor element is fabricated, having electrical contacts provided on the semiconductor element in or on the active surface of the semiconductor substrate;
(b) an overlying interconnect metallization structure comprising one or more layers of interconnects on the active surface of the substrate, wherein the interconnect layers are interconnected with electrical contacts on the overlay Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the connecting metallization structure, wherein at least one of the electrical contacts is the overlay In contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the interconnecting metallization structure, and at least of the metal lines or the contacts or the conductive bias One contacts at least one of the electrical contacts provided in the semiconductor element in or on the surface of the substrate;
(c) a passivation layer deposited on the overlying interconnect metallization structure;
(d) Insulation / separation deposited on the passivation layer that is substantially thicker than the passivation layer and substantially thicker than the dielectric intermediate layer used to fabricate the interconnect metallization structure. For polymer layer;
(e) forming a ferromagnetic layer between the passivation layer and the insulating / separating polymer layer; and
( f ) In order to expose at least one pair of the electrical contacts provided in or on the surface of the overlying interconnecting metallization structure, the insulating / separating polymer layer , the ferromagnetic layer, and the An opening formed through the passivation layer, wherein the opening is filled with a conductive material to create a metal contact through the opening;
Is formed on the surface of the insulating / separating polymer layer, and is connected to at least a pair of the electrical contacts provided in or on the surface of the overlying interconnecting metallization structure, Inductors for high-performance integrated circuits that overlay the surface of a semiconductor substrate. 30. The inductor of claim 28, wherein a size of the electrical contact provided in or on the surface of the overlaid interconnecting metallization structure ranges from about 0.3 um. To about 50 um. The passivation layer includes a plasma enhanced CVD (PECVD) oxide layer having a thickness in the range of about 0.15-2.0 um., And a PECVD nitride having a thickness in the range of about 0.5-2.0 um. Over the oxide layer. 30. The inductor of claim 28, wherein the layer is deposited. 29. The inductor according to claim 28, wherein the insulating / separating polymer layer includes a polymer of polyimide or benzocyclobutene (BCB). 29. The inductor of claim 28, wherein the thickness of the insulating / separating polymer layer after curing ranges from about 1.0 to 150 um. 29. The inductor of claim 28, wherein the insulating / separating polymer layer is spin-on coated and cured. 29. The inductor according to claim 28, wherein the insulating / separating polymer layer is subjected to a plurality of spin-on coating and curing processes. The electrical contacts provided in or on the surface of the overlying interconnected metallization structure are sputtered aluminum, CVD tungsten, CVD copper, electroplated gold, electroplated copper, electroplated silver, electroless gold 30. The inductor according to claim 28, comprising a material selected from the group comprising electroless nickel. 30. The inductor of claim 28, wherein the inductor is embedded in a dielectric and is further covered by a passivation layer. 38. The inductor of claim 36, wherein the dielectric is a low-K dielectric. One or more layers of ferromagnetic material overlaying the passivation layer having a thickness greater than about 2-50 kilo angstroms and a surface area greater than a surface area over which the inductor substantially overlays the insulating polymer layer; 30. The inductor of claim 28, wherein one or more layers of the ferromagnetic material are inserted between the surface of the passivation layer and the insulating / separating polymer layer deposited thereon by adding . 29. The inductor according to claim 28, wherein the inductor is a spiral design and is made on a surface of the insulating / separating polymer layer and in a plane parallel to the surface of the insulating / isolating polymer layer. 30. The inductor of claim 28, wherein the inductor is made using a damask patterning process. 29. The inductor of claim 28, wherein the inductor is made using a photo printing method and a photo etching method. A high performance integrated circuit capacitor on a surface of a semiconductor substrate, comprising a top plate, a bottom plate, and a dielectric layer inserted between the top plate and the bottom plate,
(a) a semiconductor substrate in or on the surface where the semiconductor element is fabricated, having electrical contacts provided on the semiconductor element in or on the active surface of the semiconductor substrate;
(b) an overlying interconnect metallization structure including one or more layers of interconnects on the active surface of the substrate, wherein the interconnect layers are interconnected with electrical contacts overlaid with the overlay. Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the connecting metallization structure, wherein at least one of the electrical contacts is the overlay In contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the interconnecting metallization structure, and at least of the metal lines or the contacts or the conductive bias One contacts and overlays at least one of the electrical contacts provided on the semiconductor element in or on the surface of the substrate The electrical contacts provided on the surface of the interconnecting metallization structure are divided into even and odd pairs of adjacent contact points, whereby one electrical contact can belong to only one pair;
(c) a passivation layer deposited on the overlying interconnect metallization structure;
(d) at least one flat surface of the electrical contact provided in or on the surface of the overlying interconnect metallization structure, wherein an opening made in the passivation layer, wherein at least one opening is provided. Overlay contacts;
(e) a first layer of a conductive material deposited on the surface of the passivation layer including the openings made in the passivation layer;
(f) an opening made in the first conductive material layer for at least one of the even-numbered electrical contacts provided in or on the surface of the overlying interconnecting metallization structure, Sometimes the first conductive material layer forms the bottom plate of the capacitor;
(g) a dielectric layer deposited on the surface of the first conductive material layer including the opening for at least one of the even electrical contacts;
(h) an opening in the dielectric layer with respect to at least one of the even-numbered electrical contacts, wherein the opening partially exposes at least one of the even-numbered electrical contacts, and the upper plate and the Constituting the dielectric layer inserted between the bottom plate; and
(i) a second conductive material layer deposited on the surface of the dielectric layer including at least one opening made in the dielectric layer;
And the upper plate of the capacitor is produced by subjecting the second conductive material layer to pattern baking and etching. On the passivation layer subjected to the pattern baking / etching process,
An insulating / separating polymer layer deposited on the surface of the pattern-baked / etched passivation layer including the opening made in the passivation layer; and on the surface of the overlying interconnect metallization structure; At least one opening made in the insulating / separating polymer layer aligned with at least one of the even electrical contacts;
43. The capacitor of claim 42, further comprising: The passivation layer includes a plasma enhanced CVD (PECVD) oxide layer having a thickness in the range of about 0.15-2.0 um., And a PECVD nitride having a thickness in the range of about 0.5-2.0 um. Over the oxide layer. 43. The capacitor of claim 42, wherein a layer is deposited. 44. The capacitor according to claim 43, wherein the insulating / separating polymer layer includes a polymer of polyimide or benzocyclobutene (BCB). 44. The capacitor of claim 43, wherein the thickness of the insulating / separating polymer layer after curing ranges from about 1.0 to 150 um. 44. The method of claim 43 , wherein the insulating and separating polymer layer is spin-on coated and cured. (a) a semiconductor substrate in or on the surface where the semiconductor element is fabricated, having electrical contacts provided on the semiconductor element in or on the active surface of the semiconductor substrate;
(b) an overlying interconnect metallization structure including one or more layers of interconnects on the active surface of the substrate, wherein the interconnect layers are interconnected with electrical contacts overlaid with the overlay. Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the connecting metallization structure, wherein at least one of the electrical contacts is the overlay In contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the interconnecting metallization structure, and at least of the metal lines or the contacts or the conductive bias One contacts at least one of the electrical contacts provided in the semiconductor element in or on the surface of the substrate;
(c) a passivation layer deposited on the overlying interconnect metallization structure;
(d) openings made in the passivation layer, wherein at least two of the openings overlay at least a pair of the electrical contacts provided in the surface of the overlaid interconnect metallization structure;
(e) a layer of conductive material deposited on the surface of the passivation layer including the openings made in the passivation layer; and
(f) a layer of conductive material that interconnects at least a pair of the openings made in the passivation layer, thereby creating a resistor;
A resistor for high performance integrated circuits on the surface of a semiconductor substrate. The passivation layer includes a plasma enhanced CVD (PECVD) oxide layer having a thickness in the range of about 0.15-2.0 um., And a PECVD nitride having a thickness in the range of about 0.5-2.0 um. Over the oxide layer. 49. The resistor of claim 48, wherein the layer is deposited. (a) a semiconductor substrate in or on the surface where the semiconductor element is fabricated, having electrical contacts provided on the semiconductor element in or on the active surface of the semiconductor substrate;
(b) an overlying interconnect metallization structure including one or more layers of interconnects on the active surface of the substrate, wherein the interconnect layers are interconnected with electrical contacts overlaid with the overlay. Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the connecting metallization structure, wherein at least one of the electrical contacts is the overlay In contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the interconnecting metallization structure, and at least of the metal lines or the contacts or the conductive bias One contacts at least one of the electrical contacts provided in the semiconductor element in or on the surface of the substrate;
(c) a passivation layer deposited on the overlying interconnect metallization structure;
(d) openings formed in the passivation layer, wherein at least two of the openings overlay at least a pair of electrical contacts provided in the surface of the overlying interconnected metallization structure, and a portion Exposed to light;
(e) an insulating / separating polymer layer deposited on the surface of the passivation layer that has been subjected to the pattern baking / etching treatment including the opening formed in the passivation layer;
(f) the insulation being aligned with at least one pair of openings made in the passivation layer and partially exposing at least one pair of electrical contacts provided in a surface of the overlying interconnect metallization structure; At least a pair of openings in the separating polymer layer;
(g) a layer of conductive material deposited on the surface of the insulating / separating polymer layer including the opening made in the insulating / separating polymer layer; and
(h) a layer of conductive material that interconnects at least a pair of the openings made in the passivation layer, thereby creating a resistor;
A resistor for high performance integrated circuits on the surface of a semiconductor substrate. The passivation layer includes a plasma enhanced CVD (PECVD) oxide layer having a thickness in the range of about 0.15-2.0 um., And a PECVD nitride having a thickness in the range of about 0.5-2.0 um. Over the oxide layer. 51. The resistor of claim 50, wherein the layer is deposited. 51. The resistor of claim 50, wherein the insulating / separating polymer layer comprises a polymer of polyimide or benzocyclobutene (BCB). 51. The resistor of claim 50, wherein the thickness of the insulating / separating polymer layer after curing ranges from about 1.0 to 150 um. 51. The resistor of claim 50, wherein the insulating and separating polymer layer is spin-on coated and cured. 51. The resistor of claim 50, wherein the insulating / separating polymer layer is subjected to multiple processing steps of spin-on coating and curing. Discrete electrical components on the surface of a semiconductor substrate,
(a) a semiconductor substrate in or on the surface where the semiconductor element is fabricated, having electrical contacts provided on the semiconductor element in or on the active surface of the semiconductor substrate;
(b) an overlying interconnect metallization structure including one or more layers of interconnects on the active surface of the substrate, wherein the interconnect layers are interconnected with electrical contacts overlaid with the overlay. Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the connecting metallization structure, wherein at least one of the electrical contacts is the overlay In contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the interconnecting metallization structure, and at least of the metal lines or the contacts or the conductive bias One contacts at least one of the electrical contacts provided in the semiconductor element in or on the surface of the substrate;
(c) a passivation layer deposited on the overlying interconnect metallization structure;
(d) Openings made in the passivation layer, wherein at least two of the openings overlay at least a pair of electrical contacts provided in the surface of the overlying interconnected metallization structure, and at least a pair Providing electrical contact to the passivation layer;
(e) an insulating / separating polymer layer deposited on the surface of the passivation layer that has been subjected to the pattern baking / etching treatment including the opening formed in the passivation layer;
(f) a ferromagnetic layer formed on the passivation layer, wherein the opening penetrates the ferromagnetic layer;
( g ) at least a pair of openings made in the insulating / separating polymer layer, aligned with at least a pair of electrical contacts provided in the passivation layer;
( h ) a layer of conductive material selectively deposited on at least a pair of surfaces of the electrical contacts provided to the passivation layer, wherein the openings made in the insulating / separating polymer layer are filled. A conductive plug is made through the insulating / separating polymer layer, and the conductive plug overlays at least a pair of electrical contacts provided to the passivation layer; and
( i ) a solder layer selectively produced on the surface of the conductive plug;
Wherein the discrete electrical component is over the selectively fabricated solder layer and the selection such that electrical contacts of the discrete electrical component are aligned with the selectively fabricated solder layer. Solder that is arranged in an aligned manner with the solder layer that has been manufactured in order to connect the conductive plug in the insulating / separating polymer layer and the discrete electrical component in which the selectively manufactured solder layer is flowed The discrete electrical component in which a ball is produced, thereby connecting a pair of electrical contacts in the passivation layer and the discrete electrical component. The passivation layer includes a plasma enhanced CVD (PECVD) oxide layer having a thickness in the range of about 0.15-2.0 um., And a PECVD nitride having a thickness in the range of about 0.5-2.0 um. Over the oxide layer. 58. The discrete electrical component of claim 56, wherein the layer is applied. 57. The discrete electrical component of claim 56, wherein the insulating / separating polymer layer includes a polymer of polyimide or benzocyclobutene (BCB). 57. The discrete electrical component of claim 56, wherein the thickness of the insulating / separating polymer layer after curing ranges from about 1.0 to 150 um. 57. The discrete electrical component of claim 56, wherein the insulating / separating polymer layer is spin-on coated and cured. 57. The discrete electrical component of claim 56, wherein the insulating / separating polymer layer is subjected to multiple processing steps of spin-on coating and curing. 57. The discrete electrical component of claim 56, wherein the discrete electrical component is selected from the group comprising a resistor, a capacitor, and an inductor. A discrete electrical component mounted on the surface of a semiconductor substrate,
(a) a semiconductor substrate in or on the surface where the semiconductor element is fabricated, having electrical contacts provided on the semiconductor element in or on the active surface of the semiconductor substrate;
(b) an overlying interconnect metallization structure including one or more layers of interconnects on the active surface of the substrate, wherein the interconnect layers are interconnected with electrical contacts overlaid with the overlay. Conductive interconnect lines or conductive contacts or conductive biases in one or more layers, provided in or on the surface of the connecting metallization structure, wherein at least one of the electrical contacts is the overlay In contact with at least one of the conductive interconnect lines or the conductive contacts or the conductive bias provided in the one or more layers of the interconnecting metallization structure, and at least of the metal lines or the contacts or the conductive bias One contacts at least one of the electrical contacts provided in the semiconductor element in or on the surface of the substrate;
(c) a passivation layer deposited on the overlying interconnect metallization structure;
(d) Openings made in the passivation layer, wherein at least two of the openings overlay at least a pair of electrical contacts provided in the surface of the overlying interconnected metallization structure, and at least a pair Providing electrical contact to the passivation layer;
(e) a solder layer selectively deposited on the surface of at least one pair of electrical contacts in the passivation layer; and
(f) a ferromagnetic layer formed on the passivation layer, wherein the opening penetrates the ferromagnetic layer;
Wherein the discrete electrical component is over the selectively deposited solder layer and the selection so that electrical contacts of the discrete electrical component are aligned with the selectively deposited solder layer. Disposed in alignment with the selectively applied solder layer, the selectively applied solder layer is flowed, and at least a pair of electrical contacts in the passivation layer and the discrete electrical component are connected, Discrete electrical equipment. The passivation layer includes a plasma enhanced CVD (PECVD) oxide layer having a thickness in the range of about 0.15-2.0 um., And a PECVD nitride having a thickness in the range of about 0.5-2.0 um. Over the oxide layer. 64. The discrete electrical component of claim 63, wherein the layer is applied. 64. The discrete electrical component of claim 63, wherein the discrete electrical component is selected from the group comprising a resistor, a capacitor, and an inductor. The method of claim 1, wherein the inductor is fabricated to overlay the surface of the passivation layer so that no polyimide layer is applied. The method of claim 1, wherein the inductor is a helical structure that overlays a polymer layer, the polymer layer overlaying a passivation layer. The method of claim 1, wherein the inductor is a spiral structure overlaying a passivation layer so that a layer of polyimide is not applied. 12. The method according to claim 11, wherein the insulating / separating polymer layer is a dry laminate film. 16. The method according to claim 15, wherein the insulating / separating polymer layer is a dry laminate film. The method of claim 21, wherein the solder balls are made by electroplating, screen printing, and ball mounting. The method according to claim 21, wherein the insulating / separating polymer layer is a dry laminate film. 29. The method according to claim 28, wherein the insulating / separating polymer layer is a dry laminate film. The inductor is a spiral design and is fabricated on a surface of the insulating / separating polymer layer and in a plane parallel to the surface of the insulating / separating polymer layer, whereby the polymer layer is a passivation layer. 30. The inductor of claim 28, wherein the inductor is deposited on the surface of the substrate. The inductor is a spiral design, and is fabricated on the surface of the insulating / separating polymer layer and in a plane parallel to the surface of the insulating / separating polymer layer, whereby the polymer layer is a polyimide layer. 29. The inductor of claim 28, wherein the inductor layer is deposited on the surface of the passivation layer, whereby the polyimide layer is deposited on the surface of the passivation layer. 44. The capacitor according to claim 43, wherein the insulating / separating polymer layer is a dry laminate film. 51. The resistor according to claim 50, wherein the insulating / separating polymer layer is a dry laminate film. 57. The discrete electrical component of claim 56, wherein the insulating / separating polymer layer is a dry laminate film.

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