JPH0262069A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0262069A
JPH0262069A JP21310388A JP21310388A JPH0262069A JP H0262069 A JPH0262069 A JP H0262069A JP 21310388 A JP21310388 A JP 21310388A JP 21310388 A JP21310388 A JP 21310388A JP H0262069 A JPH0262069 A JP H0262069A
Authority
JP
Japan
Prior art keywords
semiconductor
chip
precision
chips
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21310388A
Other languages
Japanese (ja)
Inventor
Hajime Nakamura
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP21310388A priority Critical patent/JPH0262069A/en
Publication of JPH0262069A publication Critical patent/JPH0262069A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73207Bump and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19102Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

Abstract

PURPOSE:To miniaturize an electronic circuit requiring high precision and prevent noise pickup by wiring for resistors and capacitors by mounting high precision passive elements on a semiconductor IC pellet and integrating them. CONSTITUTION:A silicon chip 2, on whose surface high precision passive elements 6 are formed, is mounted on the surface of a semiconductor IC chip 1. Electrodes of both chips are connected via connecting electrodes 3, 4 provided on the respective surfaces of the chips by means of solder 5. Then, the IC chip 1 is mounted on a lead frame 7 and wires 9 are bonded to connect the lead frame 7 to the IC 1. Further, these are wholly sealed by molding resin 8.
JP21310388A 1988-08-26 1988-08-26 Semiconductor device Pending JPH0262069A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21310388A JPH0262069A (en) 1988-08-26 1988-08-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21310388A JPH0262069A (en) 1988-08-26 1988-08-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0262069A true JPH0262069A (en) 1990-03-01

Family

ID=16633624

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21310388A Pending JPH0262069A (en) 1988-08-26 1988-08-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0262069A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5376825A (en) * 1990-10-22 1994-12-27 Seiko Epson Corporation Integrated circuit package for flexible computer system alternative architectures
US5446309A (en) * 1992-06-22 1995-08-29 Matsushita Electric Industrial Co., Ltd. Semiconductor device including a first chip having an active element and a second chip having a passive element
WO1999034444A1 (en) * 1997-12-25 1999-07-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
JP2003086690A (en) * 2001-09-04 2003-03-20 Megic Corp High performance system on-chip using post passivation method
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
JP2007243229A (en) * 2007-06-25 2007-09-20 Fujitsu Ltd Semiconductor device
JP2008538865A (en) * 2005-04-28 2008-11-06 エヌエックスピー ビー ヴィ Integrated circuit assembly having a passive integrated substrate for power and ground line routing on an integrated circuit chip

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5376825A (en) * 1990-10-22 1994-12-27 Seiko Epson Corporation Integrated circuit package for flexible computer system alternative architectures
US5446309A (en) * 1992-06-22 1995-08-29 Matsushita Electric Industrial Co., Ltd. Semiconductor device including a first chip having an active element and a second chip having a passive element
WO1999034444A1 (en) * 1997-12-25 1999-07-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
JP2003086690A (en) * 2001-09-04 2003-03-20 Megic Corp High performance system on-chip using post passivation method
JP2008538865A (en) * 2005-04-28 2008-11-06 エヌエックスピー ビー ヴィ Integrated circuit assembly having a passive integrated substrate for power and ground line routing on an integrated circuit chip
JP4904601B2 (en) * 2005-04-28 2012-03-28 エスティー‐エリクソン、ソシエテ、アノニム Integrated circuit assembly having a passive integrated substrate for power and ground line routing on an integrated circuit chip
US8178901B2 (en) 2005-04-28 2012-05-15 St-Ericsson Sa Integrated circuit assembly with passive integration substrate for power and ground line routing on top of an integrated circuit chip
JP2007243229A (en) * 2007-06-25 2007-09-20 Fujitsu Ltd Semiconductor device
JP4538473B2 (en) * 2007-06-25 2010-09-08 富士通株式会社 Semiconductor device

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