JPH0262069A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0262069A JPH0262069A JP63213103A JP21310388A JPH0262069A JP H0262069 A JPH0262069 A JP H0262069A JP 63213103 A JP63213103 A JP 63213103A JP 21310388 A JP21310388 A JP 21310388A JP H0262069 A JPH0262069 A JP H0262069A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- chip
- passive elements
- high precision
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims abstract description 7
- 239000010409 thin film Substances 0.000 claims description 14
- 229910000679 solder Inorganic materials 0.000 abstract description 4
- 239000011347 resin Substances 0.000 abstract description 3
- 229920005989 resin Polymers 0.000 abstract description 3
- 239000008188 pellet Substances 0.000 abstract description 2
- 238000000465 moulding Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体ＩＣに関し、特に高精度受動素子を有す
る半導体ＩＣの構成に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor IC, and more particularly to a structure of a semiconductor IC having high-precision passive elements.
従来、高精度受動素子を・必要とする電子回路において
は、能動素子及び、精度を必要としない受動素子を半導
体ＩＣで構成し、高精度受動素子は外付けのディスクリ
ート部品、あるいは薄膜ＩＣ等で構成していた。Conventionally, in electronic circuits that require high-precision passive elements, active elements and passive elements that do not require precision are constructed with semiconductor ICs, and high-precision passive elements are constructed with external discrete components or thin-film ICs. It was composed.
上述した従来の半導体装Ｃは高精度受動素子がディスク
リート部品あるいは薄膜ＩＣとなっているためプリント
板上で多くの面積を必要とし、また、配線の引回しが長
くなりノイズを拾い易い等の欠点がある。The above-mentioned conventional semiconductor device C has drawbacks such as high-precision passive elements that are discrete components or thin film ICs, which require a large area on the printed board, and also have long wiring and are prone to pick up noise. There is.
本発明の半導体ＩＣは高精度を有する薄膜抵抗あるいは
薄膜コンデンサを形成したシリコンチップと、該シリコ
ンチップと電気的接続可能な電極を有した半導体ＩＣか
らなる。The semiconductor IC of the present invention includes a silicon chip on which a highly accurate thin film resistor or thin film capacitor is formed, and a semiconductor IC having electrodes that can be electrically connected to the silicon chip.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。半導体ＩＣ
チップ１の表面に高精度受動素子６を表面に形成したシ
リコンチップ２を搭載スル。FIG. 1 is a sectional view of an embodiment of the present invention. semiconductor IC
A silicon chip 2 on which a high-precision passive element 6 is formed is mounted on the surface of the chip 1.
両チップ間の電極は、それぞれのチップの表面に設けら
れた接続用電極４，５を介して半田５を利用しりフロー
により接続される。しかる後リードフレーム７上に半導
体ＩＣチップ１をマウントし、ワイヤ９をポンディング
しリードフレーム７と半導体ＩＣＩを電極的に接続する
。さらにモールド樹脂８で全体を封止する。なお、高精
度受動素子としては薄膜の抵抗および薄膜のコンデンサ
でありタンタル等の材料が使われ、シリコンチップの表
面に酸化膜等の絶縁膜を介し、その上に形成される。The electrodes between both chips are connected by solder flow using solder 5 via connection electrodes 4 and 5 provided on the surface of each chip. Thereafter, the semiconductor IC chip 1 is mounted on the lead frame 7, and the wires 9 are bonded to connect the lead frame 7 and the semiconductor ICI in an electrode manner. Furthermore, the entire structure is sealed with mold resin 8. The high-precision passive elements are thin-film resistors and thin-film capacitors made of materials such as tantalum, and are formed on the surface of a silicon chip with an insulating film such as an oxide film interposed therebetween.
第２図は本発明の実施例２の断面図である。半導体ＩＣ
ｌ０の表面に高精度受動素子を有するシリコンチップ１
９を２個搭載したものであり、例えば一方のチップ１１
に薄膜抵抗のみ、他方のチップ１９には薄膜コンデンサ
のみ形成した場合、１ケのチップの上に薄膜抵抗と薄膜
コンデンサを共に形成した場合に比ベコストが安くなる
という利点がある。また、薄膜抵抗体の材料にタンタル
以外のタングステン、ニクロム等の金属を自由に選べる
という利点もある。FIG. 2 is a sectional view of Example 2 of the present invention. semiconductor IC
Silicon chip 1 with high precision passive elements on the surface of l0
For example, one chip 11
When only a thin film resistor is formed on one chip and only a thin film capacitor is formed on the other chip 19, there is an advantage that the cost is lower than when both a thin film resistor and a thin film capacitor are formed on one chip. Another advantage is that metals other than tantalum, such as tungsten and nichrome, can be freely selected as the material for the thin film resistor.
以上説明したように本発明は、半導体ＩＣペレット上に
高精度受動素子を搭載し一体化することで、高精度を必
要とする電子回路をより小型化できると同時に抵抗、コ
ンデンサのための配線の引回しによるノイズの飛込みを
防止できるという効果がある。As explained above, the present invention makes it possible to further downsize electronic circuits that require high precision by mounting and integrating high-precision passive elements on a semiconductor IC pellet, while at the same time reducing the wiring for resistors and capacitors. This has the effect of preventing noise from entering due to routing.
第１図は、本発明の半導体ＩＣの実施例１の断面図、第
２図は本発明の第２の実施例の断面図である。
１．１０・・・・・・半導体ＩＣ１２，１１・・・・・
・受動素子を形成したシリコンチップ、３．１２・・・
・・・半導体ＩＣのシリコンチップとの接続用電極、４
゜１３・・・・・・シリコンチップの半導体ＩＣとの接
続用電極、５，１４・・・・・・半田、６，１５．２０
・・・・・・薄膜受動素子、７，１６・・・・・・リー
ドフレーム、８゜１７・・・・・・封止樹脂、９，１８
・・・・・・ポンディングワイヤ。
代理人 弁理士 内 原 晋FIG. 1 is a cross-sectional view of a first embodiment of a semiconductor IC of the present invention, and FIG. 2 is a cross-sectional view of a second embodiment of the present invention. 1.10...Semiconductor IC12, 11...
・Silicon chip with passive elements formed, 3.12...
... Electrode for connection with silicon chip of semiconductor IC, 4
゜13... Electrode for connecting silicon chip to semiconductor IC, 5, 14... Solder, 6, 15.20
... Thin film passive element, 7, 16 ... Lead frame, 8゜17 ... Sealing resin, 9, 18
・・・・・・Ponding wire. Agent Patent Attorney Susumu Uchihara
Claims (1)
シリコンチップを半導体ＩＣチップ上に搭載し、それぞ
れの該チップ上に設けられた接続用電極を介して電気的
に接続した後に封止したことを特徴とする半導体装置。A silicon chip with a thin film resistor or a thin film capacitor formed on the surface thereof is mounted on a semiconductor IC chip, electrically connected through connection electrodes provided on each chip, and then sealed. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63213103A JPH0262069A (en) | 1988-08-26 | 1988-08-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63213103A JPH0262069A (en) | 1988-08-26 | 1988-08-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0262069A true JPH0262069A (en) | 1990-03-01 |
Family
ID=16633624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63213103A Pending JPH0262069A (en) | 1988-08-26 | 1988-08-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0262069A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5376825A (en) * | 1990-10-22 | 1994-12-27 | Seiko Epson Corporation | Integrated circuit package for flexible computer system alternative architectures |
| US5446309A (en) * | 1992-06-22 | 1995-08-29 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device including a first chip having an active element and a second chip having a passive element |
| WO1999034444A1 (en) * | 1997-12-25 | 1999-07-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
| JP2003086690A (en) * | 2001-09-04 | 2003-03-20 | Megic Corp | High performance system on-chip using post passivation method |
| US7112468B2 (en) | 1998-09-25 | 2006-09-26 | Stmicroelectronics, Inc. | Stacked multi-component integrated circuit microprocessor |
| JP2007243229A (en) * | 2007-06-25 | 2007-09-20 | Fujitsu Ltd | Semiconductor device |
| JP2008538865A (en) * | 2005-04-28 | 2008-11-06 | エヌエックスピー ビー ヴィ | Integrated circuit assembly having a passive integrated substrate for power and ground line routing on an integrated circuit chip |
| JP2022047347A (en) * | 2020-09-11 | 2022-03-24 | 株式会社東芝 | Semiconductor device |
-
1988
- 1988-08-26 JP JP63213103A patent/JPH0262069A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5376825A (en) * | 1990-10-22 | 1994-12-27 | Seiko Epson Corporation | Integrated circuit package for flexible computer system alternative architectures |
| US5446309A (en) * | 1992-06-22 | 1995-08-29 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device including a first chip having an active element and a second chip having a passive element |
| WO1999034444A1 (en) * | 1997-12-25 | 1999-07-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
| US7112468B2 (en) | 1998-09-25 | 2006-09-26 | Stmicroelectronics, Inc. | Stacked multi-component integrated circuit microprocessor |
| JP2003086690A (en) * | 2001-09-04 | 2003-03-20 | Megic Corp | High performance system on-chip using post passivation method |
| JP2008538865A (en) * | 2005-04-28 | 2008-11-06 | エヌエックスピー ビー ヴィ | Integrated circuit assembly having a passive integrated substrate for power and ground line routing on an integrated circuit chip |
| JP4904601B2 (en) * | 2005-04-28 | 2012-03-28 | エスティー‐エリクソン、ソシエテ、アノニム | Integrated circuit assembly having a passive integrated substrate for power and ground line routing on an integrated circuit chip |
| US8178901B2 (en) | 2005-04-28 | 2012-05-15 | St-Ericsson Sa | Integrated circuit assembly with passive integration substrate for power and ground line routing on top of an integrated circuit chip |
| JP2007243229A (en) * | 2007-06-25 | 2007-09-20 | Fujitsu Ltd | Semiconductor device |
| JP4538473B2 (en) * | 2007-06-25 | 2010-09-08 | 富士通株式会社 | Semiconductor device |
| JP2022047347A (en) * | 2020-09-11 | 2022-03-24 | 株式会社東芝 | Semiconductor device |
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