JP2809191B2 - Semiconductor chip mounting method - Google Patents
Semiconductor chip mounting methodInfo
- Publication number
- JP2809191B2 JP2809191B2 JP8109250A JP10925096A JP2809191B2 JP 2809191 B2 JP2809191 B2 JP 2809191B2 JP 8109250 A JP8109250 A JP 8109250A JP 10925096 A JP10925096 A JP 10925096A JP 2809191 B2 JP2809191 B2 JP 2809191B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- mounting
- module
- board
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体チップ等の
部品のプリント基板への実装方法に関する。The present invention relates to a method for mounting components such as semiconductor chips on a printed circuit board.
【０００２】[0002]
【従来の技術】図５は、従来の半導体チップ等の実装方
法の一例を示す断面図である。2. Description of the Related Art FIG. 5 is a sectional view showing an example of a conventional method for mounting a semiconductor chip or the like.
【０００３】図５に示すように、従来の半導体チップ等
の実装方法は、モジュール基板６１上にマウント剤６２
を使用して半導体チップ６４を搭載し、ボンディングワ
イヤ６３により半導体チップ６４とモジュール基板６１
間を電気的に接続した後、封止樹脂６６により表面を保
護する。さらにモジュール基板６１上に他の部品６５
を、半田６８により接続するという実装方法をとってい
た。以上の方法により半導体チップ６４および他の部品
６５を搭載したモジュール基板６１をプリント基板６７
上にリード６９により電気的に接続する実装方法であっ
た。As shown in FIG. 5, a conventional mounting method for a semiconductor chip or the like uses a mounting agent 62 on a module substrate 61.
The semiconductor chip 64 is mounted by using the
After the electrical connection is made, the surface is protected by the sealing resin 66. Further, another component 65 is placed on the module substrate 61.
Are connected by a solder 68. The module board 61 on which the semiconductor chip 64 and the other components 65 are mounted is mounted on the printed board 67
This is a mounting method of electrically connecting with the leads 69 on the upper side.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来の
半導体チップ等の実装方法の問題点は、上述の図５に示
すような実装構造においては、実装高さが高くなること
である。その理由は、プリント基板６７上にモジュール
６１、半導体チップ６４および封止樹脂６６が積み重な
る構造であることによる。However, a problem with the conventional mounting method of a semiconductor chip or the like is that the mounting height is increased in the mounting structure as shown in FIG. The reason is that the module 61, the semiconductor chip 64, and the sealing resin 66 are stacked on the printed board 67.
【０００５】一方、これら実装方法についての現状を見
ると、例えば携帯用電子機器は、一層の携帯性の向上が
求められ、その実装設計においては０．１ｍｍあるいは
それ以下の単位での薄型化および小型化が要請されてい
る。On the other hand, looking at the current state of these mounting methods, for example, portable electronic devices are required to be further improved in portability. There is a demand for miniaturization.
【０００６】そこで、本発明の目的は、半導体チップ等
の部品を搭載したモジュール基板をプリント基板に実装
する際、装置全体の薄型化および小型化のための高集積
化を実現するような、半導体チップ等の実装方法を提供
することである。Accordingly, an object of the present invention is to provide a semiconductor device which is mounted on a printed circuit board on which a module such as a semiconductor chip is mounted. An object of the present invention is to provide a mounting method of a chip or the like.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体チップの
実装方法は、少なくとも半導体チップを含む部品がモジ
ュール基板上に搭載され、かつこれら部品がモジュール
基板と電気的に接続されて成るモジュールをプリント基
板に実装する、半導体チップの実装方法において、モジ
ュール基板上の部品搭載位置に対応したプリント基板の
部分を該基板面に垂直にくり抜き、モジュールとプリン
ト基板とを電気的に接続し、モジュール基板とプリント
基板間の隙間を封止樹脂で充填する、ことを特徴として
いる。According to the method of mounting a semiconductor chip of the present invention, a module including at least a component including a semiconductor chip mounted on a module substrate and being electrically connected to the module substrate is printed. In the method of mounting a semiconductor chip mounted on a board, a portion of a printed board corresponding to a component mounting position on a module board is cut out perpendicularly to the board surface, and the module and the printed board are electrically connected to each other. It is characterized in that gaps between printed boards are filled with a sealing resin.
【０００８】なお、この半導体チップの実装方法は、モ
ジュール基板上に搭載された部品が、半導体チップのほ
か、抵抗、コンデンサ、ダイオード及びトランジスタで
ある、ことが望ましい。In this method of mounting a semiconductor chip, it is desirable that the components mounted on the module substrate be a resistor, a capacitor, a diode, and a transistor in addition to the semiconductor chip.
【０００９】[0009]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.
【００１０】図１は、本発明の半導体チップ等の部品の
実装方法の一実施形態例を示す断面図、図２（ａ），
（ｂ），（ｃ），（ｄ）は、本実施形態例を各工程順に
示す断面図である。FIG. 1 is a sectional view showing an embodiment of a method for mounting a component such as a semiconductor chip according to the present invention.
(B), (c), (d) is sectional drawing which shows this embodiment example in order of each process.
【００１１】図１を参照すると、本発明の実施の形態
は、モジュール基板１上に半導体チップ４および他の部
品５を搭載し、それらの部品の搭載位置に対応した部分
をくり抜いたプリント基板７と組み合せて実装する。モ
ジュール基板１の種類としては、シリコン基板、セラミ
ック基板、ガラスエポキシ樹脂などが望ましい。モジュ
ール基板１としてシリコン基板を使用することにより半
導体チップ４と同等の微細配線が形成でき、最も高集積
化された基板を実現できる。さらにシリコン基板を使用
することにより、抵抗、コンデンサ、ダイオードおよび
トランジスタなどの素子をシリコン基板内に内蔵するこ
とも可能になる。またモジュール基板１としてガラスエ
ポキシ基板を使用することにより、低価格なモジュール
を実現できる。Referring to FIG. 1, according to an embodiment of the present invention, a printed circuit board 7 in which a semiconductor chip 4 and other components 5 are mounted on a module substrate 1 and a portion corresponding to a mounting position of those components is cut out. Implement in combination with. As a type of the module substrate 1, a silicon substrate, a ceramic substrate, a glass epoxy resin, or the like is desirable. By using a silicon substrate as the module substrate 1, fine wiring equivalent to the semiconductor chip 4 can be formed, and the most highly integrated substrate can be realized. Further, by using a silicon substrate, elements such as a resistor, a capacitor, a diode, and a transistor can be built in the silicon substrate. By using a glass epoxy substrate as the module substrate 1, a low-cost module can be realized.
【００１２】以上説明した実装構造を採用することによ
り、半導体チップ４および他の部品５の厚みがプリント
基板７の厚みよりも薄ければ、実装の全体厚みは、概ね
モジュール基板１とプリント基板７の厚みの合計とな
り、半導体チップおよび他の部品の厚みは全体高さには
影響しない。By adopting the mounting structure described above, if the thickness of the semiconductor chip 4 and the other components 5 is smaller than the thickness of the printed board 7, the total thickness of the mounting is substantially equal to the module board 1 and the printed board 7 And the thickness of the semiconductor chip and other components does not affect the overall height.
【００１３】次に、図２（ａ）〜（ｄ）を参照して本発
明の半導体チップの実装方法について工程順に説明す
る。Next, a method for mounting a semiconductor chip according to the present invention will be described in the order of steps with reference to FIGS. 2 (a) to 2 (d).
【００１４】先ず、図２（ａ）に示すように、モジュー
ル基板１上に部品を搭載するためのバンプ（Ａ）２およ
びバンプ（Ｂ）３を形成する。このバンプ作成方法とし
ては、ワイヤーボンディング装置および金線を使用した
スタッドバンプボンディング等の方法を用いる。First, as shown in FIG. 2A, bumps (A) 2 and bumps (B) 3 for mounting components are formed on a module substrate 1. As a method of forming the bump, a method such as a stud bump bonding using a wire bonding apparatus and a gold wire is used.
【００１５】次に、図２（ｂ）に示すように、バンプ
（Ａ）２に銀ペースト等の導電性接着剤を塗布した後、
半導体チップ４および他の部品５を搭載しベーキングを
行い電気的に接続する。この状態においてモジュール
は、電気特性試験が可能となる。したがって、この状態
にてモジュール単体の電気特性試験を実施し不良品を除
去することができる。Next, as shown in FIG. 2B, after applying a conductive adhesive such as a silver paste to the bump (A) 2,
The semiconductor chip 4 and other components 5 are mounted, baked, and electrically connected. In this state, the module can perform an electrical property test. Therefore, in this state, an electrical characteristic test of the module alone can be performed to remove defective products.
【００１６】次に、図２（ｃ）に示すように、プリント
基板７のくり抜き部８が半導体チップ４および他の部品
５の位置に対応するようにして、プリント基板７をバン
プ（Ｂ）３上に搭載する。そしてバンプ（Ｂ）３を介し
モジュール基板１とプリント基板７を電気的に接続す
る。半導体チップ４等の部品厚みが０．４ｍｍ程度の場
合プリント基板７の厚みを０．５ｍｍ程度とすることに
より、部品厚み０．４ｍｍはプリント基板７よりも薄く
なり実装高さに影響しないようにすることができる。Next, as shown in FIG. 2C, the printed board 7 is moved to the bumps (B) 3 so that the hollow portions 8 of the printed board 7 correspond to the positions of the semiconductor chip 4 and other components 5. Mount on top. Then, the module board 1 and the printed board 7 are electrically connected via the bumps (B) 3. When the thickness of the component such as the semiconductor chip 4 is about 0.4 mm, the thickness of the printed board 7 is set to about 0.5 mm so that the component thickness 0.4 mm is thinner than the printed board 7 so as not to affect the mounting height. can do.
【００１７】次に、図２（ｄ）に示すように、くり抜き
部８から封止樹脂６をモジュール基板１とプリント基板
７間に充填する。こうして半導体チップ４等を外部環境
から保護する。Next, as shown in FIG. 2D, the sealing resin 6 is filled between the module substrate 1 and the printed substrate 7 from the hollow portion 8. Thus, the semiconductor chip 4 and the like are protected from the external environment.
【００１８】このように、本発明の半導体チップの実装
方法は、モジュール基板上に半導体チップ等の部品を搭
載し、この搭載位置に対応した部分をくり抜いたプリン
ト基板と組み合せて実装するので、装置全体の薄型化、
小型化が可能となる。As described above, according to the method of mounting a semiconductor chip of the present invention, components such as a semiconductor chip are mounted on a module substrate, and a part corresponding to the mounting position is mounted in combination with a printed circuit board. Overall thinning,
The size can be reduced.
【００１９】次に、第２の実施の形態について説明す
る。Next, a second embodiment will be described.
【００２０】図３は、本発明の第２の実施形態例を示す
断面図である。図３に示すように、モジュールの基板を
シリコン基板２１とすることにより配線の微細化が可能
となる。ガラスエポキシ等を使用したプリント基板２７
の最小配線ピッチは５０〜１００μｍ程度であるが、シ
リコン基板２１を使用することにより最小配線ピッチは
２〜３μｍ以下が可能となる。したがってシリコン基板
２１を使用することにより配線ピッチが１／１０以下と
なるので、配線の微細化が可能となり、モジュールの小
型化が可能となる。FIG. 3 is a sectional view showing a second embodiment of the present invention. As shown in FIG. 3, by using a silicon substrate 21 as the substrate of the module, miniaturization of wiring becomes possible. Printed circuit board 27 using glass epoxy etc.
Is about 50 to 100 μm, but the use of the silicon substrate 21 allows the minimum wiring pitch to be 2 to 3 μm or less. Therefore, since the wiring pitch is reduced to 1/10 or less by using the silicon substrate 21, the wiring can be miniaturized, and the module can be downsized.
【００２１】さらにモジュールの基板としてシリコン基
板２１を使用すれば、シリコン基板２１に抵抗、コンデ
ンサ、ダイオードおよびトランジスタなどの素子を内蔵
することも可能となる。それにより、シリコン基板２１
上に後から搭載する他の部品点数を削減することが可能
となる。したがって、モジュールの小型化と接続点数の
削減が可能となるのでモジュールの信頼性を向上させる
ことができる。またバンプ（Ｄ）２３を設置して置くこ
とにより、シリコン基板２１に内蔵した抵抗、コンデン
サ、ダイオードおよびトランジスタなどの素子をプリン
ト基板２７に直接、電気的に接続することが可能とな
る。Further, if the silicon substrate 21 is used as the module substrate, it is possible to incorporate elements such as a resistor, a capacitor, a diode, and a transistor in the silicon substrate 21. Thereby, the silicon substrate 21
It becomes possible to reduce the number of other components to be mounted later on the top. Therefore, the module can be reduced in size and the number of connection points can be reduced, so that the reliability of the module can be improved. Further, by installing and placing the bump (D) 23, it becomes possible to directly electrically connect elements such as a resistor, a capacitor, a diode, and a transistor built in the silicon substrate 21 to the printed circuit board 27.
【００２２】次に、第３の実施の形態について説明す
る。Next, a third embodiment will be described.
【００２３】図４は、本発明の第３の実施形態例を示す
断面図である。上述の図１から図３までに示した半導体
チップの搭載方法については、フリップチップによる実
装方法を説明したが、本発明は、フリップチップによる
と限定するものではない。図４に示すようにマウント剤
４２にてマウントした後、ボンディングワイヤ４３にて
半導体チップ４４とモジュール基板４１間を接続するチ
ップ オン ボード（ＣＯＢ）を使用しても可能であ
る。FIG. 4 is a sectional view showing a third embodiment of the present invention. As for the mounting method of the semiconductor chip shown in FIGS. 1 to 3 described above, the mounting method using the flip chip has been described, but the present invention is not limited to the flip chip. As shown in FIG. 4, it is also possible to use a chip-on-board (COB) for connecting the semiconductor chip 44 and the module substrate 41 with the bonding wires 43 after mounting with the mounting agent 42.
【００２４】[0024]
【発明の効果】以上説明したように本発明は、モジュー
ル基板上の部品搭載位置に対応したプリント基板の部分
を該基板面に垂直にくり抜き、モジュールをプリント基
板に電気的に接続し、モジュール基板とプリント基板間
の隙間を封止樹脂で充填すること等により、装置全体の
薄型化、小型化およびコストダウンを可能とした半導体
チップの実装方法を提供できる効果がある。As described above, according to the present invention, a portion of a printed board corresponding to a component mounting position on a module board is cut out perpendicularly to the board surface, and the module is electrically connected to the printed board. By filling the gap between the semiconductor device and the printed board with a sealing resin, it is possible to provide a method of mounting a semiconductor chip that enables the overall device to be thinner, smaller, and lower in cost.
【図１】本発明の半導体チップ等の部品の実装方法の一
実施形態例を示す断面図である。FIG. 1 is a cross-sectional view showing one embodiment of a method for mounting a component such as a semiconductor chip of the present invention.
【図２】（ａ），（ｂ），（ｃ），（ｄ）は、本実施形
態例を各工程順に示す断面図である。FIGS. 2A, 2B, 2C, and 2D are cross-sectional views showing the embodiment in the order of steps.
【図３】本発明の第２の実施形態例を示す断面図であ
る。FIG. 3 is a sectional view showing a second embodiment of the present invention.
【図４】本発明の第３の実施形態例を示す断面図であ
る。FIG. 4 is a sectional view showing a third embodiment of the present invention.
【図５】従来の半導体チップ等の実装方法の一例を示す
断面図である。FIG. 5 is a cross-sectional view illustrating an example of a conventional method for mounting a semiconductor chip or the like.
１，４１，６１ モジュール基板 ２ バンプ（Ａ） ３ バンプ（Ｂ） ４，２４，４４，６４ 半導体チップ ５，２５，４５，６５ 他の部品 ６，２６，４６，６６ 封止樹脂 ７，２７，４７，６７ プリント基板 ８ くり抜き部 ２１ シリコン基板 ２２ バンプ（Ｃ） ２３ バンプ（Ｄ） ４２，６２ マウント剤 ４３，６３ ボンディングワイヤ ４８ バンプ（Ｅ） ６８ 半田 ６９ リード 1, 41, 61 Module substrate 2 Bump (A) 3 Bump (B) 4, 24, 44, 64 Semiconductor chip 5, 25, 45, 65 Other components 6, 26, 46, 66 Sealing resin 7, 27, 47, 67 Printed circuit board 8 Cut-out section 21 Silicon substrate 22 Bump (C) 23 Bump (D) 42, 62 Mounting agent 43, 63 Bonding wire 48 Bump (E) 68 Solder 69 Lead
Claims (2)
ジュール基板上に搭載され、かつこれら部品が前記モジ
ュール基板と電気的に接続されて成るモジュールをプリ
ント基板に実装する、半導体チップの実装方法におい
て、 前記モジュール基板上の前記部品搭載位置に対応した前
記プリント基板の部分を該基板面に垂直にくり抜き、 前記モジュールと前記プリント基板とを電気的に接続
し、 前記モジュール基板と前記プリント基板間の隙間を封止
樹脂で充填する、ことを特徴とする半導体チップの実装
方法。1. A method for mounting a semiconductor chip, comprising: mounting a component including at least a semiconductor chip on a module substrate; and mounting a module formed by electrically connecting the component to the module substrate on a printed circuit board. A portion of the printed circuit board corresponding to the component mounting position on the module board is cut out perpendicularly to the board surface, and the module and the printed board are electrically connected, and a gap between the module board and the printed board is formed. A method for mounting a semiconductor chip, comprising filling with a sealing resin.
が、半導体チップのほか、抵抗、コンデンサ、ダイオー
ド及びトランジスタである、請求項１記載の半導体チッ
プの実装方法。2. The method of mounting a semiconductor chip according to claim 1, wherein the components mounted on the module substrate are, in addition to the semiconductor chip, a resistor, a capacitor, a diode, and a transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8109250A JP2809191B2 (en) | 1996-04-30 | 1996-04-30 | Semiconductor chip mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8109250A JP2809191B2 (en) | 1996-04-30 | 1996-04-30 | Semiconductor chip mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09298274A JPH09298274A (en) | 1997-11-18 |
| JP2809191B2 true JP2809191B2 (en) | 1998-10-08 |
Family
ID=14505424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8109250A Expired - Fee Related JP2809191B2 (en) | 1996-04-30 | 1996-04-30 | Semiconductor chip mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2809191B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000165007A (en) | 1998-11-27 | 2000-06-16 | Nec Corp | Printed circuit board, electronic component and its mounting method |
| US6617681B1 (en) * | 1999-06-28 | 2003-09-09 | Intel Corporation | Interposer and method of making same |
-
1996
- 1996-04-30 JP JP8109250A patent/JP2809191B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09298274A (en) | 1997-11-18 |
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