JPS5834764U - hybrid integrated circuit - Google Patents
hybrid integrated circuitInfo
- Publication number
- JPS5834764U JPS5834764U JP12917181U JP12917181U JPS5834764U JP S5834764 U JPS5834764 U JP S5834764U JP 12917181 U JP12917181 U JP 12917181U JP 12917181 U JP12917181 U JP 12917181U JP S5834764 U JPS5834764 U JP S5834764U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- silicon wafer
- thin film
- film resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Semiconductor Integrated Circuits (AREA)
- Networks Using Active Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は多重帰還形帯域通過フィルタの回路例、第2図
は状態変数形帯域通過フィルタの回路例、第3図は第2
図の回路を持った従来の状態変数形帯域通過フィルタの
ハイブリッドICの構成図、第4図は第3図と同一回路
の本考案のハイブリッドICの構成図、第5図は従来の
薄膜抵抗アレイチップの断面図、第6図Aは本考案の半
導体ICと薄膜抵抗アレイを搭載したチップの断面図、
第6図BはAの回路の一部である。Figure 1 is a circuit example of a multiple feedback type bandpass filter, Figure 2 is a circuit example of a state variable type bandpass filter, and Figure 3 is a circuit example of a state variable type bandpass filter.
Figure 4 is a block diagram of a hybrid IC of the present invention having the same circuit as Figure 3, and Figure 5 is a diagram of a conventional thin film resistor array. A cross-sectional view of a chip, FIG. 6A is a cross-sectional view of a chip equipped with a semiconductor IC of the present invention and a thin film resistor array;
FIG. 6B is a part of the circuit of A.
Claims (1)
、積層コンデンサ及び外部接続端子などをプリント配線
基板又はセラミック基板上に作成した導体回路、抵抗回
路と接続して構成するノ1イブリッド集積回路において
、前記半導体集積回路と前記シリコンウェハ上に作成し
た薄膜抵抗とを同一のシリコンウェハ上に作成し、前記
積層コンデンサ及び外部接続端子などと共に前記の基板
に搭載したことを特徴とするハイブリッド集積回路。No. 1 hybrid integrated circuit configured by connecting a semiconductor integrated circuit, a thin film resistor formed on a silicon wafer, a multilayer capacitor, an external connection terminal, etc. to a conductive circuit or a resistance circuit formed on a printed wiring board or a ceramic substrate; A hybrid integrated circuit characterized in that a semiconductor integrated circuit and a thin film resistor formed on the silicon wafer are formed on the same silicon wafer, and are mounted on the substrate together with the multilayer capacitor, external connection terminals, etc.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12917181U JPS5834764U (en) | 1981-08-31 | 1981-08-31 | hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12917181U JPS5834764U (en) | 1981-08-31 | 1981-08-31 | hybrid integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5834764U true JPS5834764U (en) | 1983-03-07 |
Family
ID=29922845
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12917181U Pending JPS5834764U (en) | 1981-08-31 | 1981-08-31 | hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5834764U (en) |
-
1981
- 1981-08-31 JP JP12917181U patent/JPS5834764U/en active Pending
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