JP2977049B2 - Electronic functional circuit device for surface mounting - Google Patents

Electronic functional circuit device for surface mounting

Info

Publication number
JP2977049B2
JP2977049B2 JP3053556A JP5355691A JP2977049B2 JP 2977049 B2 JP2977049 B2 JP 2977049B2 JP 3053556 A JP3053556 A JP 3053556A JP 5355691 A JP5355691 A JP 5355691A JP 2977049 B2 JP2977049 B2 JP 2977049B2
Authority
JP
Japan
Prior art keywords
ceramic capacitor
multilayer ceramic
capacitor
functional circuit
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3053556A
Other languages
Japanese (ja)
Other versions
JPH05183066A (en
Inventor
徹 須藤
三樹男 高野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GOYO DENSHI KOGYO KK
Kokusai Electric Corp
Original Assignee
GOYO DENSHI KOGYO KK
Kokusai Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GOYO DENSHI KOGYO KK, Kokusai Electric Corp filed Critical GOYO DENSHI KOGYO KK
Priority to JP3053556A priority Critical patent/JP2977049B2/en
Publication of JPH05183066A publication Critical patent/JPH05183066A/en
Application granted granted Critical
Publication of JP2977049B2 publication Critical patent/JP2977049B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Ceramic Capacitors (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、通信機,電子機器等に
用いられ、その電子回路の一部を機能回路として集積す
る電子機能回路装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic functional circuit device used for a communication device, an electronic device, etc. and integrating a part of the electronic circuit as a functional circuit.

【0002】[0002]

【従来の技術】電子機器の小形化が進むにつれて内部電
子回路の集積度が高くなり数々の工夫がなされている。
図2は従来の電子機能回路装置の構造例図であり、
(A)は縦断面図を示し、(B)はケース5を外した内
部構造例を示す斜視図である。図において、1は半導体
実装部品、2は抵抗コンデンサ複合部品、12は角形チ
ップ部品である。これらを面実装した回路基板3は外部
接続用ガラスハーメチックピンを有する金属ベース4に
取付けられ金属ケース5によって気密封止されている。
2. Description of the Related Art As the size of electronic devices has been reduced, the degree of integration of internal electronic circuits has been increased, and various efforts have been made.
FIG. 2 is a structural example diagram of a conventional electronic functional circuit device,
(A) is a longitudinal sectional view, and (B) is a perspective view showing an example of an internal structure with a case 5 removed. In the figure, 1 is a semiconductor mounted component, 2 is a resistor / capacitor composite component, and 12 is a square chip component. The circuit board 3 on which these are mounted is mounted on a metal base 4 having glass hermetic pins for external connection, and hermetically sealed by a metal case 5.

【0003】図3は図2の半導体実装部品1の詳細を示
す構造例図であり、(A)は縦断面図を示し、(B)は
そのキャップ7を外した内部構造を示す斜視図である。
図において、6は中央縦断面が凹状の有底無蓋箱形のセ
ラミック多層基板であり、その内部底面に半導体ベアチ
ップ14が金またはアルミの細線15によってワイヤボ
ンディングされている。8は金属枠体であり、セラミッ
ク多層基板6の周囲頂部に銀ろうなどのろう剤9によっ
てろう付けされている。7は金属キャップであり、金属
枠体8の上面に抵抗溶接などによって接合されて内部空
間が形成されている。半導体ベアチップ14は、このよ
うにして形成された内部空間によってその細線の保護と
対環境保護のために気密封止されている。(A)に示し
たセラミック基板6の周縁の黒い太線部分は配線導体部
分であり、底面両側部分は図2の回路基板3に面実装す
る際の電極となる。図4は図2の抵抗コンデンサ複合部
品2の詳細を示す構造例図であり、(A)は縦断面図を
示し(B)はその斜視図である。図において、10は積
層セラミックコンデンサ、11はその上面に設けられた
印刷抵抗体、13は抵抗体11とその導体配線を保護す
るためのオーバガラスである。(A)の積層セラミック
コンデンサ10の太線部分は各層のコンデンサの電極及
び導体配線部分を示す。その底面の両端部分は図2の回
路基板3に面実装する際の電極となる。
FIG. 3 is a structural example showing the details of the semiconductor mounted component 1 of FIG. 2, (A) is a longitudinal sectional view, and (B) is a perspective view showing the internal structure with the cap 7 removed. is there.
In the figure, reference numeral 6 denotes a closed bottomed box-shaped ceramic multilayer substrate having a concave central longitudinal section, and a semiconductor bare chip 14 is wire-bonded to the inner bottom surface thereof by a thin wire 15 of gold or aluminum. Reference numeral 8 denotes a metal frame, which is brazed to the peripheral top of the ceramic multilayer substrate 6 with a brazing agent 9 such as silver brazing. Reference numeral 7 denotes a metal cap, which is joined to the upper surface of the metal frame 8 by resistance welding or the like to form an internal space. The semiconductor bare chip 14 is hermetically sealed by the internal space formed in this way to protect its fine wires and protect the environment. A black thick line portion on the periphery of the ceramic substrate 6 shown in (A) is a wiring conductor portion, and both side portions on the bottom surface are electrodes for surface mounting on the circuit board 3 in FIG. FIGS. 4A and 4B are structural example views showing details of the resistance / capacitor composite component 2 of FIG. 2, in which FIG. 4A is a longitudinal sectional view and FIG. In the drawing, 10 is a multilayer ceramic capacitor, 11 is a printed resistor provided on the upper surface thereof, and 13 is an over-glass for protecting the resistor 11 and its conductor wiring. The bold line portions of the multilayer ceramic capacitor 10 in (A) show the electrode and conductor wiring portions of the capacitors in each layer. Both ends of the bottom surface become electrodes when surface-mounted on the circuit board 3 of FIG.

【0004】[0004]

【発明が解決しようとする課題】このような従来の構造
では次のような問題点がある。 (イ)半導体実装部品1と抵抗コンデンサ複合部品2及
びその他の角形チップ部品12を一旦回路基板3に面実
装した後さらに金属ベース4に取付けケース5によって
パッケージする組立て構成のため、構成部品点数が多く
小形化,コストダウンに限界がある。 (ロ)半導体ベアチップは、面実装用のセラミックまた
はモールドパッケージに実装され、さらに他の部品と共
に組立てられてもう一度気密封止されるので2重パッケ
ージング構成となり、そのための材料や加工のための費
用がかかるばかりでなく組立て時間がかかる。 本発明の目的は、上述のような問題点を解決し組立工程
と部品点数を削減した面実装用電子機能回路装置を提供
することにある。
However, such a conventional structure has the following problems. (A) Since the semiconductor mounting component 1, the resistor / capacitor composite component 2 and the other rectangular chip components 12 are once surface-mounted on the circuit board 3 and then packaged on the metal base 4 by the mounting case 5, the number of component parts is small There are many limitations in miniaturization and cost reduction. (B) A semiconductor bare chip is mounted on a ceramic or mold package for surface mounting, assembled with other components, and hermetically sealed once again, so that a double packaging configuration is obtained, and materials and processing costs for the packaging are required. Not only takes time, but also takes time to assemble. An object of the present invention is to provide an electronic functional circuit device for surface mounting which solves the above-mentioned problems and reduces the number of assembly steps and the number of components.

【0005】[0005]

【課題を解決するための手段】本発明の面実装用電子機
能回路装置は、側面導体によって各層のコンデンサ電極
が接続され上面及び底面が平坦な積層セラミックコンデ
ンサと、該積層セラミックコンデンサの前記上面の導体
電極に取付けられた少なくとも1つの半導体チップと、
該半導体チップを保護するための空間部分を設けるため
前記積層セラミックコンデンサの前記上面に取付けられ
た金属枠体と、該枠体の上面に前記空間部分を封止する
ために接合された金属キャップと、前記積層セラミック
コンデンサの前記底面に設けられた少なくとも1つの印
刷抵抗体と、該印刷抵抗を保護するために被覆加工され
たオーバガラスと、前記積層セラミックコンデンサと前
記半導体チップと前記印刷抵抗体とが所定の回路接続と
なるように該積層セラミックコンデンサの表面に設けら
れた配線導体とを備えたことを特徴とするものである。
以下図面により本発明を詳細に説明する。
According to the present invention, there is provided an electronic functional circuit device for surface mounting, comprising: a multilayer ceramic capacitor having capacitor electrodes of each layer connected by side conductors and having a flat top and bottom; At least one semiconductor chip mounted on the conductor electrode;
A metal frame attached to the upper surface of the multilayer ceramic capacitor to provide a space for protecting the semiconductor chip; and a metal cap bonded to the upper surface of the frame to seal the space. At least one printed resistor provided on the bottom surface of the multilayer ceramic capacitor, over-glass coated to protect the printed resistor, the multilayer ceramic capacitor, the semiconductor chip, and the printed resistor. And a wiring conductor provided on the surface of the multilayer ceramic capacitor so as to provide a predetermined circuit connection.
Hereinafter, the present invention will be described in detail with reference to the drawings.

【0006】[0006]

【実施例】図1は本発明の実施例を示す構造図であり、
(A)は縦断面図を示し、(B)は外観を示す斜視図で
ある。図において、10は例えば16個程度の複数のコ
ンデンサネットワークを形成する積層セラミックコンデ
ンサ、14は半導体ベアチップ、15は細線、9はろう
剤、8はコバール等の金属枠体、7は金属キャップ、1
1は例えば16個程度の複数のRu O系厚膜による印刷
抵抗体、13はオーバガラスである。(A)に示す積層
コンデンサ10の断面及び周縁部の太線部分はコンデン
サ電極と配線導体部分を示し、その側面部分16は積層
された各層のコンデンサ電極の接続配線と外部回路への
接続用電極である。図1の実施例では1つの半導体ベア
チップの例を示しているが複数個の半導体ベアチップま
たはフリップチップ半導体が実装される。上述の構成例
のように、本発明の構成は、積層セラミックコンデンサ
10の上面に少なくとも1つの半導体ベアチップまたは
フリップチップ14を直接実装封止し、底面に印刷抵抗
体13を設けることにより、従来の半導体チップの2重
封止を回避するとともに他のチップ部品を積層コンデン
サに直接実装することができる。そのため、従来の回路
基板と、全体を収容する金属ベースや金属ケースが不要
となり、それらを組立てる工程も不要となる。さらに、
全体の装置を電子機器の基板に面実装することができ
る。
FIG. 1 is a structural view showing an embodiment of the present invention.
(A) shows a longitudinal cross-sectional view, and (B) is a perspective view showing an appearance. In the figure, reference numeral 10 denotes a multilayer ceramic capacitor forming a plurality of, for example, about 16 capacitor networks, 14 denotes a semiconductor bare chip, 15 denotes a thin wire, 9 denotes a brazing agent, 8 denotes a metal frame such as Kovar, 7 denotes a metal cap,
1 print resistor of a plurality of R u O thick film of, for example, about 16, 13 is over the glass. A thick line portion of the cross section and the peripheral portion of the multilayer capacitor 10 shown in FIG. 1A shows a capacitor electrode and a wiring conductor portion, and a side portion 16 thereof is a connection wiring of the capacitor electrode of each laminated layer and a connection electrode to an external circuit. is there. Although the embodiment of FIG. 1 shows an example of one semiconductor bare chip, a plurality of semiconductor bare chips or flip chip semiconductors are mounted. As in the above configuration example, the configuration of the present invention is achieved by directly mounting and sealing at least one semiconductor bare chip or flip chip 14 on the upper surface of the multilayer ceramic capacitor 10 and providing the printed resistor 13 on the bottom surface. The double sealing of the semiconductor chip can be avoided, and another chip component can be directly mounted on the multilayer capacitor. Therefore, a conventional circuit board, a metal base and a metal case that house the entire circuit board are not required, and a process of assembling them is not required. further,
The entire device can be surface-mounted on a substrate of an electronic device.

【0007】[0007]

【発明の効果】以上詳細に説明したように、本発明を実
施することにより従来の機能回路装置と同じ機能を有し
ながら小形化,コストダウンに極めて大きい効果があ
り、電子機器の小形化,低価格化に大きく寄与すること
ができる。
As described above in detail, by implementing the present invention, it is possible to reduce the size and cost of the electronic device while having the same functions as the conventional functional circuit device. This can greatly contribute to lower prices.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例を示す構造図である。FIG. 1 is a structural diagram showing an embodiment of the present invention.

【図2】従来の構造例図である。FIG. 2 is a diagram showing an example of a conventional structure.

【図3】従来の半導体実装部品の構造例図である。FIG. 3 is a structural example diagram of a conventional semiconductor mounting component.

【図4】従来の抵抗コンデンサ複合部品の構造例図であ
る。
FIG. 4 is a structural example diagram of a conventional resistance / capacitor composite part.

【符号の説明】[Explanation of symbols]

1 半導体実装部品 2 抵抗コンデンサ複合部品 3 回路基板 4 金属ベース 5 金属ケース 6 セラミック多層基板 7 金属キャップ 8 金属枠体 9 ろう 10 積層セラミックコンデンサ 11 抵抗体 12 角形チップ部品 13 オーバガラス 14 半導体チップ 15 細線 16 側面電極 DESCRIPTION OF SYMBOLS 1 Semiconductor mounting component 2 Resistive capacitor composite component 3 Circuit board 4 Metal base 5 Metal case 6 Ceramic multilayer substrate 7 Metal cap 8 Metal frame 9 Wax 10 Multilayer ceramic capacitor 11 Resistor 12 Square chip component 13 Over glass 14 Semiconductor chip 15 Fine wire 16 Side electrode

フロントページの続き (56)参考文献 特開 昭58−225627(JP,A) (58)調査した分野(Int.Cl.6,DB名) H01L 23/12 Continuation of the front page (56) References JP-A-58-225627 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 23/12

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 側面導体によって各層のコンデンサ電極
が接続され上面及び底面が平坦な積層セラミックコンデ
ンサと、 該積層セラミックコンデンサの前記上面の導体電極に取
付けられた少なくとも1つの半導体チップと、 該半導体チップを保護するための空間部分を設けるため
前記積層セラミックコンデンサの前記上面に取付けられ
た金属枠体と、 該枠体の上面に前記空間部分を封止するために接合され
た金属キャップと、 前記積層セラミックコンデンサの前記底面に設けられた
少なくとも1つの印刷抵抗体と、 該印刷抵抗を保護するために被覆加工されたオーバガラ
スと、 前記積層セラミックコンデンサと前記半導体チップと前
記印刷抵抗体とが所定の回路接続となるように該積層セ
ラミックコンデンサの表面に設けられた配線導体とを備
えた面実装用電子機能回路装置。
1. A multilayer ceramic capacitor in which capacitor electrodes of each layer are connected by side conductors and whose top and bottom surfaces are flat, at least one semiconductor chip attached to the conductor electrode on the top surface of the multilayer ceramic capacitor, and the semiconductor chip A metal frame attached to the upper surface of the multilayer ceramic capacitor to provide a space for protecting the multilayer ceramic capacitor; a metal cap joined to the upper surface of the frame to seal the space; At least one printed resistor provided on the bottom surface of the ceramic capacitor; an over-glass coated to protect the printed resistor; and the multilayer ceramic capacitor, the semiconductor chip, and the printed resistor being a predetermined one A wiring conductor provided on the surface of the multilayer ceramic capacitor so as to form a circuit connection; Electronic functional circuit device for surface mounting, comprising:
JP3053556A 1991-02-27 1991-02-27 Electronic functional circuit device for surface mounting Expired - Fee Related JP2977049B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3053556A JP2977049B2 (en) 1991-02-27 1991-02-27 Electronic functional circuit device for surface mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3053556A JP2977049B2 (en) 1991-02-27 1991-02-27 Electronic functional circuit device for surface mounting

Publications (2)

Publication Number Publication Date
JPH05183066A JPH05183066A (en) 1993-07-23
JP2977049B2 true JP2977049B2 (en) 1999-11-10

Family

ID=12946083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3053556A Expired - Fee Related JP2977049B2 (en) 1991-02-27 1991-02-27 Electronic functional circuit device for surface mounting

Country Status (1)

Country Link
JP (1) JP2977049B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19713052A1 (en) * 1997-03-27 1998-10-01 Siemens Ag Capacitor structure
JP3780503B2 (en) * 2002-01-21 2006-05-31 京セラ株式会社 Wiring board
CN103828038B (en) 2011-07-25 2016-07-06 京瓷株式会社 Circuit board, electronic installation and electronic module
US9704791B2 (en) 2013-10-23 2017-07-11 Kyocera Corporation Wiring board and electronic device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5966356U (en) * 1982-10-25 1984-05-04 セイコーエプソン株式会社 Electric razor motor fixing structure
JPH0163849U (en) * 1987-10-20 1989-04-24

Also Published As

Publication number Publication date
JPH05183066A (en) 1993-07-23

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