JPH0457357A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPH0457357A JPH0457357A JP2166714A JP16671490A JPH0457357A JP H0457357 A JPH0457357 A JP H0457357A JP 2166714 A JP2166714 A JP 2166714A JP 16671490 A JP16671490 A JP 16671490A JP H0457357 A JPH0457357 A JP H0457357A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit device
- semiconductor element
- external lead
- electric circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000011347 resin Substances 0.000 description 11
- 229920005989 resin Polymers 0.000 description 11
- 239000000919 ceramic Substances 0.000 description 7
- 238000007789 sealing Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- ORQBXQOJMQIAOY-UHFFFAOYSA-N nobelium Chemical compound [No] ORQBXQOJMQIAOY-UHFFFAOYSA-N 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、電子内視鏡の先端部などの微小部分に実装
可能な超小型の集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an ultra-small integrated circuit device that can be mounted in a minute part such as the tip of an electronic endoscope.
従来、半導体素子等の電気回路素子はチップの保護、配
線基板への搭載等の目的で、種々の方法でパッケージに
気密に封止されている。第5図八は、その−例を示す断
面図で、基板101に半導体素子102や受動チップ部
品103を取り付けて金属フレーム104上に接着し、
外部リード105と基板101とのリードボンディング
を行ったのち、樹脂モールド106で気密封止して集積
回路装置を構成している。Conventionally, electric circuit elements such as semiconductor elements have been hermetically sealed in packages using various methods for the purpose of protecting the chip, mounting it on a wiring board, etc. FIG. 58 is a cross-sectional view showing an example of this, in which a semiconductor element 102 and a passive chip component 103 are attached to a substrate 101 and bonded onto a metal frame 104.
After lead bonding is performed between the external leads 105 and the substrate 101, the integrated circuit device is hermetically sealed with a resin mold 106.
また第5図旧)に示すように、セラミンクパッケージ1
10に半導体素子111を接着しセラミックパッケージ
110の配線部とポンディングワイヤ112で接続した
のち、ガラス板113を載置して樹脂114七封止し、
セラミックパッケージ110の下面に設けられた外部
リード115に、予め半導体素子等の電気回路素子を搭
載し封止した基板116をハンダ付は部117により接
続して構成したものが提案されている。Also, as shown in Figure 5 (old), the ceramic package 1
After bonding the semiconductor element 111 to the ceramic package 10 and connecting it to the wiring part of the ceramic package 110 with a bonding wire 112, a glass plate 113 is placed and sealed with resin 114.
A structure has been proposed in which a substrate 116 on which an electric circuit element such as a semiconductor element is previously mounted and sealed is connected to an external lead 115 provided on the lower surface of the ceramic package 110 through a soldered part 117.
〔発明が解決しようとする課B]
しかしながら、第5図式に示した構成のものは、基板1
01上に半導体素子102及びチップ部品103を搭載
しているため、集積回路装置の輻Wが大きくなり面積が
太き(なってしまい、電子内視鏡の先端部のような微小
部分への実装は困難である。[Problem B to be solved by the invention] However, in the configuration shown in the fifth diagram, the substrate 1
Since the semiconductor element 102 and the chip component 103 are mounted on the integrated circuit device 01, the radiation W of the integrated circuit device becomes large and the area becomes large. It is difficult.
方、第5図田)に示した構成のものは、幅Wは小さくな
り面積を小さくすることはできるけれども、セラミック
パッケージ110の外部リード115と基板116との
接続のためのスペースが必要であって小型化に限界があ
り、その接続スペースを小さくしようとすると、接続が
困難となって工数が増加し生産性が低下するという問題
点が生ずる。On the other hand, although the configuration shown in Fig. 5) has a smaller width W and can reduce the area, it requires space for connection between the external leads 115 of the ceramic package 110 and the substrate 116. There is a limit to miniaturization, and if the connection space is made smaller, the problem arises that connection becomes difficult, increases the number of man-hours, and reduces productivity.
本発明は、従来の集積回路装置の上記問題点を解消する
ためなされたもので、面積の縮小化を計ると共に接続の
ためのスペースを必要とせず、簡単な構成で低コストの
超小型の集積回路装置を提供することを目的とする。The present invention has been made to solve the above-mentioned problems of conventional integrated circuit devices, and is an ultra-compact integrated circuit that reduces the area, does not require space for connections, has a simple configuration, and is low-cost. The purpose is to provide a circuit device.
〔課題を解決するための手段及び作用]上記問題点を解
決するため、本発明は外部リード部を備えたパンケージ
に半導体素子を実装してなる集積回路装置において、前
記外部リード部を配線パターン状に構成し、該外部リー
ド部に半導体素子、チップ部品等の電気回路素子を搭載
して電気的に接続し気密封止するものである。[Means and effects for solving the problems] In order to solve the above-mentioned problems, the present invention provides an integrated circuit device in which a semiconductor element is mounted on a pan cage provided with an external lead portion, in which the external lead portion is shaped like a wiring pattern. An electric circuit element such as a semiconductor element or a chip component is mounted on the external lead portion, electrically connected, and hermetically sealed.
このように構成することにより、外部リード部に半導体
素子やチップ部品等の電気回路素子が搭載されているた
め、集積回路装置の幅を小さくし、面積の縮小化を計る
ことができ、また外部リード部への基板の接続が行われ
ないため接続用のスペースを必要とせず、低コストで簡
単な構成の超小型の集積回路装置を実現することができ
る。With this configuration, electrical circuit elements such as semiconductor elements and chip components are mounted on the external lead part, so the width and area of the integrated circuit device can be reduced, and the external Since the board is not connected to the lead portion, no space for connection is required, and an ultra-small integrated circuit device with a simple configuration can be realized at low cost.
[実施例]
次に実施例について説明する。第1図へは、本発明に係
る集積回路装置の第1の実施例を示す断面図である。1
は側面に外部リード部2を接続したセラミック等からな
るパッケージで、外部リード部2は第1図旧)に示すよ
うに、配線パターン状に形成されており、先端には共通
接続部2aが設けられている。パンケージ1には、半導
体素子3を共晶、樹脂ペーストハンダ等により接着し、
次いでAu、 AIなどのボンディングワイヤ4により
半導体素子3とパッケージ1の配線部との間を接続し、
低融点ガラスあるいは樹脂等によりキャップ5をパッケ
ージ1に接着し、半導体素子3をパッケージ1内に封止
する。次いでパッケージ1の外部リード部2に半導体素
子6をダイボンドしてボンディングワイヤ7で接続し樹
脂8で封止し、更に抵抗、コンデンサ等のチップ部品9
と搭載する。そして外部リード部2の先端共通接続部2
aを切断除去して集積回路装置を完成する。[Example] Next, an example will be described. FIG. 1 is a sectional view showing a first embodiment of an integrated circuit device according to the present invention. 1
is a package made of ceramic or the like with an external lead part 2 connected to the side surface, and the external lead part 2 is formed in the shape of a wiring pattern, as shown in Figure 1 (old), and a common connection part 2a is provided at the tip. It is being A semiconductor element 3 is bonded to the pan cage 1 using eutectic, resin paste solder, etc.
Next, the semiconductor element 3 and the wiring part of the package 1 are connected by bonding wires 4 made of Au, AI, etc.
The cap 5 is bonded to the package 1 using low melting point glass or resin, and the semiconductor element 3 is sealed within the package 1. Next, a semiconductor element 6 is die-bonded to the external lead part 2 of the package 1, connected with bonding wires 7, sealed with resin 8, and further chip parts 9 such as resistors and capacitors are attached.
It is equipped with. And the common connection part 2 at the end of the external lead part 2
A is cut and removed to complete the integrated circuit device.
このように構成された集積回路装置においては、配線パ
ターン状に形成された外部リード部2に半導体素子6及
びチップ部品9を直接搭載し接続しているため、パッケ
ージ1と外部リード部2に搭載された半導体素子6及び
チップ部品9との接続の必要がなくなり、その接続のた
めのスペースも必要がないため、低コストで簡単な構成
の超小型化された集積回路装置が得られる。In the integrated circuit device configured in this way, the semiconductor element 6 and the chip component 9 are directly mounted and connected to the external lead part 2 formed in the shape of a wiring pattern, so that the semiconductor element 6 and the chip component 9 are directly mounted and connected to the package 1 and the external lead part 2. Since there is no need for connection between the semiconductor element 6 and the chip component 9, and there is no need for space for the connection, an ultra-miniaturized integrated circuit device with a simple configuration and low cost can be obtained.
第2図は、電子内視鏡の先端部などの微小部分に実装す
るため、更に面積を小さくした実施例を示す断面図であ
る。この実施例では、配線パターン状に形成した外部リ
ード部12をセラミックパッケージ11の下面から突出
するように設け、該外部リード部12に第1実施例と同
様に、半導体素子やチップ部品等の電気回路素子13を
搭載し、樹脂14等で封止して集積回路装置を構成する
ものである。FIG. 2 is a sectional view showing an embodiment in which the area is further reduced in order to be mounted in a minute part such as the tip of an electronic endoscope. In this embodiment, an external lead portion 12 formed in the shape of a wiring pattern is provided so as to protrude from the bottom surface of the ceramic package 11, and the external lead portion 12 is provided with an electrical conductor such as a semiconductor element or a chip component, as in the first embodiment. An integrated circuit device is constructed by mounting a circuit element 13 and sealing it with a resin 14 or the like.
なお第2図において、15は固体撮像素子等の半導体素
子、16はその上面に配置したガラス板又はカラーフィ
ルタであり、17は封止樹脂である。In FIG. 2, 15 is a semiconductor element such as a solid-state image sensor, 16 is a glass plate or color filter disposed on the top surface thereof, and 17 is a sealing resin.
このようにパッケージ11の下面より外部リード部12
を設けているため、集積回路装置の全体の幅がパッケー
ジ11の幅寸法より大にならず、また基板を用いていな
いので外部リードと基板との接続のためのスペースも必
要とせず、長さ方向でも短縮化が実現できる。したがっ
て電子内視鏡の先端部などの微小部分への実装に好適な
集積回路装置が得られる。In this way, the external lead portion 12 is
Since the integrated circuit device is provided with Shortening can also be achieved in the direction. Therefore, an integrated circuit device suitable for mounting in a minute part such as the tip of an electronic endoscope can be obtained.
第3図は、第3実施例を示す一部省略した断面図で、第
2図に示した第2実施例と同−又は同等の部材には同一
符号を付して示している。この実施例は、配線パターン
状外部リード部12の半導体素子やチップ部品等の電気
回路素子13を搭載する面と反対側の面に、リード補強
及び封止樹脂の流れ防止のために、側板18を接着して
設けたものである。側板18は絶縁性のものであれば何
れでも用いることができ、また導電性の側板でも絶縁処
理したものであれば用いることができる。FIG. 3 is a partially omitted sectional view showing the third embodiment, in which the same or equivalent members as those of the second embodiment shown in FIG. 2 are denoted by the same reference numerals. In this embodiment, a side plate 18 is provided on the surface of the wiring pattern external lead portion 12 opposite to the surface on which the electric circuit element 13 such as a semiconductor element or chip component is mounted, in order to reinforce the lead and prevent the sealing resin from flowing. It is attached by gluing. Any insulating side plate 18 can be used, and even conductive side plates can be used as long as they are insulated.
第4図は、第3図に示した実施例において、外部リード
部12に設けた半導体素子等の電気回路素子13の気密
封止を樹脂封止で行う代わりに、更に高倍転性を得るた
めに、キャップ19を電気回路素子13に被せ、低融点
ガラスで接着して封止するようにしたものである。FIG. 4 shows that in the embodiment shown in FIG. 3, instead of using resin sealing to hermetically seal the electric circuit element 13 such as a semiconductor element provided in the external lead part 12, a further high multiplier is obtained. In addition, a cap 19 is placed over the electric circuit element 13 and sealed with a low melting point glass.
[発明の効果〕
以上実施例に基づいて説明したように、本発明によれば
、外部リード部を配線パターン状に構成し、該外部リー
ド部を利用して半導体素子やチップ部品等の電気回路素
子を搭載したため、集積回路装置の幅を小さくして面積
の縮小化を計ることができる。また外部リード部へ直接
電気回路素子を搭載しているため、基板と外部リード部
との接続などを必要とせず、接続用のスペースも要せず
、簡単な構成で低コストの超小型集積回路装置を実現す
ることができる。[Effects of the Invention] As described above based on the embodiments, according to the present invention, the external lead portion is configured in the shape of a wiring pattern, and the external lead portion is used to connect an electric circuit such as a semiconductor element or a chip component. Since the elements are mounted, the width of the integrated circuit device can be reduced and the area can be reduced. In addition, since the electric circuit elements are mounted directly on the external lead part, there is no need to connect the board and the external lead part, and no space is required for connection, making it a simple and low-cost ultra-compact integrated circuit. The device can be realized.
第1図へは、本発明に係る集積回路装置の第1実施例を
示す断面図、第1図[3)は、第1実施例の電気回路素
子搭載前の外部リード部を示す側面図、第2図は、第2
実施例を示す断面図、第3図は、第3実施例の一部を省
略して示す断面図、第4図は、第4実施例の一部を省略
して示す断面図、第5図へ、田)は、従来の集積回路装
置の構成例を示す断面図である。
回において、1.11はパッケージ、2,12は外部リ
ード部、3.6は半導体素子、4.7はボンディングワ
イヤ、5はキャップ、8,14は封止樹脂、9はチップ
部品、13は電気回路素子、15は半導体素子、16は
ガラス板、17は封止樹脂、18は側板、19はキャッ
プを示す。
特許出願人 オリンパス光学工業株式会社第1図
(△)
第2図
第3図
第4図
(B)FIG. 1 is a sectional view showing the first embodiment of the integrated circuit device according to the present invention, FIG. 1 [3] is a side view showing the external lead part of the first embodiment before mounting the electric circuit element, Figure 2 shows the second
3 is a cross-sectional view showing the third embodiment with a part omitted; FIG. 4 is a cross-sectional view showing the fourth embodiment with a part omitted; FIG. FIG. 2 is a cross-sectional view showing an example of the configuration of a conventional integrated circuit device. 1.11 is a package, 2 and 12 are external lead parts, 3.6 is a semiconductor element, 4.7 is a bonding wire, 5 is a cap, 8 and 14 are sealing resins, 9 is a chip component, and 13 is a An electric circuit element, 15 a semiconductor element, 16 a glass plate, 17 a sealing resin, 18 a side plate, and 19 a cap. Patent applicant: Olympus Optical Industry Co., Ltd. Figure 1 (△) Figure 2 Figure 3 Figure 4 (B)
Claims (1)
装してなる集積回路装置において、前記外部リード部を
配線パターン状に構成し、該外部リード部に半導体素子
、チップ部品等の電気回路素子を搭載して電気的に接続
し気密封止したことを特徴とする集積回路装置。1. In an integrated circuit device in which a semiconductor element is mounted on a package provided with an external lead part, the external lead part is configured in the form of a wiring pattern, and an electric circuit element such as a semiconductor element or a chip component is mounted on the external lead part. An integrated circuit device characterized by being mounted, electrically connected, and hermetically sealed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2166714A JPH0457357A (en) | 1990-06-27 | 1990-06-27 | Integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2166714A JPH0457357A (en) | 1990-06-27 | 1990-06-27 | Integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0457357A true JPH0457357A (en) | 1992-02-25 |
Family
ID=15836400
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2166714A Pending JPH0457357A (en) | 1990-06-27 | 1990-06-27 | Integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0457357A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008112752A (en) * | 2006-10-27 | 2008-05-15 | Mitsubishi Heavy Ind Ltd | Semiconductor device, inspection instrument, manufacturing method of semiconductor device, and manufacturing method of chip |
-
1990
- 1990-06-27 JP JP2166714A patent/JPH0457357A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008112752A (en) * | 2006-10-27 | 2008-05-15 | Mitsubishi Heavy Ind Ltd | Semiconductor device, inspection instrument, manufacturing method of semiconductor device, and manufacturing method of chip |
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