JP2003086690A - High performance system on-chip using post passivation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high performance system on-chip using a post passivation method. SOLUTION: Electric elements of high quality (e.g. inductor, capacitor or resistor) are formed on a passivation layer 18 or a surface of a thick polymer layer 20. A method further provides a method for mounting a discrete electronic element in the state that the element is isolated from a surface of a lower silicon substrate 10 to some extent.

Description

Detailed Description of the Invention

This application is assigned to a common assignee in 1998
Filed on December 21, 2014, attorney docket MSLIN98-002,
A partial continuation application of U.S. Patent Application No. 09 / 216,791, 19
Filed on February 17, 1999, attorney docket MSLIN98-002
C. Attorney docket MEG00-filed on XX, XX, XX, which is a continuation-in-part of U.S. Patent Application No. 09 / 251,183.
008, a partial continuation application of US Patent Application No. XXXX.

[0002]

The present invention relates to high performance integrated circuits (I
It relates to the production of C), and more particularly to a method of producing high performance electrical components (eg inductors) on the surface of a semiconductor substrate by reducing the electromagnetic losses commonly experienced on the surface of the semiconductor substrate.

[0003]

BACKGROUND OF THE INVENTION In semiconductor technology, there is a constant focus on manufacturing semiconductor devices of improved performance at low cost. Over the years, these focused developments have resulted in the extreme miniaturization of semiconductor devices, made possible by the combination of semiconductor processes, the constant evolution of semiconductor materials, and high-performance new device designs. It was Most of the semiconductor devices manufactured today are intended for processing digital data. However, there are many semiconductor designs that aim to incorporate analog functionality in a device that processes digital and analog data simultaneously, or in a device that can be used to process only analog data. One of the major problems in manufacturing analog processing circuits (using digital processing procedures and equipment)
First, many of the devices used for analog circuits are large in size and are not easy to integrate into devices with feature sizes that are typically near the sub-micron range. The main elements that cause these problems are capacitors and inductors. This is because all of these elements are considerably large in size in the case of an ordinary analog processing circuit.

A general application of the inductor of the present invention is in the field of modern mobile communications applications which utilize compact high frequency devices. While continuous improvements have been achieved in the performance characteristics of this device over the years, it has been sought to reduce device power consumption, reduce device size, increase usable operating frequency, and reduce noise levels. The focus will be on further improvement. One of the main applications of semiconductor devices in the field of mobile communications is
Manufacture of radio frequency (RF) amplifiers. RF amplifiers include many standard components. A main element of a general RF amplifier is a tuning circuit including an inductive element and a capacitive element.
The tuned circuit depends on, and depends on, the values of the inductive and capacitive elements to form a frequency dependent impedance, and the tuned circuit produces a high impedance or a high impedance to a signal at a particular frequency. It can provide low impedance. Thus, the tuning circuit can reject or pass the components of the analog signal and also amplify the components of the analog signal based on the frequency of the components of the analog signal. The tuned circuit can be used in this manner as a filter for excluding or removing signals of a particular frequency or for removing noise from circuit components intended for processing analog signals. The tuned circuit can also be used to create a high electrical impedance by using the LC resonance of the circuit, and thus to counteract the effects of parasitic capacitances that are part of the circuit. One of the problems encountered in making inductors on the surface of a semiconductor substrate is self-resonance caused by the parasitic capacitance between the (spiral) inductor and the underlying substrate.
ance) limits the use of inductors at high frequencies. In designing such an inductor, it is important to reduce the electrostatic coupling between the manufactured inductor and the lower substrate.

At high frequencies, the electromagnetic field produced by the inductor produces eddy currents in the underlying silicon substrate. Since the silicon substrate is a resistive conductor, the eddy currents consume electromagnetic energy and therefore the energy loss is high, which results in a low Q value of the capacitor. This is the main reason for the low Q value of capacitors,
Therefore, the resonance frequency of 1 / √ (LC) limits the upper limit of the frequency. In addition, inductor-induced eddy currents interfere with the performance of circuits that are in close physical proximity to capacitors.

As already pointed out, one of the important elements used in manufacturing high frequency analog semiconductor devices.
One is an inductor that forms part of the LC resonant circuit. High device densities commonly found in semiconductor devices and the resulting high use of substrate surface area (int
In consideration of the nse use), the fabrication of the inductor must incorporate minimizing the surface area required for the inductor while retaining a high Q factor for the inductor. In general, the inductor formed on the surface of the substrate has a spiral shape, whereby a spiral object is formed in a plane parallel to the plane of the substrate. The conventional methods used to fabricate inductors on the surface of a substrate are subject to some constraints. Most high Q inductors are hybrid device components or monolithic microwave integrated circuits (MMI).
Formed as part of C) or fabricated as discrete devices, such fabrication is not easy to integrate into the general manufacturing process of integrated circuits. What can be clearly stated is that a circuit for the purpose of manipulating analog data and the function of storing analog data is formed on one monolithic semiconductor substrate, and by combining the function of manipulating digital data and the function of storing digital data, It means that many important advantages can be achieved. Such benefits include reduced manufacturing costs and reduced power consumption due to combined functionality. However, since the shape of the inductor formed on the surface of the semiconductor substrate is spiral, a parasitic capacitance is generated between the wiring of the inductor and the lower substrate due to the physical size of the inductor. A loss of electromagnetic energy is caused in the resistive silicon substrate on the side.
These parasitic capacitances have a significant negative impact on the functionality of the LC circuit made by rapidly reducing the resonant frequency of the tuning circuit used. More seriously, the electromagnetic field generated by the inductor produces an eddy current in the underlying resistive silicon substrate, which results in a large energy loss and a low Q factor of the inductor.

Inductor performance parameters are commonly referred to as inductor quality (Q) factors. The quality factor Q of the inductor is
It is defined as Q = Es / El, where Es is the energy stored in the reactive part of the device and El is the energy lost in the reactive part of the device. As the quality of the device is higher, the resistance value of the device approaches zero, and the Q factor of the device approaches infinity. For inductors made with a silicon substrate overlay, the electromagnetic energy produced by the inductor is lost primarily in the underlying resistive silicon substrate and in the metal lines being made to form the inductor. . The quality factor for the device is
It differs from the quality associated with filters or resonators. With respect to the device, the quality factor serves as a measure of the purity of the reactance (or susceptance) of the device. Reactance (or susceptance) purity can be degraded due to resistive silicon substrates, resistance of metal lines, and dielectric losses. There are always some physical resistors that dissipate energy in a practical arrangement, thereby reducing the energy that can be recovered. The quality factor Q is a dimensionless value. When the Q value is larger than 100, it is considered that the performance of the discrete inductor mounted on the surface of the printed circuit board is extremely high. For inductors forming part of integrated circuits, the Q factor is typically in the range of about 3-10.

When fabricating an inductor on a monolithic substrate on which additional semiconductor devices are fabricated, the parasitic capacitance that occurs as part of this fabrication will reduce the cutoff frequency achievable for inductors using conventional silicon processes. The upper limit is limited. For many applications, these limitations are unacceptable. LC
Depending on the frequency at which the circuit is designed to resonate, a fairly large value of quality factor (eg 50 or more) must be obtained. In this respect, the prior art is limited to obtaining higher quality factor values as separate units and integrating these separate units with surrounding device functions. This negates the advantages gained when using a monolithic structure in which the inductor and surrounding elements are made in one and the same semiconductor substrate. The non-monolithic approach also suffers from the additional wiring required to interconnect the subcomponents of the assembly, which introduces additional parasitic capacitance and resistive losses throughout the interconnecting network. have. In many applications of RF amplifiers (eg, battery powered applications), power consumption is an important point and should be as low as possible. Although increasing power dissipation can to some extent compensate for the effects of parasitic capacitance and resistive power loss, this approach has its limitations. With the rapid spread of wireless applications (such as mobile phones), there is a need for urgent resolution of these problems. Wireless communications is a rapidly expanding market and integration of RF integrated circuits is one of the most important challenges. One approach is to set the operating frequency to, for example, 10-1.
It is to increase it to the range of 00GHz drastically. At such high frequencies, the quality factor values obtained from silicon-based inductors are significantly reduced. For applications in these frequency ranges, monolithic inductors using materials other than silicon as the basis for making inductors are being investigated. Such monolithic inductors are, for example, sapphire or G
It is made using aAs as a base. These inductors have significantly less substrate loss (no eddy currents and therefore no electromagnetic energy loss) compared to their silicon counterparts, and therefore inductors with much higher Q values are obtained. These inductors also have a lower parasitic capacitance and thus have the ability to operate at higher frequencies. However, there remains a need to fabricate silicon-based inductors when more complex applications are required. For such applications, approaches using base materials other than silicon have been found to be too complex and inefficient, for example, GaAs as a medium for making semiconductor devices still has to be resolved. There are technical issues that remain. It has become clear that GaAs is a semi-insulating material at high frequencies, which reduces the electromagnetic loss that occurs on the surface of the GaAs substrate and thereby increases the Q factor of the inductor fabricated on the GaAs surface. There is. However, GaAs RF
Since the chips are expensive, a process that does not require the use of GaAs RF chips is cost effective.

Many different approaches have been attempted to incorporate inductors into the semiconductor environment without sacrificing device performance due to substrate loss. One of these approaches is to selectively remove the silicon under the inductor by etching (using a microfabrication method), thereby eliminating the effects of substrate resistive energy loss and parasitic capacitance. is there. Another method is to use multiple layers of metal (eg, aluminum) interconnect or copper damascene interconnect.

Another approach uses a high resistivity silicon substrate, which reduces resistive losses in the silicon substrate. The resistive substrate loss at the surface of the lower substrate forms a major factor in determining the Q value of the silicon inductor. In addition, a biased well (biased) under the spiral conductor
wells) have been proposed, but this also aims to reduce the induced loss on the surface of the substrate. A more complex approach is to make an active inductive element that simulates the electrical properties of an inductor when used in an active circuit. However, this latter approach consumes a lot of power from the simulated inductor and produces noise that is unacceptable for low power, high frequency applications. All of these approaches have a common goal of increasing the quality (Q) value of the inductor and reducing the surface area required to make the inductor. The most important consideration in this respect is the electromagnetic energy loss due to the electromagnetically induced eddy currents in the silicon substrate.

Reducing the size of integrated circuits reduces the cost per die and improves some performance. Metal connections that connect integrated circuits to other circuits or system elements have become relatively important, and IC
In combination with the further miniaturization, the circuit performance is becoming more and more adversely affected. The parasitic capacitance and resistance of the metal interconnect is increased, which significantly degrades chip performance. Most important in this regard are the voltage drops along the power and ground buses, and the RC delay of the critical signal path. Attempts to reduce resistance by using wider metal lines result in greater capacitance on these wires.

The latest method of making inductors on the surface of a semiconductor substrate is to make the inductor under the passivation layer using a fine-line technique. However, this results in a very small physical distance between the fabricated inductor and the surface of the substrate on which the inductor is fabricated (typically 1
(Less than 0 μm), which results in a large electromagnetic loss in the silicon substrate and thus a reduction in the Q value of the inductor. Increasing the distance between the inductor and the semiconductor surface can reduce the electromagnetic field in the silicon substrate inversely with the distance and increase the Q factor of the inductor. Thus by making an inductor overlying a passivation layer (by a post-passivation method) and further making an inductor on the surface of a thick dielectric (eg polymer) layer deposited or adhered on the surface of the passivation layer. As a result, the Q value of the inductor can be increased. In addition, parasitic resistance can be reduced by using a wider and thicker metal to make the inductor. The method of the present invention applies these principles of inductor fabrication by the post-passivation method, where the inductor is fabricated on a thick dielectric layer using a thicker, wider metal.

US Pat. No. 5,212,403 (Nakanishi)
It shows a method of forming wiring connections for a logic circuit depending on the length of the wiring connections inside and outside (on a wiring board on a chip).

US Pat. No. 5,501,006 (Gehman, Jr. et al.)
Shows a structure incorporating an insulating layer between an integrated circuit (IC) and a wiring board. Distribution lead leads to IC
Bonding pads are connected to substrate bonding pads.

US Pat. No. 5,055,907 (Jacobs) describes thin film multilayer wiring decals (wi) on a support substrate and on a chip.
By forming a ring decal, an extended integrated semiconductor structure is disclosed that allows the circuit to be integrated across chip boundaries. However, this patent document differs from the present invention.

US Pat. No. 5,106,461 (Volfson et al.)
Polyimide (dielectric) on IC in TAB structure
It teaches a multi-layer interconnect structure comprising alternating combinations of metal and metal layers.

US Pat. No. 5,635,767 (Wenzel et al.)
He teaches how to reduce RC delay by PBGA that separates multiple metal layers. U.S. Pat. No. 5,686,764 (Fulcher) shows a flip chip substrate that reduces RC delay by isolating the power supply and the I / O traces.

US Pat. No. 6,008,102 (Alfored et al.)
Figure 4 shows a spiral inductor using two metal layers connected by a via. US Pat. No. 5,372,967 (Sundaram et al.) Discloses a spiral inductor.

US Pat. No. 5,576,680 (Ling) and US Pat. No. 5,884,990 (Burghartz et al.) Show other spiral inductor designs.

[0020]

The main object of the present invention is to:
It is to improve the RF performance of high performance integrated circuits. Another object of the present invention is to provide a method of manufacturing an inductor having a high Q value.

Another object of the present invention is to replace a GaAs chip with a silicon chip as a base for manufacturing an inductor having a high Q value. Still another object of the present invention is to widen the frequency range of an inductor formed on the surface of a silicon substrate.

Yet another object of the present invention is to produce high quality passive electrical devices that overlay the surface of a silicon substrate. In this continuation-in-part application, a thick layer of dielectric is added over the passivation layer and a wide and thick metal line is over the thick layer of dielectric in a post-passivation sequence. The present invention is a high quality electrical device (eg, inductor, capacitor, or resistor).
Are further fabricated on the passivation layer or on the surface of the thick dielectric layer to extend this continuation-in-part application to a wider area. The method of the present invention further provides a method of packaging discrete passive electrical components at a distance substantially away from the underlying silicon surface.

This part continuation application is based on the re-distrib
Ution layer) and interconnect metal layers are taught in integrated circuit structures in which a dielectric layer is made on the surface of a conventional IC. A passivation layer is deposited on the dielectric of the redistribution layer and the interconnect metal layer, and a thicker polymer layer is deposited on the surface of the passivation layer. In the present invention, high quality electrical devices are fabricated on the surface of thick polymer layers.

The present invention, among other things, includes:
We are working on the fabrication of inductors (the focus is on the fabrication of inductors with a high Q value on the surface of a semiconductor substrate) using the fabrication method and fabrication procedure of semiconductor devices known in the prior art. Since the inductor of the present invention has high quality, it can be used for high frequency applications while suppressing power loss as much as possible. The invention further comprises
We are working on fabricating capacitors and resistors on the surface of a silicon substrate (thus, the main purpose of the method of the invention for fabricating capacitors and resistors is that these elements are commonly used by these devices on the underlying silicon substrate. To reduce the parasitic capacitances that are caused).

For a more specific description, referring to FIG. 1, a cross section of one embodiment of the present application is shown.
Transistors and other elements (not shown in FIG. 1) are provided on the surface of the silicon substrate 10. The surface of the substrate 10 is covered with the dielectric layer 12, and thus the dielectric layer 12
Are attached in the surface of the substrate 10 and on the elements provided on the substrate 10. Conductive interconnection line 11 is layer 1
2 is provided inside, and these lines are connected to the semiconductor device provided on the surface of the substrate 10.

Layer 14 (two examples shown) represents all of the metal and dielectric layers that would normally be produced over dielectric layer 12 and is therefore shown in FIG. Layer 14
May include multiple dielectric layers or insulating layers, etc.,
The conductive interconnection lines 13 form a network of electrical connections made over the layer 14.
Electrical contacts 16 overlay layer 14 and
Is present on the surface of. These electrical contacts 16 may be, for example, bonding pads that ensure the formation of electrical interconnections to the transistors and other devices provided on the surface of the substrate 10. These electrical contacts 16 are interconnection points within the IC assembly that need to be further connected to the surrounding circuitry. A passivation layer 18 (formed of, for example, silicon nitride) is deposited over layer 14 to prevent the underlying layers from moisture, contamination, etc.

An important step in this application is to deposit a thick polyimide layer 20 (deposited on the surface of layer 18).
start from. Access to electrical contact 16 must be provided so that the pattern of openings 22, 36 and 38 is etched through polyimide layer 20 and passivation layer 18 so that the pattern of openings 22, 36 and 38 is in electrical contact 16. Align with the pattern. Electrical contact 1
6 is an opening 22/3 formed in the polyimide layer 20.
6/38 extends electrically to the surface of layer 20.

The material used for the deposition of layer 20 is polyimide, but the material that can be used for this layer is not limited to polyimide and includes any known polymer (eg, SiCl _x O _y ). The polyimides described above are the preferred materials to use for the method of the present invention in making the thick polymer layer 20. Examples of polymers that can be used are silicon compounds, carbon compounds (ca
rbons), fluorides, chlorides
s), oxygen compounds, parylene or Teflon (R), polycarbonate (PC), polystyrene (P)
S), polyoxide (PO), poly polooxide (PPO), and benzocyclobutene (BCB).

Electrical contact with contact 16 is provided by opening 22/3
This can be ensured by filling the 6/38 with a conductive substance. The top surface 24 of these metal conductors is contained in the openings 22/36/38 to keep the IC in its environment.
nment) and for further integration in the surrounding electrical circuit. This latter explanation allows the semiconductor device provided on the surface of the substrate 10 to be further connected to surrounding elements and circuits via the conductive interconnects contained in the openings 22/36/38. Is the same as saying. Interconnect pads 26 and 28 are formed on the surface 24 of the metal interconnect contained in openings 22, 36 and 38. These pads 26 and 28 may be of any width and thickness design to accommodate particular circuit design requirements. One pad can be used, for example, as a flip chip pad.
Other pads can be used for power distribution or as a ground or signal bus. For example, as shown in FIG. 1, the following connections can be made into pads: pad 26 can function as a flip chip pad and pad 28 can be a flip chip pad.
Function as a pad or power supply, ground terminal,
Alternatively, it can be connected to an electrical signal bus. There is no relationship between the size of the pad shown in FIG. 1 and the possible electrical connections that can use this pad. Pad size, standard practice, and constraints in designing electrical circuits determine whether an electrical connection will result in a given pad being useful.

The description given below is for the contact 1 in FIG.
6 sizes and numbers. These contacts 16 are located on a thin dielectric (layer 14 in FIG. 1) so the size of the pad should not be too large. This is because a large pad size causes a large capacitance. Furthermore, the large size of the pad impedes the routing capability of the metal layer. Therefore, it is preferable to keep the size of the pad 16 relatively small. However, the size of pad 16 is also directly related to the aspect ratio of vias 22/36/38. Taking into account the via etching and via filling, an acceptable aspect ratio is about 5. Based on these considerations, the size of the contact pad 16 is on the order of 0.5 μm to 30 μm, and the exact size depends on the thickness of layers 18 and 20.

The present application does not limit the number of contact pads that can be incorporated into a design, which number depends on the package design requirements. Layer 18 in FIG. 1 may be a conventional IC passivation layer.

The most commonly used passivation layer in the state of the art is plasma enhanced CVD (P
ECVD) oxide layer and plasma enhanced CVD nitride layer. In making the passivation layer 18, first a PECVD oxide layer of about 0.2 μm is deposited and then a nitride layer of about 0.7 μm is deposited. The passivation layer 18 is a device wafer.
It is extremely important because it protects against ionic contamination by moisture and foreign matter. Placing this layer between the sub-micron process (of the integrated circuit) and the tens-micron process of the (interconnect metallization structure) is very important. This is because it allows for a cheaper process with less stringent clean room requirements for the process of making interconnect metallization structures.

Layer 20 has a thickness of more than 2 μm (after curing)
Is a thick polymer (eg, polyimide) dielectric layer with. The range of polymer thickness may be from 2 μm to 150 μm, depending on electrical design requirements.

For depositing layer 20, for example, polyimide HD2732 or 2734 from Hitachi-DuPont can be used. The polyimide can be spin-on coated and cured. After spin-on coating, apply polyimide in a reduced pressure atmosphere or nitrogen atmosphere to 40
Cure at 0 ° C. for about 1 hour. To obtain a thicker polyimide layer, the polyimide film is coated multiple times and cured.

Another material that can be used to make layer 20 is a polymer of benzocyclobutene (BCB). This polymer is currently manufactured industrially, for example by Dow Chemical Company, and it has recently been shown that it can be used in place of common polyimide applications.

There have been various opinions regarding the dimensions of the openings 22, 36 and 38. The dimensions of the aperture and dielectric thickness together determine the aspect ratio of the aperture. Due to this aspect ratio, the via etch process and metal fill capability become an issue. As a result, the diameter for the openings 22/36/38 may range from about 0.5 μm to 30 μm.
The height for 2/36/38 may range from about 2 μm to 150 μm. The aspect ratio of the openings 22/36/38 is designed to allow the vias to be filled with metal. The vias can be filled with CVD metal (eg, CVD tungsten or CVD copper), electroless nickel, damascene metal filling, or electroplated copper.

The application can be further expanded by applying multiple polymer (eg polyimide) layers,
Therefore, it can also be adapted to a wider variety of applications. The functionality of the structure shown in FIG. 1 can be further expanded by depositing a second polyimide layer over the previously deposited layer 20 and overlaying pads 26 and 28. By selective etching and metal deposition, on the surface of the second polyimide layer,
Additional contacts can be made that can be interconnected to pads 26 and 28. The additional polyimide layers and contact pads made thereon can be customized for specific applications, and the expanded application of multiple polyimide layers greatly increases the versatility and usefulness of this continuation-in-part application.

FIG. 1 illustrates the basic design advantages of this continuation-in-part application. Due to these advantages, the metal layer 14
Submicron or fine lines running in the immediate vicinity of the contact point 16 and the contact 16 can be extended upwards 30 via the metal interconnect 36. This extension is a metal interconnect 28
In the horizontal plane of the direction 32 and back to the lower side 34 via the metal interconnect 38. Passivation layer 1
8 and the insulating layer 20 have the same functions and structures as described above. The basic design advantage of the present invention is that the fine wire interconnects are "elevated" or "fan-oued".
t) ”, and these interconnects from the micro-level and sub-micro level to the levels of metal interconnects (which have much larger dimensions and therefore smaller resistance and capacitance, and are easier to manufacture. And even more cost-effective.) This aspect of the present application is line re-distribu
It does not include any aspect of performing an action) and thus has the inherent property of simplicity. Therefore, this aspect further enhances the importance of the present application in that it allows micro and sub-micro wiring to be accessible at the level of wide and thick metal. Interconnects 20, 36, and 38 rise through the passivation layer and the polymer or polyimide dielectric layer and continue to extend over a wide and thick metal level over a distance and from the wide and thick metal level to finer levels. Interconnect fine level metals by continuing to descend and continue through the passivation layer and polymer or polyimide dielectric layer to the appropriate metal level. The extension made in this way need not be limited to the extension to a particular type of fine metal interconnect 16 (eg, signal or power or ground) that includes wide and thick metal lines 26 and 28. . The types of interconnects that can be reliably established in this way are constrained by the laws of physics and electronics (if any) and the limiting factor (if any).
actor) would be conventional electrical constraint factors such as resistance, propagation delay, RC constant, and other factors. It is important that the present continuation application gives a much wider latitude in the applicability of these laws, and in doing so, regarding the application and use of integrated circuits, as well as these circuits. It provides a significantly expanded range of conformance to the wide and thick metal environment.

FIG. 2 illustrates the basic interconnection aspect of this continuation-in-part application, in which not only is fine metal raised to the plane of a wide, thick metal in accordance with the present invention, but also of a thick polyimide layer 20. It shows how it can be scaled up to add an inductor on the surface. Inductor is board 1
Made in a plane parallel to the surface of 0 and separated from the surface of the substrate 10 by the combined height of the layers 12, 14, 18 and 20. FIG. 2 shows the substrate 1
The cross section 40 of the inductor is shown when cut in a plane perpendicular to the surface of 0. Wide and thick metal also contributes to saving energy loss due to resistance. In addition, low resistivity metals (eg, gold, silver, and copper) can be applied using electroplating, with a thickness of about 20 μm.
Can be

FIG. 3 shows a top view 42 of the spiral structure of the inductor 40 fabricated on the surface of the dielectric layer 20. The cross section of the inductor 40 in FIG. 2 is a view taken along line 2-2 ′ in FIG. The method used to make inductor 40 is a conventional method of depositing a metal (eg, gold, copper, etc.) by electroplating or metal sputtering.

FIG. 4 shows a top view of the inductor 40, which is further isolated from the surface of the substrate 10 by the addition of a layer 44 of ferromagnetic material. Apertures have been created in a layer 44 of ferromagnetic material for conductors 36 and 38, which can be measured empirically, depending on the type of material used and the layer (shown in cross section in FIG. 4). Deposited using conventional methods to a thickness that is affected and depends in part on the thickness of the ferromagnetic material (eg, used to overlay layer 20) to create the structure. There is. The surface area of the ferromagnetic material layer 44 is generally such that the inductor 40 is aligned with the layer 44,
4 extends over the surface of layer 18 so as to overlay 4 and the surface area of layer 44 extends somewhat beyond these boundaries to shield the surface of substrate 10 from the electromagnetic field of inductor 40. Has improved.

Layer 44 is not limited to being a layer of ferromagnetic material and can be a layer of a good conductor (eg, but not limited to gold, copper and aluminum). The overlaying inductor 40 is fabricated on the surface of the polyimide layer 20 and can be isolated from the underlying silicon substrate 10 by a layer 44 containing a ferromagnetic or good conductor.

FIG. 5 shows, for the sake of clarity, a simplified cross section of the substrate and the layers produced on the surface of the substrate according to the method of the invention. The highlighted areas are as defined above. That is, -10 is a silicon substrate, -12 is a dielectric layer deposited on the surface of the substrate, -14 is an interconnect layer containing interconnect lines, vias, and contacts, 16 is a contact on the surface of interconnect layer 14, -18 is a passivation layer in which an opening is made accessible to contact 16, -20 is a thick polymer layer, and -21 is a polyimide. It is a conductive plug provided through the layer 20.

The thick polymer layer 20 can be applied in liquid form on the surface of the passivation layer 18 or can be laminated by applying a dry coating on the surface of the passivation layer 18. Conductive plug 2
The vias required to make one can be made by conventional photolithography processes or can be made using laser (drill) techniques.

As will be apparent from the above description, the arrangement of layers shown in the cross-section of FIG. It is made so that it can be made in the state of being in electrical contact with The dielectric layer 12 in the cross section shown in FIG. 5 may be part of the layer 14. Because layer 14 is an Intra-level electric (Intr) that allows layer 12 to be easily integrated.
a Level Dielectric (ILD) layer.

For the cross section shown in FIG. 6, the same layers as described with reference to FIG. 5 are also given to this cross section. The top layer 17 of the silicon substrate 10 containing the active semiconductor device is further shown. Furthermore, a cross section of the inductor 19 produced on the surface of the passivation layer 18 is shown. Again, it is emphasized that the ohmic resistance of the metal used for inductor 19 should be as low as possible. Therefore, for forming the inductor 19, it is preferable to use a thick layer of gold, for example. A thick layer of gold has been shown to increase the Q factor of inductor 19 from about 5 to about 20 for the 2.4 GHz application, which is inductor 1
It shows that the Q value of 9 was considerably improved.

FIG. 7 shows a cross section of a capacitor fabricated on the surface of the substrate 10. A layer 14 including conductive interconnect lines and contacts has been fabricated on the surface of the substrate 10. A passivation layer 18 is deposited on the surface of layer 14 and openings are made in passivation layer 18 that allow access to the surface of contact pad 16.

As is well known, capacitors are
It includes a lower plate, an upper plate, and a dielectric layer separating the upper plate and the lower plate. These components of the capacitor can be easily identified as follows from the cross section shown in FIG. -42 is a conductive layer forming the lower plate of the capacitor, -44 is a conductive layer forming the upper plate of the capacitor, -46 separates the upper plate 44 of the capacitor from the lower plate 42. It is a dielectric layer.

It should be noted that the capacitors are fabricated on the surface of the passivation layer 18, as can be seen from the cross section shown in FIG. -It is called a sequence. Individual layers 42, 4
The process conditions and materials that can be used to make 4, and 46 have been previously described and therefore need not be discussed in further detail here.

Of importance are the various thicknesses to which the three layers 42, 44 and 46 can be deposited, as follows: -The thickness of the passivation layer 18 is about 0.1-0.3μ.
m, the thickness of the conductive material layer 42 is about 0.5-20 μm, the thickness of the dielectric layer 44 is about 500-10,000 angstroms, and-the conductive material layer 46 is The thickness is about 0.5 to 20 μm.

The capacitor made by the post-passivation method, shown in cross section in FIG. 7, reduces the parasitic capacitance between the capacitor and the underlying silicon substrate, and uses a thick layer of conductive material. It allows (thereby resistance of the capacitor decreases; this is particularly important in wireless applications), and - a high dielectric material as the dielectric between the upper and lower plates of the capacitor (e.g., TiO ₂ And Ta ₂ O ₅ )
It is possible to use (as a result, the capacitance value of the capacitor becomes higher).

FIG. 8 shows a three-dimensional view of the solenoid structure of the inductor 19 produced on the surface of the passivation layer 18. Further emphasized in FIG. 8 is -23, the thick polymer layer 20 of FIG. 5 due to the interconnection of the upper and lower metal levels of the inductor metal.
, -25, the bottom metal of the inductor, and -27, the top metal for the inductor.

FIG. 9 shows that a thick layer of polymer 29 is first deposited, a polymer layer (not shown) is deposited thereon, and vias 23 are made in the thick layer of polymer 20 (FIG. 5). A three-dimensional view of an inductor fabricated on the surface of passivation layer 18 is shown. Figure 9
Shows a polyimide layer 29 in addition to the layers highlighted above. The inductor 19 is made by building up the bottom metal 25 of the inductor 19, the top metal 27 of the inductor, and the via 23 made in the layer 20 (FIG. 5), which preferably comprises a polymer.

FIG. 10 shows layer 2 as already shown in FIG.
The top view in case the inductor is produced on the surface of 0 is shown. Vias 23 are top metal lines 27 of inductor 19, bottom metal lines 25 of inductor 19 (hatched because they are not visible on the surface of layer 20).
As well as being emphasized. In more detail, Bahia 23 '
And 23 "for the bottom of via 23 'and via 2
The upper ends of the 3 "are interconnect lines 31 and 33, respectively (Fig. 11).
, And these interconnection lines 31 and 33 provide connections for further interconnection of inductor 19.

FIG. 11 shows a cross section of the structure of FIG. 10 taken along the line 6e-6e 'shown in FIG. Contact pads 16 ′ are provided on the surface of the passivation layer 18, such contact pads 16 ′ forming vias 23, 2 for interconnection between the bottom metal 25 of the inductor 19 and the top metal 27 of the inductor 19.
In contact with 3'and 23 ". Vias 23 'and 2"
Interconnects to the 3 "are lines 31 and 33, which connect the inductor 19 to surrounding circuitry or devices, as previously described.

The fabrication of toroidal inductors overlaying a passivation layer is shown in FIGS. 12 and 13, where the toroidal coil 19 'is shown as a passivation layer 1.
8 on the surface. A top level metal 27 ', a bottom level metal 25', and a via 23 'interconnecting the bottom level metal 25' and the top level metal 27 'are shown in FIG.
Emphasized in 2.

FIG. 13 is a diagram of FIG. 12 for further explanation.
Figure 19 shows a top view of the toroidal 19 '. The highlighted features of this figure have been described above and therefore need not be discussed further here.

FIG. 14 shows a cross section when a capacitor is formed on the surface of the substrate 10 as shown in FIG. However, in the cross-section shown in FIG. 14, a thick polyimide layer 20 is deposited on the surface of the passivation layer 18 and patterned and etched to make contact pads 16 accessible through the thick polyimide layer 20. Has been processed. The thick polymer layer 20 separates most of the capacitors. That is, lower plate 42, upper plate 44, and dielectric 46 are separated from the surface of substrate 10 by a distance equal to the thickness of layer 20. As mentioned above, the polyimide thickness range may vary from 2 μm to 150 μm, depending on electrical design requirements. This description also applies to the cross section shown in FIG. 14, so that the layers of the capacitor can be separated from the surface of the substrate 10 by a distance of 2 μm to 150 μm. As a result, the distance between the capacitor and the underlying silicon substrate will be significantly increased, and thus the parasitic capacitance will be significantly reduced.

FIG. 15 shows that the passivation layer 18 is attached on the surface of the substrate 10.
The substrate 10 when the resistor 48 is formed on the surface of the substrate
The cross section of FIG. As is well known, a resistor is made by connecting two points with a material that creates an electrical resistance to the passage of an electric current.
The two locations that are part of the resistor 48 shown in cross section in FIG. 15 are the contact pads 16 made in or on the surface of the interconnect layer 14. A resistor was made according to the method of the invention by interconnecting the two contact pads and making a layer 48 deposited on the surface of the passivation layer 18 between the two contact pads. To make layer 48, a material of high resistivity (eg,
TaN, silicon nitride, phosphosilicate glass (PS
G), silicon oxynitride, aluminum, aluminum oxide (Al _x O _y ), tantalum, niobium, or molybdenum) can be used. The dimensions (eg, thickness, length, and width) of the deposition of layer 48 of high resistivity material depend on the application and are therefore not specified here. The resistor shown in cross section in FIG. 15 is made by the post passivation method on the surface of the passivation layer 18, as in the case of the capacitors of FIGS. 7 and 14.

FIG. 16 shows a cross section of the substrate 10 with an interconnect layer 14 formed on the surface of the substrate. A passivation layer 18 is deposited on the interconnect metal layer 14 and a thick polyimide layer 20 is deposited on the surface of the passivation layer 18. A resistor 48 is fabricated on the surface of the polyimide layer 20. The resistor 48 is manufactured with the two contact pads 16 and a thin metal layer having a high resistivity connected to each other. By increasing the distance between the resistor body and the substrate surface (by increasing the thickness of the polyimide layer 20), the parasitic capacitance between the resistor body and the substrate is reduced, thus improving the resistance. Components are obtained (reduced parasitic capacitance loss, improved high frequency performance).

A further application of the post-passivation method of the present invention is shown in FIGS. 17 and 18, where contact pad 1
The focus is on making ball-shaped contacts between 6 and the overlying electrical element (eg, discrete inductor). From the surface of the substrate 10 upwards, most of the layers of Figure 17 are identified in Figure 17 using the same reference numbers used above for the three layers. Not yet identified in FIG. 17 is −50, a contact plug formed through thick polymer layer 20, −52, selective solder deposition (electroplating or ball mounting on the surface of plug 50, A contact ball formed on the surface of the contact plug 50 using the conventional method of fluxing onto the deposited solder and flowing the solder to form the contact ball 52; A cross section of an electrical element (eg, an inductor or discrete capacitor or resistor).

FIG. 18 shows a cross section of the silicon substrate 10, in which a discrete electric element 54 is mounted on the surface of the substrate and a contact ball 56 is used, whereby the substrate 10 and the electric element 54 are connected to each other. The distance between them becomes a considerable value. A contact ball is inserted into an opening made in the passivation layer 18 overlying the contact pad 16, and this (relatively large) contact ball 56 forms the surface of the substrate 10 and the discrete electrical element 54. Result in a considerable degree of isolation.

The method shown in FIGS. 17 and 18 is that the passive element 54 is a substantial distance from the surface of the substrate 10, and that the passive element is discrete on the surface of the printed circuit board (PCB). Instead of mounting 54, the invention shows that the passive element 54 can be mounted closer to the semiconductor device.

The following points have been emphasized throughout the method and procedure described above with reference to the embodiments shown in cross section in the accompanying drawings: -further separating the passive device from the silicon substrate, thereby The adverse effects caused by the substrate due to the electromagnetic losses experienced by the substrate are reduced, the post-passivation method of the invention allows the selection of design parameters of the discrete device, so that
Resistance of discrete capacitors and discrete inductors is reduced. This becomes even clearer from the following comparison of the prior art method and the method of the present invention.

The prior art requires the use of thin metal to fabricate the inductor, which requires the fabrication of a wider coil for the inductor, which increases the surface area required for the inductor and, therefore, The parasitic capacitance of the inductor increases, which causes eddy current losses at the substrate surface.

In contrast to this, the present invention allows the use of thick metal because the metal of the passive element is separated from the (thin metal) interconnect layer 14 (by the thick polymer layer) and is therefore required for the inductor. It takes less surface area and reduces the resistivity of the inductor, which increases the Q factor of the inductor.

While the preferred embodiment of the invention has been described and described in detail, those skilled in the art will appreciate that it does not depart from the spirit of the invention and also from the scope of the appended claims. Needless to say, various modifications are possible.

[Brief description of drawings]

FIG. 1 shows a cross section of an inventive interconnection scheme according to this continuation-in-part application.

FIG. 2 shows a cross section of an expanded version of this continuation-in-part application in which an inductor is fabricated on the surface of a thick polyimide layer.

FIG. 3 shows a top view of an inductor made according to the method of the present invention.

FIG. 4 shows a cross section of a layer overlying a substrate, in which an inductor is fabricated on the surface of a thick polyimide layer and a ferromagnetic material is used to insulate the inductor from the underlying silicon substrate. More layers have been added.

FIG. 5 shows a cross section of a simplified substrate and a plurality of layers fabricated on the surface of a substrate using the method of this continuation-in-part application.

FIG. 6 shows the cross section of FIG. 5 when an inductor is added over the passivation layer.

FIG. 7 shows a cross section when a passivation layer is deposited on the surface of a substrate and a capacitor is produced on the surface of the passivation layer.

FIG. 8 shows a three-dimensional view of an inductor made on the surface of a passivation layer by making vias in a thick polymer layer.

FIG. 9 shows a three-dimensional view of an inductor made in a thick polymer layer deposited on the surface of a thick polyimide layer.

FIG. 10 shows a plan view when an inductor is produced on the surface of layer 20.

11 shows a cross section of the structure of FIG. 10 taken along line 6e-6e ′ of FIG.

FIG. 12 shows a three-dimensional view of an inductor made on the surface of a passivation layer, the inductor having the shape of a solenoid.

13 shows a plan view of the inductor of FIG.

FIG. 14 shows a cross section where a passivation layer is deposited on the surface of a substrate, a thick polyimide layer is deposited on the passivation layer, and a capacitor is fabricated on the surface of the thick polyimide layer. ing.

FIG. 15 shows a cross section where a passivation layer is deposited on the surface of the substrate and a resistor is fabricated on the surface of the passivation layer.

FIG. 16 shows a cross section where a passivation layer is deposited on the surface of a substrate, a thick polyimide layer is deposited on the passivation layer, and a resistor is fabricated on the surface of the thick polyimide layer. Shows.

FIG. 17 shows that discrete electric elements are mounted on the surface of a silicon substrate and contact balls are used, which results in a considerable distance between the substrate and the electric elements, and A cross section is shown where a polyimide layer is used.

FIG. 18 shows that discrete electrical components are mounted on the surface of a silicon substrate and thick contact balls are used, which results in a considerable distance between the substrate and the electrical components, and The cross section is shown where the polyimide layer is not used.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/90 AF term (reference) 5F033 HH07 HH08 HH11 HH13 HH14 HH20 HH21 HH32 HH35 JJ11 JJ19 KK00 PP06 PP15 PP27 PP28 QQ09 QQ37 RR04 RR06 RR21 RR22 RR23 RR24 SS15 SS22 TT04 VV07 VV08 VV09 VV10 WW01 WW02 XX10 XX24 5F038 AC01 AC15 AC19 AR06 AZ05 BE07 CD20 DF01 DF03 DF12 EZ14 EZ20

Claims (86)

[Claims] 1. A method for forming an inductor for a high-performance integrated circuit, which overlays the surface of a semiconductor substrate, comprising: (a) a semiconductor substrate having a semiconductor device formed in or on the surface, Providing a semiconductor substrate having electrical contacts provided to said semiconductor device in or on the active surface of a semiconductor substrate; and (b) an overlaying interconnect metal including one or more layers of interconnect. A metallization structure is formed on the active surface of the semiconductor substrate, and a layer of the interconnect is provided in or on the surface of the interconnecting metallization structure overlying the electrical contacts. , A conductive interconnect line or contact or conductive via in one or more layers, at least one of said electrical contacts overlaying said interconnect metallization structure. Said one or more of the conductive interconnect lines or at least one contact of the conductive contacts or the conductive vias provided in the layer, at least one of the metal wire or the contact or the conductive vias
Contacting at least one of the electrical contacts on the semiconductor device in or on the surface of the substrate; and (c) depositing a passivation layer on the overlaying interconnect metallization structure. (D) said insulating and isolating polymer layer being substantially thicker than said passivation layer and substantially thicker than a dielectric intermediate layer used to fabricate said interconnect metallization structure. Depositing on a passivation layer; (e) forming an opening through the insulating and isolating polymer layer and through the passivation layer in the surface of the overlying interconnect metallization structure or At least one of said electrical contacts provided on a surface
Exposing the pair; (f) filling the opening with a conductive material to make a metal contact through the opening; (g) placing the inductor on the surface of the insulating / separating polymer layer. Forming, said inductor being connected to at least one pair of said electrical contacts provided in or on the surface of said overlying interconnect metallization structure. 2. The size of the electrical contacts provided in or on the surface of the overlying interconnect metallization structure ranges from about 0.3 μm to about 50 μm.
The method of claim 1. 3. The electrical contacts provided in or on the surface of the overlaying interconnect metallization structure are sputtered aluminum, CVD tungsten,
The method of claim 1, comprising a material selected from the group comprising CVD copper, electroplated gold, electroplated silver, electroplated copper, electroless gold, and electroless nickel. 4. The method of claim 1, wherein the inductor is embedded in a dielectric and further covered by a passivation layer. 5. The method of claim 4, wherein the dielectric is a low K dielectric. 6. A ferromagnetic material overlaying the passivation layer having a thickness of about 1,000 to 50,000 Angstroms and a surface area greater than that of the inductor overlying the insulating polymer layer. Inserting one or more layers of said ferromagnetic material between the surface of said passivation layer and the insulating and separating polymer layer deposited thereon by adding one or more layers of material, The method of claim 1. 7. The inductor is a spiral design, made on the surface of the insulating / separating polymer layer and in a plane parallel to the surface of the insulating / separating polymer layer. The method described in 1. 8. The method of claim 1, wherein the inductor is made using a damascene process. 9. The method of claim 1, wherein the inductor is made using a photolithographic exposure and etching method. 10. A method for forming a capacitor for a high performance integrated circuit on a surface of a semiconductor substrate, which comprises a top plate, a bottom plate, and a dielectric layer inserted between the top plate and the bottom plate. (A) preparing a semiconductor substrate having a semiconductor device formed in or on the surface thereof, the semiconductor substrate having electrical contacts provided on the semiconductor device in or on the active surface of the semiconductor substrate; And (b) forming an overlaying interconnect metallization structure including one or more layers of interconnect on the active surface of the semiconductor substrate, the layer of interconnect including electrical contacts. A conductive interconnect line or contact or conductive via in one or more layers in or on the surface of the overlying interconnect metallization structure; At least one is in contact with at least one of said conductive interconnect line or said conductive contact or said conductive via provided in said one or more layers of said overlaying interconnect metallization structure, said metal line or said At least one of the contacts or said conductive vias
Contacting at least one of the electrical contacts provided in the semiconductor device in or on the surface of the substrate,
The electrical contacts provided on the surface of the overlying interconnect metallization structure are divided into pairs of even and odd adjacent contact points so that one electrical contact can belong to only one pair. (C) depositing a passivation layer on the overlying interconnect metallization structure; and (d) subjecting the passivation layer to patterning and etching to create openings in the passivation layer. And at least one opening overlays at least one even number of the electrical contacts provided in or on the surface of the overlaying interconnect metallization structure; and (e) the passivation. A first layer of conductive material on the surface of the passivation layer including the openings made in the layer; And (f) subjecting the first conductive material layer to a patterning process and an etching process to form an even number of the even-numbered locations provided in or on the surface of the overlaying interconnect metallization structure Making an opening in at least one of the electrical contacts and making the bottom plate of the capacitor; (g) the first electrically conductive material including the opening for at least one of the even numbered electrical contacts. Depositing a dielectric layer on the surface of the layer; (h) patterning and etching the dielectric layer to form at least one of the even-numbered electrical contacts.
An opening in the dielectric layer for one, partially exposing at least one of the even-numbered electrical contacts, and creating the dielectric layer to be inserted between the top plate and the bottom plate. (I) depositing a second conductive material layer on the surface of the dielectric layer including at least one opening formed in the dielectric layer; and (j) the second conductive layer. Patterning treatment and etching treatment on the functional material layer to produce the upper plate of the capacitor. 11. The surface of the patterned / etched passivation layer including the openings made in the passivation layer as an additional treatment step performed after the step of patterning and etching the passivation layer. A step of depositing an insulating / separating polymer layer; patterning and etching the insulating / separating polymer layer to form an even number of locations on the surface of the overlaying interconnect metallization structure. Forming at least one opening in the insulating polymer layer that is aligned with at least one of the electrical contacts. 12. The cured and isolated polymer layer has a thickness in the range of about 1.0 to 150 μm.
The method described in 1. 13. The insulating / separating polymer layer is spin-on coated and cured.
The method described. 14. A method of forming a resistor for a high performance integrated circuit on a surface of a semiconductor substrate, comprising: (a) a semiconductor substrate having a semiconductor device formed in or on the surface, Providing a semiconductor substrate having electrical contacts provided to said semiconductor device in or on the active surface of a semiconductor substrate; and (b) an overlaying interconnect metal including one or more layers of interconnect. A metallization structure is formed on the active surface of the semiconductor substrate, and a layer of the interconnect is provided in or on the surface of the interconnecting metallization structure overlying the electrical contacts. A conductive interconnect line or conductive contact or conductive via in one or more layers, at least one of said electrical contacts being said one or more layers of said overlaying interconnect metallization structure. The conductive interconnect lines or at least one contact of the conductive contacts or the conductive vias provided, at least one of the metal wire or the contact or the conductive vias
Contacting at least one of the electrical contacts on the semiconductor device in or on the surface of the substrate; and (c) depositing a passivation layer on the overlaying interconnect metallization structure. (D) patterning and etching the passivation layer to create openings in the passivation layer, at least two of the openings being provided in a surface of the overlying interconnect metallization structure. (E) depositing a layer of conductive material on the surface of the passivation layer including the openings made in the passivation layer; and (f) Patterning and etching the resistive conductive material layer to remove the passivation Forming a layer of electrically conductive material interconnecting at least one pair of said openings made in an insulating layer and making said resistor;
Including the method. 15. A method of forming a resistor for a high performance integrated circuit on a surface of a semiconductor substrate, comprising: (a) a semiconductor substrate having a semiconductor device formed in or on the surface, Providing a semiconductor substrate having electrical contacts provided to said semiconductor device in or on the active surface of a semiconductor substrate; and (b) an overlaying interconnect metal including one or more layers of interconnect. A metallization structure is formed on the active surface of the semiconductor substrate, and a layer of the interconnect is provided in or on the surface of the interconnecting metallization structure overlying the electrical contacts. A conductive interconnect line or conductive contact or conductive via in one or more layers, at least one of said electrical contacts being said one or more layers of said overlaying interconnect metallization structure. The conductive interconnect lines or at least one contact of the conductive contacts or the conductive vias provided, at least one of the metal wire or the contact or the conductive vias
Contacting at least one of the electrical contacts on the semiconductor device in or on the surface of the substrate; and (c) depositing a passivation layer on the overlaying interconnect metallization structure. (D) patterning and etching the passivation layer to create openings in the passivation layer, at least two of the openings being provided in a surface of the overlying interconnect metallization structure. Overlaying and partially exposing at least one pair of electrical contacts being provided; (e) insulating on the surface of the patterned and etched passivation layer including the openings made in the passivation layer. The step of attaching a separating polymer layer; (f) the insulating and separating polymer Patterning and etching the layer to form at least one pair of openings in the insulating and separating polymer layer that align with at least one pair of openings formed in the passivation layer,
And partially exposing at least one pair of electrical contacts provided in the surface of the overlying interconnect metallization structure; (g) the opening made in the insulating and separating polymer layer. A step of adhering a conductive material layer on the surface of the insulating / separating polymer layer including: (h) a patterning treatment and an etching treatment on the resistive conductive material layer to form the passivation layer. Making a layer of conductive material interconnecting at least one pair of said openings, and making said resistor;
Including the method. 16. The passivation layer is about 0.15.
Plasma enhanced CV with thickness in the range of up to 2.0 μm
16. The method of claim 15, comprising a D (PECVD) oxide layer, on which a PECVD nitride layer having a thickness in the range of about 0.5-2.0 [mu] m is deposited. 17. The method of claim 15, wherein the insulating and isolating polymer layer comprises a polymer of polyimide or benzocyclobutene (BCB). 18. The thickness of the insulating / separating polymer layer after curing is in the range of about 1.0 to 150 μm.
The method according to 5. 19. The insulating / separating polymer layer is spin-on coated and cured.
The method described. 20. The insulating / separating polymer layer is subjected to multiple treatment steps of spin-on coating and curing.
The method according to claim 19. 21. A method of mounting a discrete electrical component on a surface of a semiconductor substrate, comprising: (a) a semiconductor substrate having a semiconductor device formed in or on the surface, wherein the semiconductor substrate is active. Providing a semiconductor substrate having electrical contacts provided to said semiconductor device in a surface or on an active surface; and (b) an overlaying interconnect metallization structure including one or more layers of interconnect. Conductive interconnects fabricated on the active surface of the semiconductor substrate, with a layer of the interconnect being provided in or on the surface of the overlying interconnect metallization structure with electrical contacts. Lines or conductive contacts or conductive vias in one or more layers, at least one of the electrical contacts being in the one or more layers of the overlaying interconnect metallization structure. The conductive interconnect lines or at least one contact of the conductive contacts or the conductive vias kicked, at least one of the metal wire or the contact or the conductive vias
Contacting at least one of the electrical contacts on the semiconductor device in or on the surface of the substrate; and (c) depositing a passivation layer on the overlaying interconnect metallization structure. (D) patterning and etching the passivation layer to create openings in the passivation layer, at least two of the openings being provided in a surface of the overlying interconnect metallization structure. Overlying at least one pair of electrical contacts that are present and providing at least one pair of electrical contacts in the passivation layer; (e) patterning and etching including the openings made in the passivation layer. An insulating / separating polymer layer is attached on the surface of the passivation layer. And (f) patterning and etching the insulating / separating polymer layer to form at least one pair of openings aligned with the at least one pair of electrical contacts provided in the passivation layer for insulating / separating. (G) selectively depositing a conductive material layer on the surface of at least one pair of electrical contacts provided in the passivation layer to form the insulating / separating polymer layer; Filling an opening and making a conductive plug through the insulating and separating polymer layer, the conductive plug overlaying at least one pair of electrical contacts provided to the passivation layer; and (h) a surface of the conductive plug. Selectively producing a solder layer thereon; (i) the electrical contacts of the discrete electrical components are selectively A step of arranging the discrete electrical component on the selectively produced solder layer and in alignment with the selectively produced solder layer so as to be aligned with the produced solder layer; and (J) A solder ball is formed in the insulating / separating polymer layer by flowing the selectively-prepared solder layer to connect the discrete electrical component and the conductive plug, and thereby the discrete electrical component. And connecting a pair of electrical contacts at the passivation layer. 22. The method of claim 21, wherein the insulating / separating polymer layer comprises a polymer of polyimide or benzocyclobutene (BCB). 23. The thickness of the insulating / separating polymer layer after curing is in the range of about 1.0 to 150 μm.
The method described in 1. 24. The insulating / separating polymer layer is subjected to multiple treatment steps of spin-on coating and curing.
The method of claim 21. 25. The method of claim 21, wherein the discrete electrical component is selected from the group including resistors, capacitors, and inductors. 26. A method of mounting discrete electrical components on the surface of a semiconductor substrate, comprising: (a) a semiconductor substrate having a semiconductor device fabricated in or on the surface, wherein the semiconductor substrate is active. Providing a semiconductor substrate having electrical contacts provided to the semiconductor device in a surface or on an active surface; and (b) an overlaying interconnect metallization structure including one or more layers of interconnect. Conductive interconnects fabricated on the active surface of the semiconductor substrate, with a layer of the interconnect being provided in or on the surface of the interconnecting metallization structure overlaid with electrical contacts. Lines or conductive contacts or conductive vias in one or more layers, at least one of the electrical contacts being in the one or more layers of the overlaying interconnect metallization structure. The conductive interconnect lines or at least one contact of the conductive contacts or the conductive vias kicked, at least one of the metal wire or the contact or the conductive vias
Contacting at least one of the electrical contacts on the semiconductor device in or on the surface of the substrate; and (c) depositing a passivation layer on the overlaying interconnect metallization structure. (D) patterning and etching the passivation layer to create openings in the passivation layer, at least two of the openings being provided in a surface of the overlying interconnect metallization structure. Overlying at least one pair of electrical contacts being provided and providing at least one pair of electrical contacts in the passivation layer; (e) at least one in the passivation layer.
Selectively producing a solder layer on the surface of the pair of electrical contacts; (f) the discrete electrical component such that the electrical contacts of the discrete electrical component are aligned with the selectively fabricated solder layer. Is placed on the selectively-prepared solder layer and in alignment with the selectively-prepared solder layer; and (g) flowing the selectively-prepared solder layer. Producing a solder ball connecting the discrete electrical component and at least one pair of electrical contacts at the passivation layer. 27. The method of claim 26, wherein the discrete electrical component is selected from the group including resistors, capacitors, and inductors. 28. (a) A semiconductor substrate having a semiconductor device formed in or on the surface thereof, the semiconductor substrate having electrical contacts provided in the semiconductor device in or on the active surface of the semiconductor substrate. A substrate; and (b) an overlaying interconnect metallization structure comprising one or more layers of interconnect on the active surface of the substrate, the layer of interconnect being the electrical contact Including conductive interconnect lines or contacts or conductive vias in one or more layers provided in or on the surface of the overlying interconnect metallization structure;
At least one of said electrical contacts in contact with at least one of said conductive interconnect lines or said conductive contacts or said conductive vias provided in said one or more layers of said overlaying interconnect metallization structure; At least one of the line or the contact or the conductive via;
An overlaying interconnect metallization structure contacting at least one of the electrical contacts on the semiconductor device in or on the surface of the substrate; and (c) on the overlaying interconnect metallization structure. (D) the passivation layer being substantially thicker than the passivation layer and substantially thicker than a dielectric intermediate layer used to fabricate the interconnect metallization structure. An insulating and isolating polymer layer deposited on the layer; (e) exposing at least one pair of the electrical contacts provided in or on the surface of the overlaying interconnect metallization structure; An opening formed through the insulating / separating polymer layer and through the passivation layer, the opening being filled with a conductive material. And opening the metal contacts are made through the opening; equipped with, is formed on a surface of the insulating-separating polymeric layer,
An inductor for a high performance integrated circuit overlaying the surface of a semiconductor substrate connected to at least one pair of the electrical contacts provided in or on the surface of the overlaying interconnect metallization structure. 29. The inductor of claim 28, wherein the size of the electrical contacts provided in or on the surface of the overlying interconnect metallization structure ranges from about 0.3 μm to about 50 μm. . 30. The passivation layer is about 0.15.
Plasma enhanced CV with thickness in the range of up to 2.0 μm
29. The inductor of claim 28, comprising a D (PECVD) oxide layer on which a PECVD nitride layer having a thickness in the range of about 0.5-2.0 [mu] m is deposited. 31. The inductor of claim 28, wherein the insulating / separating polymer layer comprises a polymer of polyimide or benzocyclobutene (BCB). 32. The thickness of the insulating / separating polymer layer after curing is in the range of about 1.0 to 150 μm.
8. The inductor according to 8. 33. The insulating / separating polymer layer is spin-on coated and cured.
The listed inductor. 34. The insulating / separating polymer layer is subjected to multiple treatment steps of spin-on coating and curing.
The inductor according to claim 28. 35. The electrical contacts provided in or on the surface of the overlaying interconnect metallization structure are sputtered aluminum, CVD tungsten, CVD copper, electroplated gold, electroplated copper, electroplated. 29. The inductor of claim 28, comprising a material selected from the group including silver, electroless gold, and electroless nickel. 36. The inductor of claim 28, wherein the inductor is embedded in a dielectric and further covered by a passivation layer. 37. The inductor of claim 36, wherein the dielectric is a low K dielectric. 38. A strength overlaying said passivation layer having a thickness greater than about 2,000 to 50,000 Angstroms and a surface area greater than a surface area over which said inductor substantially overlays said insulating and isolating polymer layer. Inserting one or more layers of the ferromagnetic material between the surface of the passivation layer and the insulating / separating polymer layer deposited thereon by adding one or more layers of magnetic material. The inductor according to claim 28. 39. The inductor is a spiral design and is made on the surface of the insulating / separating polymer layer and in a plane parallel to the surface of the insulating / separating polymer layer. 28. The inductor according to item 28. 40. The inductor of claim 28, wherein the inductor is made using a damascene process. 41. The inductor of claim 28, wherein the inductor is made using a photolithographic exposure and etching method. 42. A high performance integrated circuit capacitor on the surface of a semiconductor substrate, comprising: a top plate, a bottom plate, and a dielectric layer inserted between the top plate and the bottom plate, the capacitor comprising: A semiconductor substrate having a semiconductor device formed in or on the surface thereof, the semiconductor substrate having electrical contacts provided on the semiconductor device in or on the active surface of the semiconductor substrate; and (b) of the substrate. An overlaying interconnect metallization structure comprising one or more layers of interconnects on an active surface, the layer of interconnects having electrical contacts overlaying the interconnect metallization structure. A conductive interconnection line or contact or conductive via in one or more layers, provided in or on the surface of
At least one of said electrical contacts in contact with at least one of said conductive interconnect lines or said conductive contacts or said conductive vias provided in said one or more layers of said overlaying interconnect metallization structure; At least one of the line or the contact or the conductive via;
Contacting at least one of the electrical contacts on the semiconductor device in or on the surface of the substrate, the electrical contacts on the surface of the overlying interconnect metallization structure are even and odd. An overlaying interconnect metallization structure that is divided into pairs of adjacent contact points, whereby one electrical contact can belong to only one pair; and (c) the overlaying interconnect metallization structure. And (d) an opening made in the passivation layer, wherein at least one opening is provided in or on the surface of the overlaying interconnect metallization structure. An opening overlying at least one even number of said electrical contacts that are present; and (e) said made in said passivation layer. A first layer of conductive material deposited on a surface of the passivation layer including a mouth; (f) at the even number of locations provided in or on the surface of the overlaying interconnect metallization structure. An opening made in the first conductive material layer forming the bottom plate of the capacitor for at least one of the electrical contacts; and (g) the opening for at least one of the even numbered electrical contacts. A dielectric layer deposited on the surface of the first conductive material layer, including: (h) an opening in the dielectric layer for at least one of the even-numbered electrical contacts, the even-numbered location An opening that partially exposes at least one of the electrical contacts of and that forms the dielectric layer inserted between the top plate and the bottom plate; (i) at least one made in the dielectric layer. Two openings A second conductive material layer deposited on the surface of the included dielectric layer, the upper plate of the capacitor subjecting the second conductive material layer to patterning and etching. Capacitors made by 43. An insulating / separating polymer deposited on the patterned / etched passivation layer, on the surface of the patterned / etched passivation layer including the openings formed in the passivation layer. Layers and;
At least one opening made in the insulating and isolating polymer layer that is aligned with at least one of the even-numbered electrical contacts on the surface of the overlaying interconnect metallization structure; Claim 42
The listed capacitors. 44. The passivation layer is about 0.15.
Plasma enhanced CV with thickness in the range of up to 2.0 μm
43. The capacitor of claim 42, comprising a D (PECVD) oxide layer on which is deposited a PECVD nitride layer having a thickness in the range of about 0.5-2.0 [mu] m. 45. The capacitor of claim 43, wherein the insulating / separating polymer layer comprises a polymer of polyimide or benzocyclobutene (BCB). 46. The thickness of the insulating / separating polymer layer after curing is in the range of about 1.0 to 150 μm.
3. The capacitor described in 3. 47. The insulating / separating polymer layer is spin-on coated and cured.
The listed capacitors. 48. A resistor for a high performance integrated circuit on the surface of a semiconductor substrate, comprising: (a) a semiconductor substrate having a semiconductor device fabricated in or on the surface, A semiconductor substrate having electrical contacts provided to the semiconductor device in or on the active surface; and (b) an overlying interconnect metal comprising one or more layers of interconnect on the active surface of the substrate. An electrically conductive interconnect line or contact, wherein a layer of said interconnect is provided in or on the surface of said overlying interconnect metallization structure overlaid. Or including conductive vias in one or more layers,
At least one of said electrical contacts in contact with at least one of said conductive interconnect lines or said conductive contacts or said conductive vias provided in said one or more layers of said overlaying interconnect metallization structure; At least one of the line or the contact or the conductive via;
An overlaying interconnect metallization structure contacting at least one of the electrical contacts on the semiconductor device in or on the surface of the substrate; and (c) on the overlaying interconnect metallization structure. And (d) at least two openings made in the passivation layer, the passivation layer being deposited on the electrical contact at least in the surface of the overlaying interconnect metallization structure. (E) a resistive conductive material layer deposited on a surface of the passivation layer including the opening formed in the passivation layer; and (f) the opening formed in the passivation layer. A layer of conductive material interconnecting at least one pair of openings to make the resistor. 49. The passivation layer is about 0.15.
Plasma enhanced CV with thickness in the range of up to 2.0 μm
49. The resistor of claim 48 including a D (PECVD) oxide layer on which a PECVD nitride layer having a thickness in the range of about 0.5-2.0 [mu] m is deposited. 50. A resistor for a high performance integrated circuit on the surface of a semiconductor substrate, comprising: (a) a semiconductor substrate having a semiconductor device fabricated in or on the surface thereof, A semiconductor substrate having electrical contacts provided to the semiconductor device in or on the active surface; and (b) an overlying interconnect metal comprising one or more layers of interconnect on the active surface of the substrate. An electrically conductive interconnect line or contact, wherein a layer of said interconnect is provided in or on the surface of said overlying interconnect metallization structure overlaid. Or including conductive vias in one or more layers,
At least one of said electrical contacts in contact with at least one of said conductive interconnect lines or said conductive contacts or said conductive vias provided in said one or more layers of said overlaying interconnect metallization structure; At least one of the line or the contact or the conductive via;
An overlaying interconnect metallization structure contacting at least one of the electrical contacts on the semiconductor device in or on the surface of the substrate; and (c) on the overlaying interconnect metallization structure. (D) at least two of the openings made in the passivation layer, wherein at least two of the electrical contacts are provided in the surface of the overlaying interconnect metallization structure. An opening that overlays and partially exposes the pair; and (e) an insulating and isolating polymer layer deposited on the surface of the patterned and etched passivation layer that includes the opening made in the passivation layer. (F) aligned with at least one pair of openings made in the passivation layer, At least one pair of openings in the insulating and isolating polymer layer that partially exposes at least one pair of electrical contacts provided in the surface of the interconnecting interconnect metallization structure; and (g) the insulation. A conductive material layer deposited on the surface of the insulating / separating polymer layer including the opening formed in the separating polymer layer; and (h) at least one pair of the opening formed in the passivation layer. A resistive conductive material layer interconnected to make the resistor. 51. The passivation layer is about 0.15.
Plasma enhanced CV with thickness in the range of up to 2.0 μm
51. The resistor of claim 50, comprising a D (PECVD) oxide layer on which is deposited a PECVD nitride layer having a thickness in the range of about 0.5-2.0 [mu] m. 52. The resistor of claim 50, wherein the insulating and isolation polymer layer comprises a dielectric polymer including a polymer of polyimide or benzocyclobutene (BCB). 53. The cured insulating / separating polymer layer has a thickness in the range of about 1.0 to 150 μm.
The resistor described in 0. 54. The insulating / separating polymer layer is spin-on coated and cured.
The listed resistor. 55. The insulating / separating polymer layer is subjected to multiple treatment steps of spin-on coating and curing.
The resistor according to claim 50. 56. A discrete electrical component on the surface of a semiconductor substrate, comprising: (a) a semiconductor substrate having a semiconductor device fabricated in or on the surface, wherein the active surface or active surface of the semiconductor substrate is A semiconductor substrate having electrical contacts provided to the semiconductor device on a surface; and (b) an overlaying interconnect metallization structure including one or more layers of interconnect on the active surface of the substrate. A conductive interconnect line or contact or conductive via with a layer of the interconnect being provided in or on the surface of the overlying interconnect metallization structure. Including in one or more layers,
At least one of said electrical contacts in contact with at least one of said conductive interconnect lines or said conductive contacts or said conductive vias provided in said one or more layers of said overlaying interconnect metallization structure; At least one of the line or the contact or the conductive via;
An overlaying interconnect metallization structure contacting at least one of the electrical contacts on the semiconductor device in or on the surface of the substrate; and (c) on the overlaying interconnect metallization structure. (D) at least two of the openings made in the passivation layer, wherein at least two of the electrical contacts are provided in the surface of the overlaying interconnect metallization structure. A pair of overlays and an opening providing at least one pair of electrical contacts to the passivation layer; (e) deposited on the surface of the patterned and etched passivation layer including the openings made in the passivation layer. An insulating / separating polymer layer; At least one pair of openings made in the insulating and separating polymer layer and aligned with at least one pair of air contacts; and (g) on at least one surface of the electrical contacts brought to the passivation layer. A conductive substance layer selectively adhering to, filling the opening formed in the insulating / separating polymer layer to form a conductive plug through the insulating / separating polymer layer, wherein the conductive plug is At least one of the electrical contacts provided in the passivation layer
A conductive material layer overlaying the pair; and (h) a solder layer selectively made on the surface of the conductive plug; wherein the electrical contacts of the discrete electrical component are the selectively made solder. The discrete electrical component is disposed on the selectively-fabricated solder layer and in alignment with the selectively-fabricated solder layer so as to be aligned with the layer; A solder layer is flowed to produce solder balls that connect the conductive plugs in the insulating / separating polymer layer to the discrete electrical components, thereby forming a pair of electrical contacts in the passivation layer and the discrete electrical components. Discrete electrical equipment to which and are connected. 57. The passivation layer is about 0.15.
Plasma enhanced CV with thickness in the range of up to 2.0 μm
57. The discrete electrical component of claim 56, comprising a D (PECVD) oxide layer, on which a PECVD nitride layer having a thickness in the range of about 0.5-2.0 [mu] m is deposited. . 58. The discrete electrical component of claim 56, wherein the insulating / separating polymer layer comprises a polymer of polyimide or benzocyclobutene (BCB). 59. The cured insulating / separating polymer layer has a thickness in the range of about 1.0 to 150 μm.
Discrete electrical equipment according to item 6. 60. The insulating / separating polymer layer is spin-on coated and cured.
Discrete electrical components listed. 61. The insulating / separating polymer layer is subjected to multiple treatment steps of spin-on coating and curing.
57. The discrete electrical component of claim 56. 62. The discrete electrical component of claim 56, wherein the discrete electrical component is selected from the group including resistors, capacitors, and inductors. 63. A discrete electrical component mounted on the surface of a semiconductor substrate, comprising: (a) a semiconductor substrate having a semiconductor device fabricated in or on the surface, the active surface of the semiconductor substrate. A semiconductor substrate having electrical contacts provided to the semiconductor device in or on an active surface; and (b) an overlaying interconnect metallization structure including one or more layers of interconnect on the active surface of the substrate. A conductive interconnect line or conductive contact or conductive layer, wherein a layer of the interconnect is provided in or on the surface of the overlaying interconnect metallization structure. Including vias in one or more layers,
At least one of said electrical contacts in contact with at least one of said conductive interconnect lines or said conductive contacts or said conductive vias provided in said one or more layers of said overlaying interconnect metallization structure; At least one of the line or the contact or the conductive via;
An overlaying interconnect metallization structure contacting at least one of the electrical contacts on the semiconductor device in or on the surface of the substrate; and (c) on the overlaying interconnect metallization structure. (D) at least two of the openings made in the passivation layer, wherein at least two of the electrical contacts are provided in the surface of the overlaying interconnect metallization structure. An opening overlaying the pair to provide at least one pair of electrical contacts to the passivation layer; (e) a solder layer selectively deposited on the surface of the at least one pair of electrical contacts in the passivation layer;
And wherein the discrete electrical component is on the selectively deposited solder layer and selectively so that the electrical contacts of the discrete electrical component align with the selectively deposited solder layer. Disposed in alignment with the deposited solder layer; the selectively deposited solder layer is flushed, and at least one of the passivation layers
A discrete electrical component in which a solder ball for connecting a pair of electrical contacts to the discrete electrical component is produced. 64. The passivation layer is about 0.15.
Plasma enhanced CV with thickness in the range of up to 2.0 μm
64. The discrete electrical component of claim 63, comprising a D (PECVD) oxide layer, on which is deposited a PECVD nitride layer having a thickness in the range of about 0.5-2.0 [mu] m. . 65. The discrete electrical component of claim 63, wherein the discrete electrical component is selected from the group consisting of a resistor, a capacitor, and an inductor. 66. The method of claim 1, wherein the inductor is made to overlay the surface of a passivation layer, whereby no layer of polymer is applied. 67. The solenoid structure wherein the inductor overlays a polymer layer, the polymer layer overlaying a passivation layer.
The method described. 68. The method of claim 1, wherein the inductor is a solenoid structure overlaying a passivation layer, whereby a layer of polymer is not applied. 69. The method of claim 11, wherein the insulating and separating polymer layer is a dry laminate film. 70. The method of claim 15, wherein the insulating / separating polymer layer is a dry laminate film. 71. The method of claim 21, wherein the solder balls are made by electroplating, electroless plating, screen printing, and ball mounting. 72. The method of claim 21, wherein the insulating and separating polymer layer is a dry laminated film. 73. The inductor according to claim 28, wherein the insulating / separating polymer layer is a dry laminate film. 74. The inductor is a solenoid design made on the surface of the insulating / isolating polymer layer, the solenoid being an overlaying plane parallel to the surface of the insulating / isolating polymer layer. 29. The inductor of claim 28, comprising two patterned metal layers therein, the patterned metal layers being connected by vias, whereby the polymer layer is deposited on the surface of the passivation layer. 75. The inductor is a solenoid design made on the surface of the insulating / isolating polymer layer, the solenoid being a planar overlaying surface parallel to the surface of the insulating / isolating polymer layer. There are two patterned metal layers therein, the patterned metal layers being connected by vias, whereby the polymer layer is deposited on the surface of the polyimide layer, whereby the polyimide layer is a passivation layer. 29. The inductor according to claim 28 deposited on a surface. 76. The capacitor according to claim 43, wherein the insulating / separating polymer layer is a dry laminate film. 77. The resistor of claim 50, wherein said insulating / separating polymer layer is a dry laminate film. 78. The discrete electrical component of claim 56, wherein the insulating / separating polymer layer is a dry laminate film. 79. A conductive layer overlying the passivation layer having a thickness greater than about 1,000-50,000 angstroms and a surface area greater than a surface area over which the inductor substantially overlays the insulating and isolating polymer layer. Inserting one or more layers of the conductive material between the surface of the passivation layer and the insulating / separating polymer layer deposited thereon by adding one or more layers of the conductive material. The method according to claim 1. 80. The method of claim 1, wherein the inductor is a toroidal design and is fabricated on the surface of the insulating and isolating polymer layer. 81. A conductive layer overlying the passivation layer having a thickness greater than about 1,000-50,000 angstroms and a surface area greater than a surface area over which the inductor substantially overlays the insulating and isolating polymer layer. Inserting one or more layers of the conductive material between the surface of the passivation layer and the insulating / separating polymer layer deposited thereon by adding one or more layers of the conductive material. The inductor according to claim 28. 82. The inductor according to claim 28, wherein the inductor is a toroidal coil and is formed on the surface of the insulating / separating polymer layer. 83. The method of claim 1, wherein the inductor is a toroidal coil structure overlaying a polymer layer, the polymer layer overlaying a passivation layer. 84. The method of claim 1, wherein the inductor is a toroidal coil overlaying a passivation layer, whereby a layer of polymer is not applied. 85. The inductor of claim 28, wherein the inductor is a toroidal coil and is made on the surface of the insulating and isolating polymer layer, thereby depositing the polymer layer on the surface of the passivation layer. . 86. The inductor is a toroidal coil, made on the surface of the insulating / separating polymer layer, thereby depositing the polymer layer on the surface of the polymer layer, thereby passivating the polymer layer. 29. The inductor of claim 28 deposited on the surface of a layer.