JP5683765B2 - Integrated circuit chip and method of forming the same - Google Patents

Description

  This application is a continuation-in-part application of attorney docket MSLIN 98-002, U.S. Patent Application No. 09 / 216,791, filed December 21, 1998, assigned to a common assignee, dated February 17, 1999. Attorney docket MSLIN98-002C, part of continuation of US patent application No. 09 / 251,183 It is.

  The present invention relates to the manufacture of high performance integrated circuits (ICs), and more particularly, by reducing high frequency electrical components (eg, inductors) on the surface of a semiconductor substrate by reducing electromagnetic losses typically experienced at the surface of the semiconductor substrate. It relates to a method of manufacturing.

Problems to be solved by the prior art and the invention

  A constant emphasis in semiconductor technology is the manufacture of semiconductor devices with improved performance at low cost. These years of focused development have resulted in extreme miniaturization of semiconductor devices, a combination of semiconductor processes and the constant advances in semiconductor materials and high-performance new device designs. It was. Most of the semiconductor devices manufactured today are intended to process digital data. However, there are many semiconductor designs that are aimed at incorporating analog functionality in devices that process digital and analog data simultaneously, or in devices that can be used to process only analog data. One of the major problems in manufacturing analog processing circuits (using digital processing procedures and equipment) is that many of the elements used for analog circuits are generally submicron due to their large size. It is not easy to integrate into a device having a characteristic size close to The main elements that cause these problems are capacitors and inductors. This is because all of these elements are considerably larger in the case of a normal analog processing circuit.

  The inductor of the present invention is generally applicable in the field of the latest mobile communication applications using a compact high-frequency device. While continuous improvements in the performance characteristics of this device have been achieved over the years, it has reduced device power consumption, device size, usable operating frequency, and reduced noise levels. Emphasis will be placed on further improvements. One of the major uses of semiconductor devices in the field of mobile communications is in the manufacture of radio frequency (RF) amplifiers. An RF amplifier includes many standard elements. A main element of a general RF amplifier is a tuning circuit including an inductive element and a capacitive element. The tuning circuit depends on and depends on the values of the inductive and capacitive elements, but forms a frequency-dependent impedance, and the tuning circuit has a high impedance or A low impedance can be provided. Thus, the tuning circuit can reject or pass the analog signal component based on the frequency of the analog signal component, and can further amplify the analog signal component. The tuning circuit can be used in this manner as a filter to exclude or remove signals at a specific frequency or to remove noise from circuit components intended for analog signal processing. The tuning circuit can also be used to create a high electrical impedance by using the LC resonance of the circuit and thereby reduce the effects of parasitic capacitance that is part of the circuit. One of the problems that arise when fabricating inductors on the surface of a semiconductor substrate is high due to self-resonance caused by parasitic capacitance between the (helical) inductor and the underlying substrate. The use of inductors at frequencies is limited. In designing such an inductor, it is important to reduce electrostatic coupling between the fabricated inductor and the lower substrate.

  At high frequencies, the electromagnetic field generated by the inductor generates eddy currents in the lower silicon substrate. Since the silicon substrate is a resistive conductor, eddy currents consume electromagnetic energy and thus increase energy loss, resulting in a lower Q value for the capacitor. This is the main reason for the low Q value of the capacitor, so the resonance frequency of 1 / √ (LC) limits the upper frequency limit. In addition, eddy currents induced by the inductor interfere with the performance of circuits that are physically very close to the capacitor.

  As already pointed out, one of the important elements used in fabricating a high frequency analog semiconductor device is an inductor that forms part of an LC resonant circuit. In view of the high element density commonly found in semiconductor devices and the resulting intense use of the substrate surface area, inductors can be made for inductors while maintaining a high Q value for the inductor. It must incorporate minimizing the required surface area. In general, an inductor manufactured on the surface of a substrate has a spiral shape, whereby a spiral-shaped object is formed in a plane parallel to the plane of the substrate. Conventional methods used to make inductors on the surface of a substrate are subject to several limitations. Most inductors with high Q values form part of a hybrid device component or monolithic microwave integrated circuit (MMIC), or are made as discrete elements, but such fabrication is common in integrated circuits Integration into a simple manufacturing process is not easy. What can be said clearly is that by creating a circuit for the purpose of analog data manipulation and analog data storage on a single monolithic semiconductor substrate, and combining digital data manipulation and digital data storage functions, Many important benefits can be achieved. Such advantages include reduced manufacturing costs and reduced power consumption due to combined functions. However, because the shape of the inductor fabricated on the surface of the semiconductor substrate is spiral, due to the physical size of the inductor, a parasitic capacitance is generated between the inductor wiring and the lower substrate. A loss of electromagnetic energy is caused in the resistive silicon substrate on the side. These parasitic capacitances have a significant adverse effect on the functionality of the fabricated LC circuit by sharply reducing the resonant frequency of the tuning circuit being used. More seriously, the electromagnetic field generated by the inductor generates eddy currents in the lower resistive silicon substrate, which causes large energy loss and lowers the Q value of the inductor.

  Inductor performance parameters are generally expressed as inductor quality (Q) factors. The inductor quality factor Q is defined as Q = Es / El, where Es is the energy stored in the reactive portion of the device, and El is the energy lost in the reactive portion of the device. The higher the quality of the element, the closer the resistance value of the element approaches zero and the Q factor of the element approaches infinity. In the case of an inductor made with a silicon substrate overlaid, the electromagnetic energy created by the inductor is lost primarily in the underlying resistive silicon substrate and in the metal wire being made to form the inductor. . The quality factor for the element is different from the quality associated with the filter or resonator. For a device, the quality factor serves as a measure of the purity of the reactance (or susceptance) of the device. The purity of reactance (or susceptance) may be reduced due to resistive silicon substrate, metal wire resistance, and dielectric loss. In practical arrangements, there are always some physical resistors that dissipate energy, thereby reducing the recoverable energy. The quality factor Q is a dimensionless value. When the Q value is greater than 100, it is considered that the performance of the discrete inductor mounted on the surface of the printed circuit board is extremely high. For inductors that form part of an integrated circuit, the Q factor is typically in the range of about 3-10.

  When fabricating an inductor on a monolithic substrate on which additional semiconductor devices are fabricated, the parasitic capacitance that occurs as part of this fabrication limits the upper cutoff frequency that can be achieved for inductors using conventional silicon processes. Is done. For many applications, this limitation is unacceptable. Depending on the frequency at which the LC circuit is designed to resonate, a fairly large value of quality factor (eg 50 or more) must be obtained. In this regard, the prior art is limited to obtaining higher quality factor values as separate units and integrating these separate units and surrounding device functions. This negates the advantages obtained when using a monolithic structure in which the inductor and surrounding elements are made on one and the same semiconductor substrate. Non-monolithic approaches also require additional wiring to interconnect assembly sub-components, which introduces additional parasitic capacitance and resistive losses throughout the interconnecting network have. In many applications of RF amplifiers (eg battery powered applications) power consumption is an important point and should be as low as possible. Although increasing the power consumption can compensate to some extent for the effects of parasitic capacitance and resistive power loss, this approach also has limitations. With the rapid spread of wireless applications (such as mobile phones), there is a need for an immediate solution to these problems. Wireless communication is a rapidly expanding market, and integration of RF integrated circuits is one of the most important issues. One approach is to significantly increase the operating frequency, for example in the range of 10-100 GHz. At such high frequencies, the quality factor values obtained from silicon-based inductors are significantly reduced. For applications in these frequency ranges, monolithic inductors using materials other than silicon as the base for making inductors have been studied. Such a monolithic inductor is produced using, for example, sapphire or GaAs as a base. These inductors have significantly less substrate loss than their counterparts using silicon (no eddy currents and hence no loss of electromagnetic energy), and thus inductors with much higher Q values are obtained. These inductors also have lower parasitic capacitance and thus have the ability to operate at higher frequencies. However, there is still a need to make silicon based inductors when more complex applications are required. For these applications, approaches using base materials other than silicon have proved too complex and inefficient, for example GaAs as a medium for fabricating semiconductor devices still has to be solved. There are technical issues that must be solved. It has become apparent that GaAs is a semi-insulating material at high frequencies and reduces the electromagnetic losses that occur on the surface of the GaAs substrate, thereby increasing the Q value of inductors fabricated on the GaAs surface. Yes. However, since a GaAs RF chip is expensive, a process that does not require the use of a GaAs RF chip is advantageous in terms of cost.

  Many different approaches have been attempted to incorporate the inductor into the semiconductor environment without sacrificing device performance due to substrate loss. One of these approaches is to selectively remove the silicon under the inductor by etching (using microfabrication), thereby removing the effects of resistive energy loss and parasitic capacitance on the substrate. is there. Another method is to use multiple layers of metal (eg, aluminum) interconnects or copper damascene interconnects.

  Another approach uses a high resistivity silicon substrate, thereby reducing resistive loss in the silicon substrate. Resistive substrate loss at the surface of the lower substrate forms a major factor in determining the Q value of the silicon inductor. In addition, biased wells under the helical conductor have been proposed, which are also aimed at reducing induced losses at the surface of the substrate. A more complex approach is to create an active inductive element that simulates the electrical characteristics of the inductor when used in an active circuit. However, this latter approach results in high power consumption due to the simulated inductor and unacceptable noise for low power, high frequency applications. Both of these approaches have the common goal of increasing the quality (Q) value of the inductor and reducing the surface area required to make the inductor. The most important point in this regard is electromagnetic energy loss due to electromagnetically induced eddy currents in the silicon substrate.

  Reducing the size of the integrated circuit reduces the cost per die and improves some performance. Metal connections that connect integrated circuits to other circuits or system elements have become relatively important and, along with further miniaturization of ICs, have increasingly negative effects on circuit performance. ing. The parasitic capacitance and resistance of the metal interconnect increases, which significantly degrades chip performance. Most important in this regard is the voltage drop along the power and ground buses and the RC delay of the critical signal path. Attempting to reduce resistance by using wider metal lines results in greater capacitance of these wires.

  The latest method for fabricating an inductor on the surface of a semiconductor substrate is to fabricate the inductor under a passivation layer using a fine-line technique. However, this indicates that the physical distance between the fabricated inductor and the substrate surface on which the inductor is fabricated is extremely small (typically less than 10 μm), which results in large electromagnetic losses in the silicon substrate. Therefore, the Q value of the inductor is lowered. By increasing the distance between the inductor and the semiconductor surface, the electromagnetic field in the silicon substrate can be decreased inversely proportional to the distance, and the Q value of the inductor can be increased. Thus, by creating an inductor that overlays a passivation layer (by post-passivation method), and additionally, creating an inductor on the surface of a thick dielectric (eg polymer) layer that is deposited or adhered onto the surface of the passivation layer Thus, the Q value of the inductor can be increased. Furthermore, the parasitic resistance can be reduced by using a wide and thick metal to make the inductor. The method of the present invention applies these principles of post-passivation inductor fabrication, where the inductor is fabricated on a thick dielectric layer using a thicker and wider metal.

  US Pat. No. 5,212,403 (Nakanishi) shows a method of forming wiring connections for logic circuits depending on the length of the wiring connections on the inside and outside (in the wiring board on the chip).

  US Pat. No. 5,501,006 (Gehman, Jr. et al.) Shows a structure incorporating an insulating layer between an integrated circuit (IC) and a wiring board. The distribution lead wires connect the IC bonding pads to the substrate bonding pads.

  US Pat. No. 5,055,907 (Jacobs) describes an extended integration that allows circuits to be integrated across chip boundaries by forming thin film multilayer wiring decals on a support substrate and on a chip. A semiconductor structure is disclosed. However, this patent document is different from the present invention.

  US Pat. No. 5,106,461 (Volfson et al.) Teaches a multilayer interconnect structure comprising alternating combinations of polyimide (dielectric) and metal layers on an IC in a TAB structure.

U.S. Pat. No. 5,635,767 (Wenzel et al.) Teaches a method for reducing RC delay by PBGA isolating multiple metal layers.
US Pat. No. 5,686,764 (Fulcher) shows a flip chip substrate that reduces RC delay by isolating the power supply and I / O traces.

US Pat. No. 6,008,102 (Alfored et al.) Shows a spiral inductor that uses two metal layers connected by vias.
US Pat. No. 5,372,967 (Sundaram et al.) Discloses a helical inductor.

  US Pat. No. 5,576,680 (Ling) and US Pat. No. 5,884,990 (Burghartz et al.) Show other helical inductor designs.

Means for solving the problem

A primary object of the present invention is to improve the RF performance of high performance integrated circuits.
Another object of the present invention is to provide a method for producing an inductor having a high Q value.

Another object of the present invention is to replace a GaAs chip with a silicon chip as a base for producing an inductor having a high Q value.
Still another object of the present invention is to widen the frequency range of inductors fabricated on the surface of a silicon substrate.

Yet another object of the present invention is to produce a high quality passive electrical device that overlays the surface of a silicon substrate.
In this continuation application, in a post-passivation sequence, a thick layer of dielectric is added over the passivation layer and a wide and thick metal line is added over the thick layer of dielectric. The present invention extends the continuation-in-part application to a wider range by further fabricating high quality electrical elements (eg, inductors, capacitors, or resistors) on the passivation layer or on the surface of the thick dielectric layer. Yes. The method of the present invention further provides a method for mounting discrete passive electrical elements at a distance substantially away from the underlying silicon surface.

  This continuation-in-part application teaches an integrated circuit structure in which a re-distribution layer and an interconnect metal layer are made in a dielectric layer on the surface of a conventional IC. A passivation layer is deposited on the dielectric of the redistribution layer and the interconnect metal layer, and a thicker polymer layer is deposited on the surface of the passivation layer. In the present invention, high quality electrical elements are made on the surface of a thick polymer layer.

  The present invention is, among other things, manufacturing an inductor using a manufacturing method and manufacturing procedure of a semiconductor device well known in the prior art (making an inductor having a high Q value on the surface of a semiconductor substrate). Emphasis is put on). Since the inductor of the present invention is of high quality, it can be used for high frequency applications while minimizing power loss. The present invention further addresses the fabrication of capacitors and resistors on the surface of a silicon substrate (thus the main purpose of the method of the present invention for fabricating capacitors and resistors is in the underlying silicon substrate. To reduce the parasitics typically caused by the device).

  Referring to FIG. 1 for more specific explanation, a cross section of one embodiment of the present application is shown. Transistors and other elements (not shown in FIG. 1) are provided on the surface of the silicon substrate 10. The surface of the substrate 10 is covered with a dielectric layer 12, so that the dielectric layer 12 adheres in the surface of the substrate 10 and on the elements provided on the substrate 10. Conductive interconnect lines 11 are provided inside the layer 12, and these lines are connected to a semiconductor device provided on the surface of the substrate 10.

  Layer 14 (two examples are shown) shows all of the metal and dielectric layers that are typically fabricated on the dielectric layer 12, so the layer 14 shown in FIG. A plurality of dielectric layers or insulating layers, etc., and the conductive interconnect lines 13 constitute a network of electrical connections made throughout layer 14. Electrical contacts 16 are present on the surface of layer 14 overlaying layer 14. These electrical contacts 16 may be, for example, bonding pads that reliably form electrical interconnects for transistors and other devices provided on the surface of the substrate 10. These electrical contacts 16 are interconnect points within the IC assembly that need to be further connected to surrounding circuitry. A passivation layer 18 (eg, formed of silicon nitride) is deposited on layer 14 to prevent the lower layer from moisture, contamination, and the like.

  An important step of the application begins with depositing a thick polyimide layer 20 (depositing on the surface of layer 18). Access to the electrical contacts 16 must be provided, so that the pattern of the openings 22, 36, and 38 is etched through the polyimide layer 20 and the passivation layer 18, and the pattern of the openings 22, 36, and 38 is Align with the pattern. The electrical contacts 16 are electrically extended to the surface of the layer 20 by openings 22/36/38 made in the polyimide layer 20.

The material used for the deposition of layer 20 is polyimide, but the material that can be used for this layer is not limited to polyimide and includes any known polymer (eg, SiCl _x O _y ). The above polyimide is a preferred material to be used for the method of the present invention in making the thick polymer layer 20. Examples of polymers that can be used include silicons, carbons, fluorides, chlorides, oxygens, parylene or Teflon (R), polycarbonate (PC), Examples include polystyrene (PS), polyoxide (PO), poly polooxide (PPO), and benzocyclobutene (BCB).

  Electrical contact with the contacts 16 can be ensured by filling the openings 22/36/38 with a conductive material. The upper surface 24 of these metal conductors is included in the openings 22/36/38 and can be used to connect the IC to its environment and to further integrate into the surrounding electrical circuitry. This latter description allows the semiconductor device provided on the surface of the substrate 10 to be further connected to surrounding elements and circuits via conductive interconnects contained in the openings 22/36/38. Is the same as saying. Interconnect pads 26 and 28 are formed on the surface 24 of the metal interconnect housed in openings 22, 36, and 38. These pads 26 and 28 may be designs having any width and thickness as long as they can accommodate specific circuit design requirements. One pad can be used as, for example, a flip chip pad. Other pads can be used for power distribution or as a ground or signal bus. For example, as shown in FIG. 1, the following connections can be made into pads: pad 26 can function as a flip chip pad and pad 28 can function as a flip chip pad. Or a power source, a ground terminal, or an electrical signal bus. There is no relationship between the size of the pad shown in FIG. 1 and the possible electrical connections that can use this pad. The pad size, standard practice, and constraints on designing the electrical circuit determine whether an electrical connection can be obtained for which a given pad is useful.

  The following description relates to the size and number of contacts 16 in FIG. Since these contacts 16 are located on a thin dielectric (layer 14 in FIG. 1), the pad size should not be too large. This is because a large capacitance is generated when the pad size is large. In addition, a large pad size hinders the routing capability of the metal layer. Therefore, it is preferable to keep the size of the pad 16 relatively small. However, the size of the pad 16 is further directly related to the aspect ratio of the vias 22/36/38. Considering that via etching and via filling are applied, an acceptable aspect ratio is about 5. Based on these considerations, the size of the contact pad 16 is on the order of 0.5 μm to 30 μm, and the exact size depends on the thickness of the layers 18 and 20.

  This application does not limit the number of contact pads that can be incorporated into a design, and this number depends on package design requirements. Layer 18 in FIG. 1 may be a general IC passivation layer.

  The most commonly used passivation layers in the state of the art are the plasma enhanced CVD (PECVD) oxide layer and the plasma enhanced CVD nitride layer. In forming the passivation layer 18, a PECVD oxide layer of about 0.2 μm is first deposited, and then a nitride layer of about 0.7 μm is deposited. The passivation layer 18 is extremely important because it protects the device wafer from ionic contamination by moisture and foreign matter. It is very important to place this layer between the sub-micron process (for integrated circuits) and the tens-micron process (for interconnected metallization structures). This is because a cheaper process with less stringent clean room requirements is possible for the process of making interconnected metallized structures.

  Layer 20 is a thick polymer (eg polyimide) dielectric layer having a thickness (after curing) greater than 2 μm. The range of polymer thickness can be from 2 μm to 150 μm, depending on the electrical design requirements.

  For the deposition of the layer 20, for example, polyimide HD2732 or 2734 made by Hitachi-DuPont can be used. The polyimide can be spin-on coated and can be cured. After spin-on coating, the polyimide is cured at 400 ° C. for about 1 hour in a vacuum or nitrogen atmosphere. In order to obtain a thicker polyimide layer, the polyimide film is coated multiple times and cured.

  Another material that can be used to make layer 20 is a polymer of benzocyclobutene (BCB). This polymer is currently manufactured industrially, for example by Dow Chemical Company, and it has recently become clear that it can be used in place of general polyimide applications.

  There are various opinions on the dimensions of the openings 22, 36, and 38. The aspect ratio of the opening is determined by the dimension when the opening and the dielectric thickness are combined. This aspect ratio creates a problem with via etch process and metal filling capability. As a result, the diameter for opening 22/36/38 may range from about 0.5 μm to 30 μm, and the height for opening 22/36/38 may range from about 2 μm to 150 μm. The aspect ratio of the openings 22/36/38 is designed so that the via can be filled with metal. Vias can be filled with CVD metal (eg, CVD tungsten or CVD copper), with electroless nickel, with damascene metal filling, or with electroplated copper.

  By applying multiple polymer (eg polyimide) layers, the application can be further expanded and therefore also adapted to a wider variety of applications. The function of the structure shown in FIG. 1 can be further expanded by depositing a second polyimide layer over the previously deposited layer 20 and overlaying pads 26 and 28. Additional contacts that can be interconnected to pads 26 and 28 can be made on the surface of the second polyimide layer by selective etching and metal deposition. Additional polyimide layers and contact pads made thereon can be customized for specific applications, and the expanded use of multiple polyimide layers greatly increases the versatility and usefulness of this continuation-in-part application.

  FIG. 1 illustrates the basic design advantages of this continuation-in-part application. These advantages allow a sub-micron or fine line passing in close proximity to the metal layer 14 and the contact 16 to extend upward 30 through the metal interconnect 36. This extension continues in direction 32 in the horizontal plane of the metal interconnect 28 and returns to the lower 34 via the metal interconnect 38. The functions and structures of the passivation layer 18 and the insulating layer 20 are as described above. The basic design advantage of the present invention is that the thin wire interconnects are “elevate” or “fan-out” and these interconnects are taken from the micro and sub-micro levels. It is to be removed to the level of metal interconnects (which have much larger dimensions and therefore have lower resistance and capacitance, are easier to manufacture and are more cost effective). This aspect of the present application does not include any aspect of performing line re-distribution and thus has the inherent property of simplicity. Thus, this aspect further increases the importance of this application in that it allows micro and sub-micro wiring to be accessed at the level of wide and thick metals. Interconnects 20, 36, and 38 rise through the passivation layer and the polymer or polyimide dielectric layer, continue to extend over a distance on a wide and thick metal level, and fine from a wide and thick metal level. Fine levels of metal are interconnected by continuing to extend down through the passivation layer and the polymer or polyimide dielectric layer to the correct metal level. The extension made in this way need not be limited to extending to a specific type of fine metal interconnect point 16 (eg, signal or power or ground) that includes wide and thick metal lines 26 and 28. . The types of interconnects that can be reliably established in this way are constrained (if any) by laws of physics and electronics, and the limit factor is the resistance Conventional electrical constraint factors such as propagation delay, RC constant, and other factors. The present application is important in that the continuation-in-part application gives a much wider tolerance in that these laws can be applied, and in doing so, regarding the use and use of the integrated circuit and the circuit The result is a considerably expanded range for adapting to a wide and thick metal environment.

  FIG. 2 shows how the basic interconnect aspect of this continuation application not only raises the fine metal to a wide and thick metal plane according to the present invention, but also on the surface of the thick polyimide layer 20. It shows how it can be expanded to add inductors. The inductor is made in a plane that is parallel to the surface of the substrate 10 and that is separated from the surface of the substrate 10 by the combined height of the layers 12, 14, 18, and 20. FIG. 2 shows a cross section 40 of the inductor when cut in a plane perpendicular to the surface of the substrate 10. Wide and thick metals also contribute to energy loss savings due to resistance. In addition, low resistivity metals (eg, gold, silver, and copper) can also be applied using electroplating methods, and their thickness can be about 20 μm.

  FIG. 3 shows a plan view 42 of the spiral structure of the inductor 40 fabricated on the surface of the dielectric layer 20. The cross section of the inductor 40 in FIG. 2 is a view taken along line 2-2 'in FIG. The method used to make the inductor 40 is a conventional method of depositing metal (eg, gold or copper) by electroplating or metal sputtering.

  FIG. 4 shows a plan view of the inductor 40, which is further isolated from the surface of the substrate 10 by adding a layer 44 of ferromagnetic material. An opening is made in the layer of ferromagnetic material 44 for the conductors 36 and 38, which can be measured experimentally, and the type and layer of material used (shown in the cross section of FIG. 4). To produce a structure that is affected and to some extent dependent on the thickness of the ferromagnetic material (eg, used to overlay the layer 20). It is. The surface area of the ferromagnetic material layer 44 generally extends over the surface of the layer 18 so that the inductor 40 is aligned with the layer 44 and overlays the layer 44, with the surface area of the layer 44 somewhat beyond these boundaries. This further improves the point that the surface of the substrate 10 is shielded from the electromagnetic field of the inductor 40.

  Layer 44 is not limited to a layer of ferromagnetic material, and may be a layer of good conductor (eg, but not limited to gold, copper and aluminum). The overlaying inductor 40 is fabricated on the surface of the polyimide layer 20 and can be isolated from the underlying silicon substrate 10 by a layer 44 comprising ferromagnetic or good conductors.

FIG. 5 shows, for the sake of clarity, a simplified cross section of a substrate and a layer made on the surface of the substrate according to the method of the present invention. The highlighted area is as defined above. That is,
−10 is a silicon substrate,
-12 is a dielectric layer deposited on the surface of the substrate;
−14 is an interconnect layer including interconnect lines, vias, and contacts;
-16 is a contact on the surface of the interconnect layer 14,
−18 is a passivation layer in which an opening accessible to the contact 16 is made,
−20 is a thick polymer layer, and −21 is a conductive plug provided through the polyimide layer 20.

  The thick polymer layer 20 can be applied in liquid form on the surface of the passivation layer 18 or can be laminated by applying a dry film on the surface of the passivation layer 18. The vias required to make the conductive plug 21 can be made by a conventional photolithography process or can be made using laser (drill) technology.

  As is apparent from the above description, the layer arrangement shown in the cross section of FIG. 5 is such that additional electrical elements such as inductors and capacitors are electrically connected to the surface of the polyimide layer 20 and to the conductive plug 21. It is built so that it can be manufactured in a state in contact with. The dielectric layer 12 in the cross section shown in FIG. This is because the layer 14 is an Intra Level Dielectric (ILD) layer on which the layer 12 can be easily integrated.

  For the cross section shown in FIG. 6, the same layers as described with respect to FIG. Further shown is an upper layer 17 of the silicon substrate 10 containing active semiconductor devices. Further, a cross section of an inductor 19 that is fabricated on the surface of the passivation layer 18 is shown. Again, it is emphasized that the ohmic resistance of the metal used for the inductor 19 must be as low as possible. For this reason, it is preferable to use a thick layer of gold for the formation of the inductor 19, for example. A thick layer of gold has been shown to increase the Q value of inductor 19 from about 5 to about 20 for 2.4 GHz applications, which is a substantial improvement in the Q value of inductor 19. Is shown.

  FIG. 7 shows a cross section of a capacitor fabricated on the surface of the substrate 10. A layer 14 containing conductive interconnect lines and contacts is fabricated on the surface of the substrate 10. A passivation layer 18 is deposited on the surface of the layer 14 and an opening is made in the passivation layer 18 that allows access to the surface of the contact pad 16.

As is well known, a capacitor includes a lower plate, an upper plate, and a dielectric layer that separates the upper and lower plates. These components of the capacitor can be easily identified from the cross section shown in FIG.
−42 is a conductive layer forming the lower plate of the capacitor;
−44 is a conductive layer forming the upper plate of the capacitor;
−46 is a dielectric layer that separates the capacitor upper plate 44 from the lower plate 42.

  It should be noted that the capacitor is fabricated on the surface of the passivation layer 18, as can be seen from the cross section shown in FIG. 7, and thus this method of fabricating the capacitor includes a post-passivation processing sequence and be called. The processing conditions and materials that can be used to make the individual layers 42, 44, and 46 have already been described and therefore need not be described in further detail here.

The important points are the various thicknesses to which the three layers 42, 44 and 46 can be deposited, as follows.
The thickness of the passivation layer 18 is about 0.1 to 0.3 μm;
The thickness of the conductive material layer 42 is about 0.5-20 μm;
The thickness of the dielectric layer 44 is about 500 to 10,000 angstroms, and the thickness of the one conductive material layer 46 is about 0.5 to 20 μm;

The capacitor produced by the post-passivation method shown in the cross section in FIG.
-Reducing the parasitic capacitance between the capacitor and the underlying silicon substrate;
-Enabling the use of a thick layer of conductive material (this reduces the resistance of the capacitor; this is particularly important in wireless applications), and-the dielectric between the upper and lower plates of the capacitor As a result, it is possible to use a high dielectric material (for example, TiO ₂ or Ta ₂ O ₅ ) (as a result, the capacitance value of the capacitor becomes higher).

FIG. 8 shows a three-dimensional view of the solenoid structure of the inductor 19 fabricated on the surface of the passivation layer 18. What is further emphasized in FIG.
-23, a via made in the thick polymer layer 20 of FIG. 5 for interconnecting the upper and lower metal levels of the inductor,
-25, the bottom metal of the inductor, and -27, the top metal for the inductor.

  FIG. 9 shows a passivation layer 18 by first depositing a thick layer 29 of polymer, depositing a polymer layer (not shown) thereon, and creating vias 23 in the thick layer of polymer 20 (FIG. 5). FIG. 3 shows a three-dimensional view of an inductor fabricated on the surface of. FIG. 9 shows a polyimide layer 29 in addition to the layers highlighted above. Inductor 19 is made by building up via 23 made in bottom metal 25 of inductor 19, top metal 27 of the inductor, and layer 20 (FIG. 5), which preferably includes a polymer.

  FIG. 10 shows a plan view when an inductor is fabricated on the surface of the layer 20, as already shown in FIG. Vias 23 are highlighted as well as top metal line 27 of inductor 19 and bottom metal line 25 of inductor 19 (hatched because it is not visible on the surface of layer 20). More specifically, for vias 23 ′ and 23 ″, the lower end of via 23 ′ and the upper end of via 23 ″ are connected to interconnect lines 31 and 33 (FIG. 11), respectively. 19 connections for further interconnections.

  FIG. 11 shows a cross-section of the structure of FIG. 10 taken along line 6e-6e 'shown in FIG. Contact pads 16 'are provided on the surface of the passivation layer 18, such contact pads 16' for vias 23, 23 for interconnection between the bottom metal 25 of the inductor 19 and the top metal 27 of the inductor 19. In contact with 'and 23 ". Interconnects to vias 23' and 23" are lines 31 and 33, which connect the inductor 19 to the surrounding circuitry or elements as described above.

  Fabrication of a toroidal inductor overlying the passivation layer is shown in FIGS. 12 and 13 where a toroidal coil 19 ′ is fabricated on the surface of the passivation layer 18. The upper level metal 27 ', the bottom level metal 25', and vias 23 'interconnecting the bottom level metal 25' and the upper level metal 27 'are highlighted in FIG.

  FIG. 13 shows a plan view of the toroidal 19 'of FIG. 12 for further explanation. The highlighted features of this figure have been described above and therefore need not be described further here.

  FIG. 14 shows a cross section when a capacitor is formed on the surface of the substrate 10 as shown in FIG. However, in the cross-section shown in FIG. 14, a thick polyimide layer 20 is deposited on the surface of the passivation layer 18, and patterning and etching is performed to create a contact pad 16 accessible through the thick polyimide layer 20. Processing has been applied. A thick polymer layer 20 separates most of the capacitor. That is, the lower plate 42, the upper plate 44, and the dielectric 46 are separated from the surface of the substrate 10 by a distance equal to the thickness of the layer 20. As mentioned above, the polyimide thickness range may vary from 2 μm to 150 μm, depending on the electrical design requirements. This description also applies to the cross section shown in FIG. 14, so that each layer of the capacitor can be separated from the surface of the substrate 10 by a distance of 2 μm to 150 μm. As a result, the distance between the capacitor and the underlying silicon substrate will be greatly increased, and thus obviously the parasitic capacitance will be greatly reduced.

FIG. 15 shows a cross section of the substrate 10 when the passivation layer 18 is attached on the surface of the substrate 10 and the resistor 48 is formed on the surface of the passivation layer 18. As is well known, resistors are made by connecting two points with a substance that produces an electrical resistance to the passage of current. Two portions of the resistor 48 shown in cross section in FIG. 15 are contact pads 16 fabricated in or on the surface of the interconnect layer 14. Resistors were made according to the method of the present invention by interconnecting the two contact pads and creating a layer 48 between the two contact pads that adheres to the surface of the passivation layer 18. To make layer 48, a high resistivity material (eg, TaN, silicon nitride, phosphosilicate glass (PSG), silicon oxynitride, aluminum, aluminum oxide (Al _x O _y ), tantalum, niobium, or molybdenum). ) Can be used. The dimensions (eg, thickness, length, and width) of the deposition of the high resistivity material layer 48 depend on the application and are therefore not specified here. The resistor shown by the cross section in FIG. 15 is produced by the post-passivation method on the surface of the passivation layer 18 as in the case of the capacitors of FIGS.

  FIG. 16 shows a cross section of the substrate 10, with the interconnect layer 14 formed on the surface of the substrate. A passivation layer 18 is deposited on the interconnect metal layer 14 and a thick polyimide layer 20 is deposited on the surface of the passivation layer 18. A resistor 48 is fabricated on the surface of the polyimide layer 20. Resistor 48 is fabricated with two contact pads 16 connected to a thin metal layer having a high resistivity. By increasing the distance between the resistor body and the substrate surface (by increasing the thickness of the polyimide layer 20), the parasitic capacitance between the resistor body and the substrate is reduced, and thus improved resistance. Components are obtained (reduction of parasitic capacitance loss, improvement of high frequency performance).

A further application of the post-passivation method of the present invention is illustrated in FIGS. 17 and 18, with an emphasis on creating a ball contact between the contact pad 16 and an overlying electrical element (eg, a discrete inductor). I put it. Most of the layers of FIG. 17 from the surface of the substrate 10 upward are identified in FIG. 17 using the same reference numerals used above for the three layers. What has not yet been identified in FIG.
-50, a contact plug formed through the thick polymer layer 20,
-52, a conventional solder deposition method (electroplating or ball mounting on the surface of the plug 50, flux on the deposited solder, and flow of the solder to form the contact ball 52) Is a cross-section of a contact ball formed on the surface of the contact plug 50, and -54, a discrete electrical element (eg, an inductor or a discrete capacitor or resistor).

  FIG. 18 shows a cross section of the silicon substrate 10, where a discrete electrical element 54 is mounted on the substrate surface and a contact ball 56 is used, thereby providing a gap between the substrate 10 and the electrical element 54. The distance is a considerable value. A contact ball is inserted into an opening made in the passivation layer 18 overlaying the contact pad 16, and this (relatively large) contact ball 56 is connected to the surface of the substrate 10 and the discrete electrical element 54. Provides a considerable degree of isolation during

The method shown in FIGS. 17 and 18 is
The passive element 54 is at a considerable distance from the surface of the substrate 10, and, instead of mounting the discrete passive element 54 on the surface of the printed circuit board (PCB), the present invention is closer to the semiconductor device This shows that the passive element 54 can be mounted.

The following points have been emphasized throughout the methods and procedures described above with reference to the embodiments shown in cross-section in the accompanying drawings:
-Further moving passive elements away from the silicon substrate, thereby reducing the negative effects caused by the substrate due to electromagnetic losses experienced by the substrate;
-The post-passivation method of the present invention allows the selection of discrete element design parameters, which results in a decrease in the resistance of the discrete capacitor and the discrete inductor. This becomes even clearer from the following comparison between the prior art method and the method of the present invention.

  The prior art requires the use of thin metals to make the inductor, which requires the creation of a wide coil for the inductor, which increases the surface area required for the inductor, and thus the parasitic nature of the inductor. The capacitance increases, which causes eddy current loss at the substrate surface.

  In contrast, the present invention allows the use of thick metal since the metal of the passive element is away from the (thin metal) interconnect layer 14 (by the thick polymer layer) and is therefore required for the inductor. Less surface area is required, and the resistivity of the inductor is reduced, thereby increasing the Q value of the inductor.

  While the preferred embodiment of the present invention has been described and described in detail, various modifications may be made by those skilled in the art without departing from the spirit of the invention and without departing from the scope of the appended claims. Needless to say, deformation is possible.

  FIG. 1 shows a cross-section of the inventive interconnection scheme according to this continuation-in-part application.   FIG. 2 shows a cross-section when the present continuation application that the inductor is made on the surface of the thick polyimide layer is expanded.   FIG. 3 shows a plan view of an inductor made according to the method of the present invention.   FIG. 4 shows a cross section of the layer overlaying the substrate, where the inductor is fabricated on the surface of the thick polyimide layer, and an additional layer of ferromagnetic material is added to insulate the inductor from the underlying silicon substrate. It has been.   FIG. 5 shows a cross-section in the case where the multiple layers produced on the substrate surface and the substrate are simplified using the method of the present continuation-in-part application.   FIG. 6 shows the cross-section of FIG. 5 when an inductor is added over the passivation layer.   FIG. 7 shows a cross section when a passivation layer is deposited on the surface of the substrate, and a capacitor is formed on the surface of the passivation layer.   FIG. 8 shows a three-dimensional view of an inductor made on the surface of the passivation layer by making vias in a thick polymer layer.   FIG. 9 shows a three-dimensional view of an inductor made in a thick polymer layer deposited on the surface of a thick polyimide layer.   FIG. 10 shows a plan view when an inductor is fabricated on the surface of the layer 20.   FIG. 11 shows a cross-section of the structure of FIG. 10 taken along line 6e-6e 'of FIG.   FIG. 12 shows a three-dimensional view of the inductor fabricated on the surface of the passivation layer, where the inductor has the shape of a solenoid.   FIG. 13 shows a plan view of the inductor of FIG.   FIG. 14 shows a cross-section when a passivation layer is deposited on the surface of the substrate, a thick polyimide layer is deposited on the passivation layer, and a capacitor is fabricated on the surface of the thick polyimide layer.   FIG. 15 shows a cross section when a passivation layer is deposited on the surface of the substrate and a resistor is fabricated on the surface of the passivation layer.   FIG. 16 shows a cross-section when a passivation layer is deposited on the surface of the substrate, a thick polyimide layer is deposited on the passivation layer, and a resistor is fabricated on the surface of the thick polyimide layer.   FIG. 17 shows that a discrete electrical element is mounted on the surface of a silicon substrate, contact balls are used, and the distance between the substrate and the electrical element becomes a considerable value, and a thick polyimide layer is used. The cross section in the case where it is said is shown.   FIG. 18 shows that discrete electrical elements are mounted on the surface of a silicon substrate, thick contact balls are used, resulting in a considerable distance between the substrate and the electrical elements, and a polyimide layer is used. The cross section in the case of not being shown is shown.

Claims (27)

A semiconductor substrate;
A number of semiconductor devices in or on the surface of the semiconductor substrate, wherein the number of semiconductor devices includes transistors;
A metallized structure on the semiconductor substrate, wherein the metallized structure is included in the multiple semiconductor devices.
Connect the metallization structure comprises a second metal layer on the first metal layer and the first metal layer, and a metallization structure;
A dielectric layer between the first and second metal layers;
A passivation layer on the metallized structure and on the dielectric layer, wherein the passivation layer comprises a nitride layer;
A polymer layer on the passivation layer, wherein the polymer layer has a thickness of 2 to 150 micrometers that exceeds a thickness of the passivation layer and exceeds a thickness of the dielectric layer; A first opening in and in the passivation layer is over the first pad of the metallization structure and exposes the first pad, and a first opening in the polymer layer and in the passivation layer. Two openings are on the second pad of the metallized structure.
A polymer layer, exposing the second pad , the first and second pads being separated from each other by an insulating material ;
A first conductive structure connected to the first pad through the first opening;
A second conductive structure connected to the second pad through the second opening;
A first solder joint on the surface of the first conductive structure;
A second solder joint on the surface of the second conductive structure;
Passive elements on the polymer layer and on the first and second solder joint surfaces, the receiver
Moving element is connected to the first pad through the first conductive structure by connecting the first solder joint and directly, the passive element, the second solder joint and direct connection A passive element connected to the second pad through the second conductive structure by;
An integrated circuit chip.
The integrated circuit chip of claim 1, wherein the polymer layer comprises polyimide.
2. The integrated circuit chip of claim 1, wherein the polymer layer is benzocyclobutene (BC).
B) an integrated circuit chip.
2. The integrated circuit chip of claim 1, wherein the passive element includes a capacitor.
2. The integrated circuit chip according to claim 1, wherein the passive element includes an inductor.
The integrated circuit chip according to claim 1, wherein the passive element includes a resistor.
2. The integrated circuit chip of claim 1, wherein the nitride layer has a thickness of 0.5-2 micrometers.
The integrated circuit chip of claim 1, wherein the passivation layer includes an oxide layer under the nitride layer.
A semiconductor substrate;
A number of semiconductor devices in or on the surface of the semiconductor substrate, wherein the number of semiconductor devices includes transistors;
A metallized structure on the semiconductor substrate, wherein the metallized structure is included in the multiple semiconductor devices.
Connect the metallization structure comprises a first metal layer and second metal layer on said first metal layer, and a metallization structure;
A dielectric layer between the first and second metal layers;
A passivation layer on and the dielectric layer on the metallization structure, the passivation <br/> Shon layer includes a nitride layer, a first opening of the passivation layer, the metal structures On the first pad of the object , exposing the first pad , and a second opening in the passivation layer is on the second pad of the metallized structure, and the second pad A passivation layer, wherein the first and second pads are separated from each other by an insulating material ;
A first conductive structure connected to the first pad through the first opening;
A second conductive structure connected to the second pad through the second opening;
A first solder joint on the surface of the first conductive structure;
A second solder joint on the surface of the second conductive structure;
A passive element on the passivation layer and on the first and second solder joint surfaces, wherein the passive element is directly connected to the first solder joint through the first conductive structure. connected to the first pad Te, the passive element is connected to the second pad via the second conductive structure by connecting directly to the second solder joint,
With passive elements ;
An integrated circuit chip.
The integrated circuit chip according to claim 9 , wherein the passive element includes a capacitor.
10. The integrated circuit chip according to claim 9 , wherein the passive element includes an inductor.
The integrated circuit chip according to claim 9 , wherein the passive element includes a resistor.
The integrated circuit chip of claim 9 , wherein the nitride layer has a thickness of 0.5-2 micrometers.
The integrated circuit chip of claim 9 , wherein the passivation layer includes an oxide layer under the nitride layer.
A method of forming an integrated circuit chip, the method comprising :
Comprising: providing a wafer, the wafer includes a semiconductor substrate, includes a number of semiconductor devices in or on the semiconductor substrate, wherein one of the plurality of semiconductor device transistor, on said semiconductor substrate It includes a metallization structure, the metallization structure is connected to said plurality of semiconductor devices, the metallization structure, the first metal layer and second metal layer on said first metal layer, wherein A dielectric layer between the first and second metal layers, and a passivation layer on and on the metallized structure, wherein the first opening in the passivation layer includes the metallized structure Overlying the first pad of the object , exposing the first pad , and a second opening in the passivation layer overlying the second pad of the metallization structure ; Pack
Exposing the first and second pads, the first and second pads are separated from each other by an insulating material, and the passivation layer includes a nitride layer;
And forming a first first conductive structure on the pad and the second conductive structure on the second pad, the first conductive structure, the first of connected to the through openings first pad, the second conductive structure is connected to the second pad through said second opening, and a step;
Forming a solder layer on the first and second conductive structures;
Wherein on the passivation layer and the method comprising the steps of placing a passive element on the solder layer, the first contact of the passive element is located on said solder layer on the first conductive structure, the receiving
A second contact of a moving element is on the solder layer on the second conductive structure;
Flowing the solder layer, between the first solder interconnect between the first contact and the first conductive structure and between the second contact and the second conductive structure. Generating a second solder interconnect, wherein the first contact is directly connected to the first solder interconnect via the first conductive structure. connected to the pad, the second contact is connected to the second pad via the second conductive structure by connecting directly to the second solder interconnection thereof, the steps;
Including a method.
16. The method of claim 15 , wherein placing the passive element comprises placing a capacitor over the passivation layer and over the solder layer.
16. The method of claim 15 , wherein placing the passive element comprises placing an inductor over the passivation layer and over the solder layer.
16. The method of claim 15 , wherein placing the passive element comprises placing a resistor over the passivation layer and over the solder layer.
16. The method of claim 15 , wherein the metallized structure includes aluminum.
A method of forming an integrated circuit chip, the method comprising :
Comprising: providing a wafer, the wafer includes a semiconductor substrate, includes a number of semiconductor devices in or on the semiconductor substrate, wherein one of the plurality of semiconductor device transistor, on said semiconductor substrate It includes a metallization structure, the metallization structure is connected to said plurality of semiconductor devices, the metallization structure, the first metal layer and second metal layer on said first metal layer, wherein A dielectric layer between first and second metal layers, on the metallized structure and on the dielectric layer
In the passivation layer above the passivation layer comprises a nitride layer, a passivation layer, and comprises a polymer layer of the passivation layer surface, through the polymer layer, a first opening through the passivation layer, the metallized Of the first pad of the structure
A second opening overlying, exposing the first pad , through the polymer layer, and through the passivation layer is over the second pad of the metallized structure; And the first and second pads are separated from each other by an insulating material, and the polymer layer has a thickness of 2 to 150 micrometers;
And forming a first first conductive structure on the pad and the second conductive structure on the second pad, the first conductive structure, the first of connected to the through openings first pad, the second conductive structure is connected to the second pad through said second opening, and a step;
Forming a solder layer on the first and second conductive structures;
A step of placing a passive element on and on the solder layer and the polymer layer, the passive element
The first contact of the child is on the solder layer on the first conductive structure, a second contact of said passive elements, on said solder layer on the second conductive structure There is a step;
Flowing the solder layer, between the first solder interconnect between the first contact and the first conductive structure and between the second contact and the second conductive structure. Generating a second solder interconnect, wherein the first contact is directly connected to the first solder interconnect via the first conductive structure. connected to the pad, the second contact is connected to the second pad via the second conductive structure by connecting directly to the second solder interconnection thereof, the steps;
Including a method.
21. The method of claim 20 , wherein the metallized structure comprises aluminum.
21. The method of claim 20 , wherein placing the passive element comprises placing a capacitor on the polymer layer and on the solder layer.
21. The method of claim 20 , wherein placing the passive element comprises placing an inductor on the polymer layer and on the solder layer.
21. The method of claim 20 , wherein placing the passive element comprises placing a resistor on the polymer layer and on the solder layer.
21. The method of claim 20 , wherein the polymer layer comprises benzocyclobutene (BCB).
21. The method of claim 20 , wherein the polymer layer is formed by a process that includes a coating process and a curing process.
21. The method of claim 20 , wherein the polymer layer comprises polyimide.

Images