CN104952789A - Manufacturing method of adapter plate comprising high-aspect-ratio TSV (through silicon vias) - Google Patents
Manufacturing method of adapter plate comprising high-aspect-ratio TSV (through silicon vias) Download PDFInfo
- Publication number
- CN104952789A CN104952789A CN201510214323.5A CN201510214323A CN104952789A CN 104952789 A CN104952789 A CN 104952789A CN 201510214323 A CN201510214323 A CN 201510214323A CN 104952789 A CN104952789 A CN 104952789A
- Authority
- CN
- China
- Prior art keywords
- tsv
- keyset
- insulating barrier
- ratio
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
Abstract
The invention provides a manufacturing method of an adapter plate comprising high-aspect-ratio TSV (through silicon vias). The adapter plate comprises a plurality of high-aspect-ratio perpendicular TSV holes, an insulating layer and re-wiring layers and is provided with a first surface and a second surface which are opposite to each other; the diameter of the TSV is 5-150 micrometers; the aspect ratio of the TSV is 10:1; the TSV are perpendicular through holes which penetrate in the first surface and the second surface of the adapter plate perpendicularly; the insulating layer covers the surface of a whole substrate and side walls of the TSV in a shape maintenance manner; and the re-wiring layers are arranged on the first surface and the second surface of the adapter plate. Correspondingly, manufacturing steps of the adapter plate are described in detail. The problems that the insulating layer on the back surface is discontinuous and cracks due to too small TSV and the TSV have holes due to quick sealing caused by over fast growth of metal of seed layers of side walls of the small-sized TSV can be solved effectively, and the yield and the electrical reliability of the adapter plate comprising the high-aspect-ratio TSV can be improved.
Description
Technical field
The invention belongs to microelectronic packaging technology field, relate to the three-dimensional integration technology of silicon through hole (Through Silicon Via, TSV), be specifically related to a kind of manufacture method of the keyset containing high-aspect-ratio TSV.
Background technology
Along with constantly reducing of transistor feature size, Moore's Law is more and more hard to carry on.Particularly in recent years, along with the proposition surmounting Moore's Law, system in package becomes one of main flow direction of semiconductor industry future development.Based on the system in package of TSV technology because having the advantages such as high density of integration, low signal delay, low-power consumption, become the focus of academia and industrial quarters research.On electronic components in 2014 and technical conference (ECTC), in the industry generally acknowledge to semiconductor element carry out three-dimensional stacked and wiring 3D technological difficulties heavy, the 2.5D encapsulation technology introducing keyset between semiconductor element and base plate for packaging is current main flow.
Keyset thickness comparatively ripe is at present at 200 ~ 300 μm, and the TSV diameter that keyset etches is at 50 ~ 100 μm, and the making of TSV and connect up again (Redistribution Layer, RDL) is all comparatively ripe; Along with TSV size narrows down to 20 μm and following gradually, the TSV depth-to-width ratio that need etch reach 10:1 and more than, the preparation of follow-up TSV inner insulating layer/Seed Layer, Cu plating in TSV, and back side TSV insulating barrier makes and all challenged.
Specifically: along with TSV size on keyset narrows down to 20 μm and following gradually, TSV depth-to-width ratio reach 10:1 and more than, TSV inner insulating layer can not, again by the method for conventional P ECVD or ICPCVD, need adopt oxidation furnace to prepare hot oxygen SiO
2insulating barrier.Traditional Slag coating Cu Seed Layer method, also can sputter last layer Cu Seed Layer at TSV sidewall, carry out in TSV electroplating process follow-up, the Seed Layer of TSV sidewall is easy to cause TSV Quick seal, cause TSV lower middle portion to occur large-scale cavity, affect electric property and the reliability of keyset.After chip back attenuated polishing exposes TSV, need to prepare insulating barrier, routine has CVD to prepare SiO
2the method of insulating barrier prepared by insulating barrier and BCB glue.SiO
2insulating barrier needs photoetching to etch SiO at TSV upper shed RIE after having prepared
2insulating barrier, exposes TSV, and TSV size is little, and opening needs less, if etch away the part SiO of TSV periphery due to alignment error or exposure transition
2, will directly cause keyset electricity to lose efficacy, and RIE etches SiO
2keyset is easily caused to meet with stresses excessive and ftracture.BCB glue does insulating barrier, and thickness is too large, should not use when TSV size is too little.
Summary of the invention
For above-mentioned existing various problems, the object of the present invention is to provide a kind of manufacture method of the keyset containing high-aspect-ratio TSV.
Keyset containing high-aspect-ratio TSV of the present invention, comprises the vertical TSV through hole of multiple high-aspect-ratio, insulating barrier, again wiring layer; Form insulating barrier at keyset first surface and second surface and TSV through hole sidewall and only bottom TSV, make Seed Layer; Redistribution lines layer, at described keyset first surface and/or second surface, is made up of conductive metal layer and interlayer dielectric layer.Wherein:
Described keyset is high resistant silicon chip, low resistance silicon chip or the insulating material such as glass, quartz, has relative first surface and second surface;
Described TSV is diameter 5 ~ 150 μm, and depth-to-width ratio is about 10:1, vertically runs through the first surface of described keyset and the vertical through hole of second surface;
Described insulating barrier guarantor type covers whole substrate surface and TSV sidewall, one or more layers structure can be had, its material is silica, silicon nitride, or polyimides, Parylene, polyphenyl butylene and combination thereof, the method forming described insulating barrier comprises thermal oxidation, ald, chemical vapour deposition (CVD), sputtering, spin coating and combination thereof;
Described Seed Layer is relevant with the metal that TSV need electroplate, and can be Cu, W etc.
Accordingly, the invention discloses the manufacture method that this contains the keyset of high-aspect-ratio TSV, this manufacture method comprises following key step:
A) provide keyset, described keyset has relative first surface and second surface, at the photoetching of described keyset first surface, the TSV making high-aspect-ratio;
B) by thinning for described keyset second surface, polishing, expose TSV hole, make TSV hole run through first surface and the second surface of described keyset;
C) homogeneous insulation layers is made at described keyset first surface, second surface and TSV sidewall;
D) RDL (again wiring layer) is prepared at the described keyset first surface preparing insulating barrier;
E) provide liner, described liner has relative first surface and second surface, deposit releasing layer and Seed Layer on the first surface of described liner;
F) adopt the graphical bonding of BCB (photosensitive benzocyclobutene), the keyset first surface with graphical BCB opening is carried out face-to-face wafer bonding with the liner first surface that deposited releasing layer and Seed Layer successively;
G) adopt the mode of bottom-up plating to carry out plating to TSV to fill;
H) RDL and micro convex point is prepared at the described keyset second surface preparing insulating barrier;
I) scribing, separates bonding, is separated by described keyset with described liner.
Preferably, step a) in depth-to-width ratio TSV manufacture method be that deep reaction ion etching (DRIE), laser ablation, sandblasting are with methods such as, Ultrasonic machining;
Preferably, in steps d), g) in prepare RDL and micro convex point method comprise evaporation, sputtering, plating, chemical vapour deposition (CVD) and combination thereof, the metal layer material of described RDL is copper, gold, silver, platinum, aluminium or its alloy etc.;
Preferably, in step e) in the releasing layer of deposit, material can be photoresist, ephemeral key rubber alloy etc.
The present invention can simultaneously form insulating barrier at keyset first surface and second surface and TSV through hole sidewall and only bottom TSV, make Seed Layer, its the insulating backside layer too little insulating backside layer brought of TSV size effectively can avoided to make difficulty and cause is discontinuous, insulating backside layer cracking, and small size TSV sidewall Seed Layer metallic growth is too fast causes Quick seal and bring the problem of TSV empty memory, the rate of finished products containing the keyset of high-aspect-ratio TSV and electrical reliability can be improved.
Accompanying drawing explanation
Fig. 1 is embodiment makes the vertical TSV deep hole of high-aspect-ratio schematic diagram at keyset first surface;
Fig. 2 is that embodiment is thinning at keyset second surface, polishing, exposes TSV vertical long hole from second surface, makes TSV hole run through the first surface of described keyset and the schematic diagram of second surface;
Fig. 3 is that embodiment makes the schematic diagram of homogeneous insulation layers at keyset first surface, second surface and TSV sidewall;
Fig. 4 is the schematic diagram of embodiment at keyset first surface pre-deposited RDL;
Fig. 5-1 is the schematic diagram of embodiment deposit releasing layer and Seed Layer on described liner, and Fig. 5-2 illustrates that embodiment carries out BCB photoetching at keyset first surface, makes the schematic diagram with patterned BCB opening;
Fig. 6 is the schematic diagram that embodiment carries out wafer bonding between described liner first surface and the patterned keyset first surface of BCB;
Fig. 7 is that the mode of embodiment in the bottom-up plating of employing carries out TSV electroplating the schematic diagram of filling;
Fig. 8 is that embodiment prepares the schematic diagram of RDL and micro convex point at keyset second surface;
Fig. 9 is embodiment at solution bonding, by the schematic diagram that described keyset is separated with described liner.
Wherein:
1 keyset substrate 2 insulating barrier
3 wiring layer (RDL) 4 liners again
5 releasing layer 6 Seed Layer
7 interlayer dielectric layers (BCB glue) 8 fill metal
9 micro convex point
Embodiment
In order to make object of the present invention, advantage, manufacture method clearly, below in conjunction with accompanying drawing, exemplifying embodiment of the present invention is described in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.It should be noted that, the embodiment be described with reference to the drawings is exemplary, only for explaining the present invention, and can not be interpreted as limitation of the present invention.
Hereafter the adapter plate structure containing high-aspect-ratio TSV provided by the invention is set forth.Illustrate with reference to accompanying drawing, it should be noted that, the accompanying drawing of each embodiment of the present invention is only the object in order to illustrate, so there is no necessity and draws in proportion.The making step of this adapter plate structure specifically comprises:
Step S101, provides keyset substrate 1, and described keyset substrate 1 has relative first surface and second surface, the first surface of described keyset etches multiple vertical TSV deep hole, as shown in Figure 1;
Described keyset can be high resistant silicon chip or low resistance silicon chip, can also be the insulating material such as glass or quartz.The thickness of described keyset is within the scope of 150 μm ~ 500 μm.
In the present embodiment, the method concrete steps forming vertical TSV deep hole are as follows: make mask layer first over the substrate, and form multiple TSV figure opening.The material of described mask layer is silica, silicon nitride or polyimides, Parylene or thick photoresist, and combination.RIE dry etching, wet etching are comprised to the patterned method of described mask layer, and combination.Subsequently, as shown in the figure, etch described substrate, etch multiple vertical TSV deep hole.The aperture of described deep hole is within the scope of 5 μm ~ 150 μm, the depth-to-width ratio scope of described deep hole is 1:1 ~ 50:1, its cross section is generally circular or square, also can be other shapes such as hexagon or octagon, the method forming described vertical TSV deep hole comprises deep reaction ion etching (DRIE), laser ablation, sandblasting, wet etching and combination thereof.
Step S102, polishing thinning at described keyset second surface, exposes vertical TSV deep hole from second surface, makes TSV hole run through first surface and the second surface of described keyset, as shown in Figure 2;
The method that described method that is thinning, polishing can select chemico-mechanical polishing (CMP), reactive ion etching (RIE), TMAH and KOH wet etching and combination thereof etc. suitable.
Step S103, prepares uniform insulating barrier 2, as shown in Figure 3 in described keyset first surface, second surface and TSV deep hole;
Described insulating barrier can have one or more layers structure, its material is silica, silicon nitride, or polyimides, Parylene, polyphenyl butylene and combination thereof, its thickness range is 100nm ~ 10 μm, in order to realize the electric isolation between deep hole and keyset substrate.The method forming described insulating barrier comprises thermal oxidation, ald, chemical vapour deposition (CVD), sputtering, spin coating, glue spraying and combination thereof.In some other embodiment of the present invention, when described backing material is the insulating material such as glass, quartz, insulating barrier can be formed.
Step S104, at described keyset first surface pre-deposited RDL, as shown in Fig. 43;
On the described keyset with insulating barrier, optical graving is for RDL figure, then prepares RDL.Described RDL can pass through evaporation, sputtering, plating, chemical plating, chemical vapour deposition (CVD) and combination thereof.RDL comprises metal level, interlayer dielectric layer, repeatedly can carry out the processing step of metal deposition, interlayer dielectric layer deposition, thus form the RDL of sandwich construction.
Step S105, provides liner 4, deposit releasing layer 5 and Seed Layer 6 on described liner, as shown in fig. 5-1;
The material of described liner can be semi-conducting material, metal material, insulating material and combination thereof.Releasing layer can be ephemeral key rubber alloy, photoresist or other there is viscosity and can rapidly-soluble glue in coordinative solvent; Seed Layer is then relevant with the metal that TSV need electroplate, and can be Cu, W etc.;
Step S106, carries out BCB photoetching at described keyset first surface, and make BCB figure opening, as shown in Fig. 5-2, wherein 7 is BCB glue;
Described BCB figure opening can be suitably larger than TSV opening, and the follow-up keyset first surface micro convex point of can working as of outstanding part uses;
Step S107, carries out wafer bonding, as shown in Figure 6 between described liner first surface and the patterned keyset first surface of BCB;
Step S108, adopts the mode of bottom-up plating to fill the TSV on described keyset, and as shown in Figure 8, wherein 8 for filling metal;
The metal of plating can be metal conventional in the current TSV such as Cu, W, if fill the materials such as polysilicon, then considers other ways except plating.
Step S109, described prepare insulating barrier and complete TSV plating keyset second surface prepare RDL and micro convex point 9, as shown in Figure 9;
On the described keyset with insulating barrier, optical graving is for RDL figure, then prepares RDL.Described RDL can pass through evaporation, sputtering, plating, chemical plating, chemical vapour deposition (CVD) and combination thereof.Repeatedly can carry out the processing step of metal deposition, interlayer dielectric layer deposition, thus form the RDL of sandwich construction.Finally, make metal micro convex point, for follow-up wafer or chip bonding stacking.The material of described metal micro convex point is copper, gold, tin, lead, silver, nickel and alloy thereof, and the method that evaporation, sputtering, plating, chemical plating and combination thereof etc. can be adopted suitable is formed.
Step S110, separates bonding, is separated by described keyset, as shown in Figure 9 with described liner.
The equipment described keyset wafer being placed in special solution bonding heats also applied thrust and realizes the solution bonding of wafer, also after can carrying out scribing according to scribe line, be placed in the interim bonding liquid that removes photoresist and add heat soaking, after a period of time, keyset chip is separated with liner, realizes the solution bonding of chip.
Subsequently, other the follow-up processing steps based on the three-dimensional integration technology of interconnecting silicon through holes can be carried out, comprise that bonding is stacking, underfill filling etc., do not repeat them here.
Although describe in detail about example embodiment and advantage thereof, being to be understood that when not departing from the protection range of spirit of the present invention and claims restriction, various change, substitutions and modifications can being carried out to these embodiments.For other examples, those of ordinary skill in the art should easy understand maintenance scope in while, the order of processing step can change.
In addition, range of application of the present invention is not limited to the technique of the specific embodiment described in specification, mechanism, manufacture, material composition, means, method and step.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technique existed at present or be about to develop, mechanism, manufacture, material composition, means, method or step later, wherein their perform the identical function of the corresponding embodiment cardinal principle that describes with the present invention or obtain the identical result of cardinal principle, can apply according to the present invention to them.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.
Claims (10)
1., containing a manufacture method for the keyset of high-aspect-ratio TSV, it is characterized in that, comprise the following steps:
A) provide keyset, described keyset has relative first surface and second surface, makes the TSV of high-aspect-ratio in described first surface photoetching;
B) by thinning for the second surface of described keyset, TSV hole is made to run through first surface and the second surface of described keyset;
C) uniform insulating barrier is made at the first surface of described keyset, second surface and TSV sidewall;
D) RDL is prepared at the keyset first surface preparing insulating barrier;
E) provide liner, described liner has relative first surface and second surface, deposit releasing layer and Seed Layer on the first surface of described liner;
F) adopt the graphical bonding of BCB, the liner first surface after keyset first surface and deposit releasing layer and Seed Layer is carried out face-to-face wafer bonding;
G) adopt the mode of bottom-up electro-coppering to carry out plating to TSV to fill;
H) RDL is prepared at the keyset second surface preparing insulating barrier;
I) by separating bonding, described keyset being separated with described liner, obtaining the keyset containing high-aspect-ratio TSV.
2. method according to claim 1, is characterized in that, step a) described keyset is high resistant silicon chip, low resistance silicon chip or insulating material, and described insulating material is the insulating material such as glass or quartz; When described keyset is insulating material, make described insulating barrier, or do not make described insulating barrier.
3. method according to claim 1, is characterized in that, step a) described TSV is diameter 5 ~ 150 μm, and depth-to-width ratio is 1:1 ~ 50:1, vertically runs through the first surface of described keyset and the vertical through hole of second surface; The manufacture method in TSV hole be following in one: deep reaction ion etching, laser ablation, sandblasting, Ultrasonic machining.
4. method according to claim 1, is characterized in that, step b) in the thining method of keyset be chemico-mechanical polishing, reactive ion etching, TMAH and KOH wet etching and combination thereof.
5. method according to claim 1, it is characterized in that, step c) described insulating barrier is one or more layers structure, its material is silica or silicon nitride, or polyimides, Parylene, polyphenyl butylene and combination thereof, the method forming described insulating barrier comprises thermal oxidation, ald, chemical vapour deposition (CVD), sputtering, spin coating and combination thereof.
6. method according to claim 1, it is characterized in that, in steps d), h) in form the method for RDL and comprise evaporation, sputtering, plating, chemical plating, chemical vapour deposition (CVD) and combination thereof, the metal layer material of described RDL is copper, gold, silver, platinum, nickel, tungsten, aluminium or its alloy, and the interlayer dielectric layer of described RDL is silicon dioxide, silicon nitride, polyimides or BCB.
7. method according to claim 1, is characterized in that, in step e) material of described liner is semi-conducting material, metal material, insulating material and combination thereof; Described releasing layer is ephemeral key rubber alloy, photoresist or other there is viscosity and can rapidly-soluble glue in coordinative solvent; The material of described Seed Layer is identical with the metal material that TSV need electroplate.
8. method according to claim 1, it is characterized in that, step I) use and separate the equipment of bonding and carry out heating and applied thrust realizes the solution bonding of wafer, or after carrying out scribing according to scribe line, be placed in the interim bonding liquid that removes photoresist and add heat soaking, after a period of time, keyset chip is separated with liner, realizes the solution bonding of chip.
9. method according to claim 1, is characterized in that, step h) also comprise the step making metal micro convex point, for follow-up wafer or chip bonding stacking.
10. the keyset containing high-aspect-ratio TSV that according to any one of claim 1 ~ 9 prepared by method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510214323.5A CN104952789A (en) | 2015-04-29 | 2015-04-29 | Manufacturing method of adapter plate comprising high-aspect-ratio TSV (through silicon vias) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510214323.5A CN104952789A (en) | 2015-04-29 | 2015-04-29 | Manufacturing method of adapter plate comprising high-aspect-ratio TSV (through silicon vias) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104952789A true CN104952789A (en) | 2015-09-30 |
Family
ID=54167353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510214323.5A Pending CN104952789A (en) | 2015-04-29 | 2015-04-29 | Manufacturing method of adapter plate comprising high-aspect-ratio TSV (through silicon vias) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104952789A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106117472A (en) * | 2016-06-30 | 2016-11-16 | 上海交通大学 | The method of one-step method chemical graft organic insulating film in silicon through hole |
| CN106252276A (en) * | 2016-08-08 | 2016-12-21 | 中国电子科技集团公司第五十四研究所 | Manufacture method based on TSV technology switch matrix radio frequency unit |
| CN106608615A (en) * | 2015-10-22 | 2017-05-03 | 上海先进半导体制造股份有限公司 | Method for manufacturing MEMS device |
| CN107293484A (en) * | 2017-07-11 | 2017-10-24 | 华进半导体封装先导技术研发中心有限公司 | One kind switching board fabrication method |
| CN107359137A (en) * | 2017-07-11 | 2017-11-17 | 华进半导体封装先导技术研发中心有限公司 | A kind of method for manufacturing pinboard |
| CN109019504A (en) * | 2018-06-22 | 2018-12-18 | 北京时代民芯科技有限公司 | A kind of new producing method of the adjustable interconnection through silicon via of resistance |
| CN110010476A (en) * | 2018-10-10 | 2019-07-12 | 浙江集迈科微电子有限公司 | A kind of novel electroplating process for filling hole in system-in-package structure |
| CN110010548A (en) * | 2018-12-26 | 2019-07-12 | 杭州臻镭微波技术有限公司 | A kind of cavity structure production method of bottom belt pad |
| CN110430086A (en) * | 2019-08-27 | 2019-11-08 | 安徽工程大学 | TSV honeycomb single ring architecture, TSV honeycomb multiring structure and fault-tolerance approach based on time-sharing multiplex |
| CN111799169A (en) * | 2020-07-17 | 2020-10-20 | 绍兴同芯成集成电路有限公司 | Process for processing TGV by combining femtosecond laser with HF wet etching |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101834159A (en) * | 2010-04-23 | 2010-09-15 | 中国科学院上海微系统与信息技术研究所 | Manufacturing process for realizing through silicon via packaging by adopting BCB (Benzocyclobutene) supplementary bonding |
| CN102376689A (en) * | 2011-09-09 | 2012-03-14 | 华中科技大学 | Through silicon hole structure with step and manufacture process of through silicon hole |
| JP2013021253A (en) * | 2011-07-14 | 2013-01-31 | Seiko Epson Corp | Semiconductor device manufacturing method |
| CN103258789A (en) * | 2013-04-17 | 2013-08-21 | 华中科技大学 | Manufacturing method of through hole interconnection structure and product of through hole interconnection structure |
-
2015
- 2015-04-29 CN CN201510214323.5A patent/CN104952789A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101834159A (en) * | 2010-04-23 | 2010-09-15 | 中国科学院上海微系统与信息技术研究所 | Manufacturing process for realizing through silicon via packaging by adopting BCB (Benzocyclobutene) supplementary bonding |
| JP2013021253A (en) * | 2011-07-14 | 2013-01-31 | Seiko Epson Corp | Semiconductor device manufacturing method |
| CN102376689A (en) * | 2011-09-09 | 2012-03-14 | 华中科技大学 | Through silicon hole structure with step and manufacture process of through silicon hole |
| CN103258789A (en) * | 2013-04-17 | 2013-08-21 | 华中科技大学 | Manufacturing method of through hole interconnection structure and product of through hole interconnection structure |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106608615B (en) * | 2015-10-22 | 2019-03-08 | 上海先进半导体制造股份有限公司 | The manufacturing method of MEMS device |
| CN106608615A (en) * | 2015-10-22 | 2017-05-03 | 上海先进半导体制造股份有限公司 | Method for manufacturing MEMS device |
| CN106117472B (en) * | 2016-06-30 | 2018-11-16 | 上海交通大学 | The method of one-step method chemical graft organic insulating film in through silicon via |
| CN106117472A (en) * | 2016-06-30 | 2016-11-16 | 上海交通大学 | The method of one-step method chemical graft organic insulating film in silicon through hole |
| CN106252276A (en) * | 2016-08-08 | 2016-12-21 | 中国电子科技集团公司第五十四研究所 | Manufacture method based on TSV technology switch matrix radio frequency unit |
| CN106252276B (en) * | 2016-08-08 | 2019-01-15 | 中国电子科技集团公司第五十四研究所 | Manufacturing method based on TSV technology switch matrix radio frequency unit |
| CN107293484A (en) * | 2017-07-11 | 2017-10-24 | 华进半导体封装先导技术研发中心有限公司 | One kind switching board fabrication method |
| CN107359137A (en) * | 2017-07-11 | 2017-11-17 | 华进半导体封装先导技术研发中心有限公司 | A kind of method for manufacturing pinboard |
| CN109019504A (en) * | 2018-06-22 | 2018-12-18 | 北京时代民芯科技有限公司 | A kind of new producing method of the adjustable interconnection through silicon via of resistance |
| CN109019504B (en) * | 2018-06-22 | 2020-02-21 | 北京时代民芯科技有限公司 | Manufacturing method of interconnected silicon through hole with adjustable resistance |
| CN110010476A (en) * | 2018-10-10 | 2019-07-12 | 浙江集迈科微电子有限公司 | A kind of novel electroplating process for filling hole in system-in-package structure |
| CN110010548A (en) * | 2018-12-26 | 2019-07-12 | 杭州臻镭微波技术有限公司 | A kind of cavity structure production method of bottom belt pad |
| CN110010548B (en) * | 2018-12-26 | 2021-08-24 | 浙江集迈科微电子有限公司 | Manufacturing method of cavity structure with bonding pad at bottom |
| CN110430086A (en) * | 2019-08-27 | 2019-11-08 | 安徽工程大学 | TSV honeycomb single ring architecture, TSV honeycomb multiring structure and fault-tolerance approach based on time-sharing multiplex |
| CN111799169A (en) * | 2020-07-17 | 2020-10-20 | 绍兴同芯成集成电路有限公司 | Process for processing TGV by combining femtosecond laser with HF wet etching |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104952789A (en) | Manufacturing method of adapter plate comprising high-aspect-ratio TSV (through silicon vias) | |
| CN102270603B (en) | Manufacturing method of silicon through hole interconnect structure | |
| CN102214624B (en) | Semiconductor structure with through holes and manufacturing method thereof | |
| JP5274004B2 (en) | Method for manufacturing a conductive via structure in a semiconductor substrate | |
| CN103193193B (en) | MEMS and forming method thereof | |
| US8525343B2 (en) | Device with through-silicon via (TSV) and method of forming the same | |
| US8390125B2 (en) | Through-silicon via formed with a post passivation interconnect structure | |
| US9484293B2 (en) | Semiconductor devices with close-packed via structures having in-plane routing and method of making same | |
| CN103681390B (en) | A kind of wafer scale silicon substrate preparation method based on TSV technique | |
| CN103367285B (en) | A kind of through-hole structure and preparation method thereof | |
| CN103700595B (en) | A kind of wafer scale high-aspect-ratio TSV base plate for packaging preparation method | |
| CN101179037A (en) | High, depth and width three-dimensional uprightness interconnect and realization method of three-dimensional integrate circuit | |
| CN102376689A (en) | Through silicon hole structure with step and manufacture process of through silicon hole | |
| CN115799194B (en) | Wafer heat dissipation micro-channel, preparation method and three-dimensional integration method | |
| CN107316840A (en) | The 3DIC structures and method of mixing engagement semiconductor wafer | |
| US8080876B2 (en) | Structure and method for creating reliable deep via connections in a silicon carrier | |
| CN106449573A (en) | Metal adapter plate with vertical via interconnect and manufacturing method thereof | |
| CN103346120A (en) | Method for exposing TSV heads in chemical etching mode and corresponding device | |
| CN104882432B (en) | A kind of semiconductor structure and its manufacture method with vertical through hole interconnection | |
| CN207134348U (en) | The embedded fan-out-type silicon pinboard of three-dimensional systematic package application | |
| CN103258788A (en) | Through hole interconnection structure manufacturing method based on bidirectional filling and through hole interconnection structure product | |
| CN111968953A (en) | Through silicon via structure and preparation method thereof | |
| CN101645401A (en) | Circuit device three-dimensional integrative method | |
| CN113410175B (en) | TSV conductive through hole structure preparation method | |
| CN102683309B (en) | Wafer scale plants adapter plate structure of ball indentation brush filling through hole and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150930 |
|
| WD01 | Invention patent application deemed withdrawn after publication |