CN101645401A - Circuit device three-dimensional integrative method - Google Patents
Circuit device three-dimensional integrative method Download PDFInfo
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- CN101645401A CN101645401A CN200910092403A CN200910092403A CN101645401A CN 101645401 A CN101645401 A CN 101645401A CN 200910092403 A CN200910092403 A CN 200910092403A CN 200910092403 A CN200910092403 A CN 200910092403A CN 101645401 A CN101645401 A CN 101645401A
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Abstract
The invention discloses a circuit device three-dimensional integrative method, which comprises the following steps of: manufacturing a blind hole on the front side of a first substrate disc with the circuit device; bonding the front side of a first substrate disc and an auxiliary disc, carrying out back reduction processing on the first substrate disc, and causing an open mouth of the blind hole to form a through hole; using a metal seed layer on the auxiliary disc as a starting point and filling an electric conduction metal in the through hole in an electro-plating mode from bottom to top; and bonding the back side of the first substrate disc and the front side of a second substrate disc with the circuit device. In the embodiment of the invention, when the circuit device is integrated ina three-dimensional way, the blind hole is manufactured in the substrate disc with the circuit device and opened to form the through hole, and the metal is filled in the through hole by using the auxiliary disc in the electro-plating mode from bottom to top, thus avoiding a hole and a gap appearing on the electro-plated bind hole, realizing the three-dimensional interconnection of high density andhigh aspect ratio, and simultaneously reducing the technology difficulty of the three-dimensional integration and interconnection.
Description
Technical field
The present invention relates to integrated circuit and make field, the integrated method of particularly a kind of circuit device three-dimensional.
Background technology
Circuit devcie, as integrated circuit, transducer and MEMS (microelectromechanical systems, Micro-Electro-Mechanical System) etc., developed into system level chip (SOC at present, Systemon a Chip) this stage, the manufacturing technology of employing system level chip can realize the repertoire of system on single-chip, the developing compatibling problem that a difficult problem is different manufacture crafts of SOC, the manufacture craft that may need to adopt multiple standards in the process of making SOC, but the manufacture method of these manufacturing process is all different with the backing material of employing, be difficult to be implemented on the same chip, even backing material is identical, also to consider the manufacturing feasibility of each circuit module in the mill.This makes on the one hand and can not optimize fully each circuit module of SOC, on a substrate, realize a plurality of circuit modules on the other hand, not only need to increase mask quantity, and arrange the production order of each circuit module that very big restriction is also arranged, increased the circuit manufacturing cost, limited the raising of chip performance.
In order to address the above problem, can use the mode of circuit device three-dimensional interconnection to realize three-dimensional integrated, the three-dimensional interconnection of circuit devcie is on the planar circuit basis, utilize the third dimension of vertical plane to realize the interconnection of multilayer circuit device in the single chip, promptly a big planar circuit being divided into some functional modules that are associated in logic is distributed on a plurality of chip layer, by penetrating the three-dimensional perpendicular interconnect metallization lines of substrate, multilayer chiop is carried out three-dimensional interconnection and integrated then.Three-dimensional interconnection can be realized a plurality of circuit devcies vertically integrated of difference in functionality, different process, has reduced the integrated difficulty of circuit devcie significantly, and can improve integrated circuit speed, reduced the power consumption of chip.Three-dimensional interconnection can the integrated multi-layer different process or the circuit devcie of different backing materials, provides good solution for promoting the SOC performance.
Realize that at present the circuit device three-dimensional Interworking Technology mainly comprises based on the implementation of blind hole with based on the implementation of through hole.Based on the implementation of blind hole, on the substrate disk of circuit devcie, utilize the single face etching to make the blind hole of single face opening, the mode that adopts Damascus to electroplate is then filled metal to realize three-dimensional interconnection in the blind hole of single face opening.The substrate disk keeps original thickness in this method, by being manufactured with the substrate disk of vertical interconnects with auxiliary wafer bonding and attenuate, forms three-dimensional interconnection thereby the metal wire that makes the substrate disk fill can penetrate substrate after metal filled getting well.
Implementation based on through hole, at first on the substrate disk of circuit devcie, make through hole, in through hole, fill metal with plating mode then, can carry out double-side operation when filling metal, promptly after the opening of through hole is sealed in the single face plating, utilize the mode of bottom-up plating to fill metal material.
After prior art was studied, the inventor found, based on the implementation of blind hole, owing to can only adopt Damascus to electroplate, is easy to make blind hole at first to be sealed at opening part, forms and fills the metal wire inside holes.In order to guarantee the reliability of three-dimensional interconnection, the blind hole of making on substrate can not be dark excessively, therefore realizes that the depth-to-width ratio of substrate disk three-dimensional interconnection has considerable restraint.Easy during based on the implementation filling vias of through hole, in order to guarantee the operability on the substrate disk, the thickness of single-layer substrate disk often surpasses 200 microns, though have higher depth-to-width ratio, but limited the raising of interconnection line density simultaneously.
Summary of the invention
The embodiment of the invention provides a kind of circuit device three-dimensional integrated method, and described technical scheme is as follows:
The method that a kind of circuit device three-dimensional is integrated, described method comprises:
Blind hole is made in front at the first substrate disk that has circuit devcie;
The front and the auxiliary disk of the described first substrate disk are carried out bonding, and wherein, the one side with the first substrate wafer bonding on the described auxiliary disk has the metal seed layer of electroplating usefulness;
The described first substrate disk is carried out thinning back side handle, make described blind hole opening form through hole;
With the described metal seed layer on the described auxiliary disk is starting point, adopts bottom-up plating mode filled conductive metal in described through hole;
Bonding is carried out with the front that has the second substrate disk of circuit devcie in the back side of the first substrate disk.
The embodiment of the invention circuit devcie is carried out three-dimensional when integrated, by on the substrate disk of circuit devcie, making blind hole, and to blind hole opening formation through hole, utilize auxiliary disk to adopt bottom-up plating mode in through hole, to fill metal, avoided electroplating hole and the slit that blind hole may occur, realize the three-dimensional integrated of circuit devcie high density, high-aspect-ratio, also reduced the technology difficulty of the integrated and interconnection of circuit device three-dimensional simultaneously.
Description of drawings
Fig. 1 is the schematic diagram of the substrate disk that provides of the embodiment of the invention;
Fig. 2 is the integrated method flow diagram of circuit device three-dimensional that the embodiment of the invention 1 provides;
Fig. 3 is the integrated method flow diagram of circuit device three-dimensional that the embodiment of the invention 2 provides;
The schematic diagram of the substrate disk of blind hole that Fig. 4 is the making that provides of the embodiment of the invention 2;
The schematic diagram of the substrate disk of Fig. 5 insulating barrier that has been the deposit in blind hole that provides of the embodiment of the invention 2 and diffusion impervious layer;
Fig. 6 is the substrate disk that provides of the embodiment of the invention 2 and the schematic diagram behind the auxiliary wafer bonding;
Fig. 7 schematic diagram of the substrate disk after the reduction processing that has been the carrying out that provide of the embodiment of the invention 2;
The schematic diagram of the substrate disk of Fig. 8 is the removal that provides of the embodiment of the invention 2 via bottoms high molecular polymer;
Fig. 9 is the schematic diagram of the substrate disk of having filled metal in through hole that provides of the embodiment of the invention 2;
Figure 10 is the schematic diagram of the substrate disk of having made metal salient point on through hole that provides of the embodiment of the invention 2;
Figure 11 is the schematic diagram of the two-layer substrate wafer bonding that provides of the embodiment of the invention 2;
The schematic diagram of the two-layer substrate wafer bonding of Figure 12 is the removal that provides of the embodiment of the invention 2 auxiliary disk;
Figure 13 is the schematic diagram of three layers of substrate wafer bonding providing of the embodiment of the invention 2.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.
Embodiment 1
The embodiment of the invention provides a kind of method of circuit device three-dimensional interconnection, and this method can be carried out the substrate disk of circuit devcie the three-dimensional perpendicular interconnection of high density, high-aspect-ratio, has realized that effectively the three-dimensional interconnection of circuit devcie and three-dimensional are integrated.
In the present embodiment, at first the three-dimensional interconnection with the substrate disk of realizing the two-tier circuit device is that example describes, Figure 1 shows that the employed substrate disk of present embodiment W1, comprised the circuit devcie of making on this substrate disk, as devices such as integrated circuit, MEMS device or microsensors; Also comprise on this substrate disk W1: multiple layer metal interconnection line 12, and the interlayer dielectric layer of metal interconnecting wires 12 or surface passivation layer 11.Wherein, the material of substrate disk can be silicon, strained silicon, germanium silicon, GaAs (GaAs) or silicon-on-insulator (SOI).
In the present embodiment, with the substrate disk integrated the one side of circuit devcie be called the front, another side is called the back side.In the following description, the aspect relation according to bonding is divided into the first substrate disk and the second substrate disk with the substrate disk, and its aspect is closed and is: bonding is carried out in the front of the back side of the first substrate disk and the second substrate disk.In the process of three-dimensional perpendicular interconnection, need on the first substrate disk, carry out following operation, integrated with the three-dimensional perpendicular interconnection and the three-dimensional that realize the first substrate disk and the second substrate disk.Referring to Fig. 2, concrete operations are as follows:
201: blind hole is made in the front at the first substrate disk.
202: the front and the auxiliary disk of this first substrate disk are carried out bonding, and wherein, the one side with the first substrate wafer bonding on this auxiliary disk has the metal seed layer of electroplating usefulness.
Concrete, can utilize the bonding material of high molecular polymer as the intermediate layer, interim bonding is realized in the front of this ground floor substrate disk and the back side of auxiliary disk.
203: this first substrate disk is carried out thinning back side handle, make this blind hole opening form through hole;
204: with the metal seed layer on this auxiliary disk is starting point, adopts bottom-up plating mode filled conductive metal in the through hole of this first substrate disk.
Owing to adopted bottom-up plating mode that conducting metal is filled to through hole, conducting metal is to insert from the bottom of through hole, until the opening part that is filled to through hole.Therefore, in the process of filling, through hole can be filled up by conducting metal fully, is difficult for producing the space.
205: bonding is carried out in the back side and the front that has the second substrate disk of circuit devcie of the first substrate disk.
Owing to be filled with conducting metal in first through hole, by the metal wire of filling in the through hole, just can realize being electrically connected of the first substrate disk and the second substrate disk, utilize bonding material that two substrate disks are carried out bonding again, just realize the three-dimensional interconnection of two substrate disks.
From above-mentioned manufacturing process as can be seen, therefore the embodiment of the invention can allow to make darker blind hole on the substrate disk owing to adopted bottom-up filling mode, has improved three-dimensional integrated depth-to-width ratio; Owing to backing material has been carried out reduction processing, therefore can improve three-dimensional integrated density.
Need to prove that the method for the embodiment of the invention can also be used to make the MULTILAYER SUBSTRATE disk, when the new substrate disk of needs interconnection, then need to remove the auxiliary disk on the first substrate disk, and on this first substrate disk, make interconnect pad; Interconnect for new substrate disk.At this moment, it is the first substrate disk in 201 that new substrate disk is equal to, the first substrate disk of bonding and the second substrate disk are all the second substrate disk in 205 as an integral body etc., after according to the method among the 201-205 new substrate disk being handled, the back side of new substrate disk is bonded to the front of the first substrate disk, has promptly realized the three-dimensional interconnection of new substrate disk.In like manner, repeat bonding according to the method described above, just can realize the bonding of MULTILAYER SUBSTRATE disk, repeat no more herein.
The embodiment of the invention circuit devcie is carried out three-dimensional when integrated, by on the substrate disk of circuit devcie, making blind hole, and to blind hole opening formation through hole, utilize auxiliary disk to adopt bottom-up plating mode in through hole, to fill metal, avoided electroplating hole and the slit that blind hole may occur, realize the three-dimensional integrated of circuit devcie high density, high-aspect-ratio, also reduced the technology difficulty of the integrated and interconnection of circuit device three-dimensional simultaneously.
Embodiment 2
The embodiment of the invention provides a kind of circuit device three-dimensional integrated method, and this method can be carried out the substrate disk of circuit devcie the three-dimensional perpendicular interconnection of high density, high-aspect-ratio, has effectively realized the three-dimensional integrated and three-dimensional interconnection of circuit devcie.
In the present embodiment, at first the three-dimensional interconnection with the substrate disk of realizing the two-tier circuit device is that example describes, Figure 1 shows that the employed substrate disk of present embodiment W1, comprised the circuit devcie of making on this substrate disk, as devices such as integrated circuit, MEMS device or microsensors; Also comprise on this substrate disk W1: multiple layer metal interconnection line 12, and the interlayer dielectric layer of metal interconnecting wires 12 or surface passivation layer 11.Wherein, the material of substrate disk W1 can be silicon, strained silicon, germanium silicon, GaAs (GaAs) or silicon-on-insulator (SOI).
In the present embodiment, with the substrate disk integrated the one side of circuit devcie be called the front, another side is called the back side.In the following description, the aspect relation according to bonding is divided into the first substrate disk and the second substrate disk with the substrate disk, and its aspect is closed and is: bonding is carried out in the front of the back side of the first substrate disk and the second substrate disk.In the process of three-dimensional perpendicular interconnection, need on the first substrate disk, carry out following operation, integrated with the three-dimensional perpendicular interconnection and the three-dimensional that realize the first substrate disk and the second substrate disk.Referring to Fig. 3, concrete operations are as follows:
301: blind hole 14 is made in the front at the first substrate disk.
Concrete, make blind hole 14 and can adopt following method: methods such as reaction ion deep etching, laser ablation, machining.To adopt the reactive ion etching method is example; process in the positive manufacturing of first substrate disk blind hole is as follows: deposit etching protective layer film 13 on the surface passivation layer 11 of the first substrate disk W1; with protective layer film 13 as mask; utilize reactive ion etching technology that surface passivation layer 11 is carried out dry etching; utilize reaction ion deep etching that substrate disk W1 is lost deeply again and make blind hole 14, be illustrated in figure 4 as the substrate disk of having made blind hole 14.Wherein, the material of protective layer film 13 can be: materials such as silicon nitride (SixNy), silica, aluminium, photoresist.Can adopt during deposit etching protective layer film 13: methods such as low pressure chemical vapor deposition, plasma reinforced chemical vapor deposition, sputter or spin coating.
In addition; after having made blind hole 14; can also be at just the deposit side wall insulating layer and the diffusion impervious layer 15 in the blind hole 14 of this ground floor substrate disk, protecting, in blind hole 14 deposit side wall insulating layer and diffusion impervious layer 15 former of first substrate as shown in Figure 5.In the present embodiment, deposition process can be plasma-reinforced chemical vapour deposition, modes such as atomic layer deposition, sputter; The material of the side wall insulating layer of deposit can for but be not limited to silica, silicon nitride, macromolecular material etc.; The material of diffusion impervious layer can for but be not limited to materials such as silicon nitride, titanium nitride, tantalum nitride.
302: utilize the bonding material of high molecular polymer as intermediate layer B1, interim bonding is realized in the front of this first substrate disk and the back side of auxiliary disk F1, wherein, the one side of this auxiliary disk F1 and the first substrate wafer bonding has the metal seed layer F11 that electroplates usefulness.
Structure chart behind the first substrate disk and the auxiliary disk F1 bonding as shown in Figure 6, wherein, intermediate layer B1 is one deck bonding material of bonded substrate disk and auxiliary disk.The one side that has metal seed layer F11 on the auxiliary disk F1 is carried out bonding with the front of the first substrate disk, and the front of the metal seed layer F11 and the first substrate disk is bonded together by bonding material.Wherein, high molecular polymer as the bonding material in intermediate layer, for can chemistry removing or macromolecule polymer material that can photosensitive sex change, include but not limited to materials such as photoresist, WaferBondTM, benzocyclobutene (BCB), polyimides (PI), dimethyl silicone polymer (PDMS), poly-methacrylic methyl esters (PMMA), Merlon (PC), polystyrene (PS), poly-p-xylylene ethene (PET) and Teflon.The material of auxiliary other parts of disk F1 can be but be not limited to glass, stainless steel, titanium, silicon etc.
303: this first substrate disk is carried out thinning back side handle, make this blind hole 14, form through hole 14 from backside openings.
Concrete, referring to Fig. 7, this first substrate disk is carried out reduction processing, promptly attenuate is carried out at the back side of the first substrate disk W1 shown in Fig. 6, make blind hole 14 form through hole 14 from the backside openings of the first substrate disk.Wherein, can adopt the mode of modes such as mechanical lapping, chemico-mechanical polishing, chemical corrosion, plasma etching or its combination to the thinning back side of substrate disk.
304: the bonding material that intermediate layer B1 is positioned at via bottoms from this first substrate disk back side is removed.
Concrete, as shown in Figure 8: the structure chart that both had been the first substrate disk after the bonding material of the intermediate layer B 1 of through hole 14 bottoms among the first substrate disk W1 is removed, wherein, the method for removing the bonding material of intermediate layer B1 can be but be not limited to the mode of chemical corrosion, plasma etching or the two combination.
In addition, can also be further from the back side of this substrate disk to through hole 14 inner deposit side wall insulating layer and diffusion impervious layers, to protect.The method of carrying out carrying out in the method and 301 of deposit deposit in blind hole 14 is identical, repeats no more herein.
305: with the metal seed layer F11 on this auxiliary disk F1 is starting point, utilizes bottom-up plating mode filled conductive metal in the through hole 14 of this ground floor substrate disk.
Concrete, referring to Fig. 9,, be starting point with the metal seed layer F11 that assists disk F1 because through hole 14 is communicated with metal seed layer in the bottom, adopt bottom-up plating mode that conducting metal is filled to through hole 14.Conducting metal is to insert from the bottom of through hole 14, until the opening part that is filled to through hole 14.Therefore, in the process of filled conductive metal, through hole 14 can be filled up by conducting metal fully, is difficult for producing the space.The structure chart of having filled the substrate disk behind the conducting metal as shown in Figure 9.Wherein, the metal of filling includes but not limited to that copper, tungsten, gold, nickel, chromium etc. can electroplated metal, or the alloy of its mixing.
306: make metal salient point 17 at this ground floor substrate disk back side, and bonding is carried out with the front that has the second substrate disk of circuit devcie in the back side of the first substrate disk.
Concrete, as shown in figure 10,,, make the metal salient point 17 that is used to be electrically connected the second substrate disk at the opening part of the through hole 14 of having filled conducting metal at the back side of the first substrate disk.The metal material of making metal salient point 17 can be but be not limited to one or more materials in copper, silver, tin, gold, indium, the lead, or the alloy material of above-mentioned material.The manufacture method of metal salient point 17 can be but be not limited to be modes such as plating, sputter.
Structure chart behind the first substrate disk and the second substrate wafer bonding as shown in figure 11.Conducting metal and the pad on the second substrate disk or the conductive plate etc. of filling in the through hole 14 of the first substrate disk can be in contact with one another, realized that thus the first substrate disk is electrically connected with second the vertical of substrate disk, utilize bonding material that two substrate disks are carried out bonding again, just realized the three-dimensional interconnection of two substrate disks.
Afterwards, as shown in figure 12, can further remove the intermediate layer B1 and the auxiliary disk F1 at the positive place of the first substrate disk again, the first substrate disk and the second substrate disk behind the reservation bonding.
Pass through aforesaid operations, just finished the perpendicular interconnection of two-layer substrate disk, if also need be again during bonding the 3rd substrate disk in the front of the first substrate disk, then connect up again by carrying out metal in the front of the first substrate disk, and make new pad 18 at the opening part of through hole 14, carry out three-dimensional interconnection and integrated for the 3rd substrate disk.Then, according to the method for among the 301-306 the first substrate disk being handled, the 3rd substrate disk is handled, after on the 3rd substrate disk, making through hole and filling metal, just the 3rd substrate disk can be bonded on the first substrate disk, just realize the perpendicular interconnection of three layers of substrate disk thus.
Referring to Figure 13 shows that the structural representation that adopts said method to realize three layers of substrate disk three-dimensional interconnection.Wherein, W1 is the first substrate disk, and W2 is the second substrate disk that is in bottommost, and W3 is the 3rd substrate disk that is in top layer; 16, the 36 three-dimensional interconnection copper posts that are illustrated respectively in substrate disk W1, the last making of W3; 17, the metal salient point made of 37 back sides that are illustrated respectively in substrate disk W1, W3; 18,28,38 pads that are used for bonding or encapsulation of representing substrate disk W1, W2, W3 front respectively; 19,29 bonded layers that are illustrated respectively in substrate disk W1, W2 front.
More than realized the three-dimensional interconnection of three layers of substrate disk.What can expect is that the method for the embodiment of the invention can also be used for the three-dimensional interconnection of MULTILAYER SUBSTRATE disk.When needing the new substrate disk of bonding, then need to remove the auxiliary disk on the 3rd substrate disk, and on the 3rd substrate disk, make interconnect pad; Interconnect for new substrate disk.At this moment, it is the first substrate disk in 301 that new substrate disk is equal to, all substrate disks of bonding are all the second substrate disk in 306 as an integral body etc., according to the method among the 301-306 to new substrate disk is handled, the back side of new substrate disk is bonded to the front of the 3rd substrate disk, has promptly realized the bonding of new substrate disk.In like manner, repeat bonding according to the method described above, just can realize the bonding of MULTILAYER SUBSTRATE disk, repeat no more herein.
From above-mentioned manufacturing process as can be seen, the technical scheme that the embodiment of the invention provides has following advantage: adopt deep earlier erosion to make blind hole, back attenuate is made the mode of through hole, can not cause horizontal undercutting, the etching speed difference at different size and diverse location place also can not influence the carrying out of subsequent technique; Because the supporting role of auxiliary disk finally can make the single-layer substrate disk very thin, helps realizing the integrated interconnection of the highdensity three-dimensional of substrate disk.In addition, provide the metal seed layer of electroplating usefulness by auxiliary disk, when through hole is filled metal, metal seed layer is with the end sealing of through hole, directly adopt bottom-up plating mode to fill, therefore can allow early stage on the substrate disk, to make darker blind hole, improve three-dimensional integrated depth-to-width ratio; And bottom-up plating mode has been avoided electroplating hole and the crack phenomenon that blind hole occurs, and has reduced technology difficulty, has shortened process time.
The embodiment of the invention circuit devcie is carried out three-dimensional when integrated, by on the substrate disk, making blind hole, and the substrate disk is carried out attenuate make blind hole form through hole, utilize auxiliary disk to adopt bottom-up plating mode in through hole, to fill metal, avoided electroplating hole and the slit that blind hole may occur, realize the three-dimensional interconnection of circuit devcie high density, high-aspect-ratio, also reduced the technology difficulty of the integrated and interconnection of circuit device three-dimensional simultaneously.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1, the integrated method of a kind of circuit device three-dimensional is characterized in that, described method comprises:
Blind hole is made in front at the first substrate disk that has circuit devcie;
The front and the auxiliary disk of the described first substrate disk are carried out bonding, and wherein, the one side with the first substrate wafer bonding on the described auxiliary disk has the metal seed layer of electroplating usefulness;
The described first substrate disk is carried out thinning back side handle, make described blind hole opening form through hole;
With the described metal seed layer on the described auxiliary disk is starting point, adopts bottom-up plating mode, filled conductive metal in described through hole;
Bonding is carried out with the front that has the second substrate disk of circuit devcie in the back side of the described first substrate disk.
2, the integrated method of circuit device three-dimensional according to claim 1 is characterized in that, bonding is carried out with the front that has the second substrate disk of circuit devcie in the described back side with the first substrate disk, comprising:
Through hole at the described first substrate disk back side makes metal salient point, utilizes described metal salient point that the described first substrate disk is electrically connected with the second substrate disk;
Utilize bonding material that bonding is carried out at the back side of the described first substrate disk and the front of the second substrate disk.
3, the integrated method of circuit device three-dimensional according to claim 1 is characterized in that, described front and auxiliary disk with the described first substrate disk carries out bonding, comprising:
Utilize high molecular polymer as bonding material, the one side that the described first substrate disk and auxiliary disk is had metal seed layer is carried out bonding, but described bonding material is the macromolecule polymer material of chemical corrosion or photosensitive sex change.
4, the integrated method of circuit device three-dimensional according to claim 3 is characterized in that, describedly before the filled conductive metal, also comprises in described through hole:
The bonding material that will be positioned at via bottoms is removed.
5, the integrated method of circuit device three-dimensional according to claim 1 is characterized in that, described front and auxiliary disk with the described first substrate disk carries out also comprising before the bonding:
At described first substrate disk front deposit side wall insulating layer and the diffusion impervious layer in blind hole;
The described back side with the first substrate disk carries out with the front that has the second substrate disk of circuit devcie also comprising before the bonding:
From the back side of the described first substrate disk to inner deposit side wall insulating layer of through hole and diffusion impervious layer.
6, the integrated method of circuit device three-dimensional according to claim 1 is characterized in that, the described back side with the first substrate disk carries out with the front that has the second substrate disk of circuit devcie also comprising after the bonding:
Remove described auxiliary disk, and on the described first substrate disk, make interconnect pad;
Blind hole is made in front at the 3rd substrate disk that has circuit devcie;
Bonding is carried out in the front of described the 3rd substrate disk and new auxiliary disk, and wherein, the one side with the 3rd substrate wafer bonding on the described auxiliary disk newly has the metal seed layer of electroplating usefulness;
Described the 3rd substrate disk is carried out thinning back side handle, make the blind hole opening on described the 3rd substrate disk form through hole;
With the described metal seed layer on the described auxiliary disk newly is starting point, adopts filled conductive metal in the through hole of bottom-up plating mode on described the 3rd substrate disk;
Bonding is carried out at the back side of described the 3rd substrate disk and the front of the first substrate disk.
7, the integrated method of circuit device three-dimensional according to claim 1 is characterized in that, describedly the described first substrate disk is carried out thinning back side handles, and comprising:
Adopt the mode of mechanical lapping, chemico-mechanical polishing, chemical corrosion or reactive ion etching, and the combination in any mode is carried out attenuate to the described first substrate disk back side.
8, the integrated method of circuit device three-dimensional according to claim 1 is characterized in that, blind hole is made in described front at the first substrate disk that has circuit devcie, comprising:
Utilize the reaction ion deep etching technology, or laser ablation technology, or Machining Technology is in the positive blind hole of making of the first substrate disk.
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| CN200910092403A CN101645401A (en) | 2009-09-10 | 2009-09-10 | Circuit device three-dimensional integrative method |
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| CN200910092403A CN101645401A (en) | 2009-09-10 | 2009-09-10 | Circuit device three-dimensional integrative method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101840856A (en) * | 2010-04-23 | 2010-09-22 | 中国科学院上海微系统与信息技术研究所 | Etch tank adopted in process of packaging and manufacturing TSV (Through Silicon Via) wafer and preparation process |
| CN103391077A (en) * | 2013-07-29 | 2013-11-13 | 电子科技大学 | Three dimensional integrated solid state relay |
| CN103457589A (en) * | 2013-07-29 | 2013-12-18 | 电子科技大学 | Optical integration solid state relay |
| CN108910819A (en) * | 2018-07-13 | 2018-11-30 | 河南汇纳科技有限公司 | A kind of three-dimensionally integrated method of multisensor that MEMS is compatible |
| CN110727046A (en) * | 2018-07-16 | 2020-01-24 | 上海新微技术研发中心有限公司 | Method for manufacturing optical coupling end face in three-dimensional integrated optical interconnection chip |
| CN113155348A (en) * | 2021-02-26 | 2021-07-23 | 西安微电子技术研究所 | Piezoresistive pressure sensor signal processing module and integration method thereof |
| CN113562685A (en) * | 2021-07-26 | 2021-10-29 | 美满芯盛(杭州)微电子有限公司 | Blind hole structure of MEMS device |
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2009
- 2009-09-10 CN CN200910092403A patent/CN101645401A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101840856A (en) * | 2010-04-23 | 2010-09-22 | 中国科学院上海微系统与信息技术研究所 | Etch tank adopted in process of packaging and manufacturing TSV (Through Silicon Via) wafer and preparation process |
| CN103391077A (en) * | 2013-07-29 | 2013-11-13 | 电子科技大学 | Three dimensional integrated solid state relay |
| CN103457589A (en) * | 2013-07-29 | 2013-12-18 | 电子科技大学 | Optical integration solid state relay |
| CN103457589B (en) * | 2013-07-29 | 2017-12-01 | 电子科技大学 | A kind of light integrates solid-state relay |
| CN108910819A (en) * | 2018-07-13 | 2018-11-30 | 河南汇纳科技有限公司 | A kind of three-dimensionally integrated method of multisensor that MEMS is compatible |
| CN110727046A (en) * | 2018-07-16 | 2020-01-24 | 上海新微技术研发中心有限公司 | Method for manufacturing optical coupling end face in three-dimensional integrated optical interconnection chip |
| CN110727046B (en) * | 2018-07-16 | 2021-07-23 | 上海新微技术研发中心有限公司 | Method for manufacturing optical coupling end face in three-dimensional integrated optical interconnection chip |
| CN113155348A (en) * | 2021-02-26 | 2021-07-23 | 西安微电子技术研究所 | Piezoresistive pressure sensor signal processing module and integration method thereof |
| CN113155348B (en) * | 2021-02-26 | 2023-09-12 | 西安微电子技术研究所 | Piezoresistive pressure sensor signal processing module and integration method thereof |
| CN113562685A (en) * | 2021-07-26 | 2021-10-29 | 美满芯盛(杭州)微电子有限公司 | Blind hole structure of MEMS device |
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