CN208753310U - Semiconductor devices - Google Patents
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- CN208753310U CN208753310U CN201821514032.3U CN201821514032U CN208753310U CN 208753310 U CN208753310 U CN 208753310U CN 201821514032 U CN201821514032 U CN 201821514032U CN 208753310 U CN208753310 U CN 208753310U
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- insulating medium
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Abstract
There is provided a kind of semiconductor devices, including at least one interconnection structure, comprising: substrate, substrate have upper surface and lower surface opposite to the upper surface；The first insulating medium layer positioned at substrate lower surface；Positioned at the second insulating medium layer of upper surface of substrate；First connection gasket is set in the first insulating medium layer；Metal connecting piece, through the second part of the first part of the first insulating medium layer, substrate and the second insulating medium layer, to connect the first connection gasket, wound hole is formed in around metal connecting piece and through substrate；Liner dielectric layer, is formed in wound hole, and the film thickness of liner dielectric layer is less than wound hole by the gap half of first surface to second surface, to form the air gap；Liner capping, is formed on liner dielectric layer, and with gas-tight seal gas gap, the air gap surrounds metal connecting piece；And second connection gasket, it is set in the second insulating medium layer and is located in liner capping, the second connection gasket connects metal connecting piece.
Description
Technical field
The utility model belongs to technical field of manufacturing semiconductors, and in particular to a kind of semiconductor devices.
Background technique
With the rapid development of semiconductor fabrication techniques, semiconductor devices is in order to reach faster arithmetic speed, bigger
Data storage amount and more functions, semiconductor chip develop to more high integration direction.And the integrated level of semiconductor chip
Higher, the characteristic size of semiconductor devices is smaller.
Three dimensional integrated circuits are prepared using advanced chip Stack Technology, are the chip stacks that will have different function
Build up the integrated circuit with three-dimensional structure.Compared to the integrated circuit of two-dimensional structure, the Stack Technology of three dimensional integrated circuits is not
Three dimensional integrated circuits signaling path can only shortened, the speed of service of three dimensional integrated circuits can also be made to accelerate；In short,
The Stack Technology of three dimensional integrated circuits have the advantage that meet semiconductor devices higher performance, smaller szie, more low-power consumption with
And more multi-functional demand.
Realize the Stack Technology of three dimensional integrated circuits, through silicon via technology (TSV:TroughSiliconVia) is new one
The technology that generation enables the chip stacked to interconnect is current popular one of key technology.TSV technology makes in integrated circuit
The signaling path of chip chamber is shorter, therefore the speed of service of three dimensional integrated circuits is faster, and ghost effect and power consumption are lower, ruler
Very little smaller and weight is lighter, and the limitation of stacked chips number is not present.
However, the problems such as that there are RC retardation ratios is poor in the semiconductor devices that the prior art is formed, poor reliability.
Utility model content
To overcome drawbacks described above, the utility model provides a kind of semiconductor devices and preparation method thereof.
On the one hand the utility model provides a kind of semiconductor devices, including at least one interconnection structure, the interconnection structure
It include: substrate, the substrate has upper surface and the lower surface opposite with the upper surface；Positioned at the of the substrate lower surface
One insulating medium layer；Positioned at the second insulating medium layer of the upper surface of substrate；First connection gasket is set to first insulation
In dielectric layer；Metal connecting piece is situated between through the second part of first insulating medium layer, the substrate and second insulation
The first part of matter layer, to connect first connection gasket, wound hole is formed in around the metal connecting piece, described to surround
Hole at least appears the first surface of the metal connecting piece, the second surface for appearing the substrate and bottom surface；Liner dielectric layer, shape
In wound hole described in Cheng Yu and cover the first surface, the second surface and the bottom surface, the film of the liner dielectric layer
Thickness is less than the wound hole by the gap half of the first surface to the second surface, to form the air gap；
Liner capping, is formed on the liner dielectric layer, and with the gas-tight sealing the air gap, the air gap surrounds the gold
Belong to connector；And second connection gasket, it is set in second insulating medium layer and is located in liner capping, described the
Two connection gaskets connect the metal connecting piece.
An embodiment according to the present utility model, the substrate include in silicon, germanium, SiGe, silicon carbide and GaAs
It is one or more.
Another embodiment according to the present utility model, first insulating medium layer and the second insulating medium layer packet
Include one of silicon nitride, silica and silicon oxynitride or a variety of.
Another embodiment according to the present utility model, first connection gasket, the metal connecting piece and described second
Connection gasket includes one of tungsten, copper, aluminium, silver, platinum and their alloy or a variety of.
Another embodiment according to the present utility model, the wound hole run through second of first insulating medium layer
The first part of part, the substrate and second insulating medium layer.
Another embodiment according to the present utility model, the vertical range of the first surface to the second surface are
0.1-5μm。
Include the air gap (airgap) in the interconnection structure of semiconductor devices, can effectively reduce in semiconductor devices
Parasitic capacitance, reduce RC retardation ratio effect, improve the semiconductor devices speed of service and reliability.And in the utility model method
The air gap is uniform in the semiconductor devices of preparation, improves the reliability of semiconductor devices.
Detailed description of the invention
Its example embodiment is described in detail by referring to accompanying drawing, above and other feature and advantage of the utility model will
It becomes readily apparent from.
Fig. 1 is the schematic sectional view of the semiconductor devices of the utility model embodiment.
Fig. 2A to 2M is to illustrate to prepare the schematic of semiconductor devices process according to an embodiment of the present invention
Cross-sectional view.
Fig. 3 A to 3K is the signal for preparing semiconductor devices process illustrated according to another embodiment of the utility model
Property cross-sectional view.
Fig. 4 A to 4J is the signal for preparing semiconductor devices process illustrated according to another embodiment of the utility model
Property cross-sectional view.
Wherein, the reference numerals are as follows:
1: substrate
21: the first insulating medium layers
The first part of 211: the first insulating medium layers
The second part of 212: the first insulating medium layers
22: the second insulating medium layers
The first part of 221: the second insulating medium layers
The second part of 222: the second insulating medium layers
223: third insulating medium layer
224: dielectric layer
23: groove
3: metallic conductor
31: the first connection gaskets
32: metal connecting piece
33: the second connection gaskets
4: separator
41: liner dielectric layer
42: liner capping
5: the air gap
61: the first mask layers
62: the second mask layers
71: through-hole
72: wound hole
721: first surface
722: second surface
723: bottom surface
Specific embodiment
The terms " semiconductor devices " typically refer to the solid-state device comprising one or more semiconductor materials.Semiconductor
The example of device includes logic device, memory device and diode and other.In addition, term " semiconductor devices " can refer into
Product device or refer to become finished devices before each processing stage at sub-assembly or other structures.Depending on wherein using
The context of term " substrate ", the term can refer to wafer scale type substrate or refer to singulated bare die grade substrate.The skill of related fields
Art personnel are it will be recognized that the suitable step of method described herein can be executed with wafer scale or with bare die grade.In addition, unless
Context is indicated otherwise, and otherwise conventional semiconductor manufacturing technology can be used to be formed for structure disclosed herein.Material (can illustrate
For) deposited using chemical vapor deposition, physical vapour deposition (PVD), atomic layer deposition, spin coating and/or other suitable technologies.Class
As, material (for example) can be moved using plasma etching, wet etching, chemical-mechanical planarization or other suitable technologies
It removes.
The terms such as herein "upper", "lower", only relative concept or be reference with the normal operating condition of product each other
, and should not be regarded as restrictive.The similar term such as " first ", " second ", " third ", is not offered as any suitable
Sequence, quantity or importance, and be used only to distinguish different component parts.
Firstly, as shown in Figure 1, semiconductor devices includes at least one interconnection structure, in figure by taking two interconnection structures as an example
Illustrate the design of the utility model.Interconnection structure include substrate 1, the first insulating medium layer 21, the second insulating medium layer 22,
Metallic conductor 3 and separator 4.First insulating medium layer 21 and the second insulating medium layer 22 are respectively laminated on two phases of substrate 1
To on surface.Metallic conductor 3 includes being set to the first connection gasket 31 in the first insulating medium layer 21, being set to the second dielectric
The second connection gasket 33 in layer 22 and through substrate 1 and the first connection gasket 31 of connection is connected with the metal of the second connection gasket 33
Part 32.Separator 4 is formed by insulating dielectric materials, around metal connecting piece 32, and the air gap 5 is sealed in separator 4.Half
Conductor device can also be combined with other layers, be such as, but not limited to laminated on another substrate 1.
Substrate 1 can be any suitable semiconductor material, such as silicon, germanium, SiGe, silicon carbide and GaAs etc..
First insulating medium layer 21 and the second insulating medium layer 22 may be, but not limited to, SiO2, SiN, SiON etc..The
One insulating medium layer 21 may include first part 211 and the second part 212 of stacking.
First part 211 and the second part of the first insulating medium layer 21 is arranged in first connection gasket 31 of metallic conductor 3
Between 212.Second connection gasket 33 is arranged in the second insulating medium layer 22.Metal connecting piece 32 connects through the connection of substrate 1 first
Connection pad 31 and the second connection gasket 33.The metal of metallic conductor 3 can be selected from tungsten, copper, aluminium, silver, platinum or their alloy.First connects
Connection pad 31, metal connecting piece 32 and the second connection gasket 33 can be same metal, be also possible to not same metal.
Separator 4 is formed by insulating dielectric materials, such as SiO2, SiN, SiON etc..
Include the air gap (airgap) in the interconnection structure of semiconductor devices, can effectively reduce in semiconductor devices
Parasitic capacitance, reduce RC retardation ratio effect, improve the semiconductor devices speed of service and reliability.
The semiconductor devices of the utility model can be formed in several ways, such as mode shape shown in Fig. 2A to 2M
At.As shown in Figure 2 A, include the first part 221 of the second insulating medium layer, substrate 1 and including the first connection gasket 31 the
221 surface of first part of second insulating medium layer of the stacked structure of one insulating medium layer 22 forms patterned first mask
Layer 61.First mask layer 61 can be photoresist layer.
As shown in Figure 2 B, the first part 221 with the first mask layer 61 for the second insulating medium layer of mask etching, substrate 1
The through-hole 71 for exposing the first connection gasket 31 is formed with the first insulating medium layer 21.The first connection gasket 31 exposed, which can be, exposes it
Surface can also etch a part of the first connection gasket 31, the situation of etching a part be shown in figure, but and as limit, ability
Field technique personnel can reasonably select according to actual process conditions.It forms through-hole 71 and removes the first mask layer 61 later.
Later, metal is filled into full through-hole 71.It can be as shown in Figure 2 C, by the modes such as sputtering or being electroplated for metal example
Through-hole 71 is expired in such as Cu filling, while the surface of the first part 221 of the second insulating medium layer also covers one layer of metal layer.So
Afterwards, such as by way of chemical mechanical grinding (CMP) 221 surface of first part for being covered on the second insulating medium layer is removed
Metal layer exposes the surface (as shown in Figure 2 D) of the first part 221 of the second insulating medium layer.The metal being filled in through-hole 71
Form the metal connecting piece 32 of metallic conductor 3.Metal connecting piece 32 is connect with the first connection gasket 31.
Then, as shown in Figure 2 E, patterned second mask is formed on 221 surface of first part of the second insulating medium layer
Layer 62.Second mask layer 62 is also possible to photoresist layer.
As shown in Figure 2 F, the first part 221 with the second mask layer 62 for the second insulating medium layer of mask etching, substrate 1
The wound hole 72 for surrounding metal connecting piece 32 is formed with the first insulating medium layer 21, wound hole 72 exposes the table of the first connection gasket 31
Face.Wound hole 72 exposes 32 outer surface of metal connecting piece, i.e. first surface 721.Wound hole 72, which exposes, runs through the first dielectric
The second part 212 of layer, the first part 221 of substrate 1 and the second insulating medium layer side wall, i.e. second surface 722.It surround
The surface of the first connection gasket 31 is exposed in 72 bottom of hole and/or the surface of the first insulating medium layer is known as bottom surface 723.Wound hole 72
Cross section can be circle, polygon etc..The cross section of metal connecting piece 32 can be circle, polygon etc..Metal connecting piece
32 first surface 721 to substrate second surface 722 vertical range can be 0.1-5 μm.
As shown in Figure 2 G, liner dielectric layer 41 is formed to cover first surface 721, second surface 722 and bottom surface 723.It is interior
Lining dielectric layer 41 can be SiN etc., can form liner dielectric layer 41 by modes such as atomic layer depositions.
Later, sealing wound hole 72 forms the separator 4 around metal connecting piece 32, and encapsulation forms air in separator 4
The surface of the first part 221 of gap 5, the surface of separator 4 and the second insulating medium layer and the surface of metal connecting piece 32 are flat
Together.It can be that plasma-enhanced vapor is first passed through shown in Fig. 2 H is heavy on the surface of the first part 221 of the second insulating medium layer
Product insulating dielectric materials form third insulating medium layer 223, and wherein the upper end of wound hole 72 is filled with insulating dielectric materials.Then
The insulating dielectric materials on first part 221 surface of the height beyond the first insulating medium layer can be removed by chemical mechanical grinding
Expose the first part 221 of the second insulating medium layer and the surface of metal connecting piece 32.Wherein the upper end of wound hole 72 is filled
First surface 721, second surface 722 and bottom surface 723 are deposited with liner medium by the liner capping 42 that insulating dielectric materials are formed
The sealing of wound hole 72 of layer 41 forms the separator 4 including the air gap 5.Third insulating medium layer 223 can use and liner
The identical or different material of dielectric layer 41 is formed, and in figure by taking same material as an example, but is not intended to be limited to same material.Isolation
The surface of the first part 211 of the surface of part 4 and the first insulating medium layer and the flush of metal connecting piece 32 are (such as Fig. 2 I institute
Show).
As shown in fig. 2j, in the upper table of the first part 221 of the second insulating medium layer, metal connecting piece 32 and separator 4
The second part 222 that face deposits the second insulating medium layer covers the surface of the first part 221 of the second insulating medium layer, separator
4 surface and the surface of metal connecting piece 32.The second part 222 of second insulating medium layer can be with the second insulating medium layer
First part 221 is formed using identical material, can also be formed using different materials.
As shown in figure 2k, the surface that groove 23 exposes separator 4 is formed on the second part 222 of the second insulating medium layer
With the surface of metal connecting piece 32.
The second connection gasket 33 is formed finally, filling metal to groove 23.Second connection gasket 33 and 32 phase of metal connecting piece
Even.Second connection gasket 33, metal connecting piece 32 and the first connection gasket 31 constitute metallic conductor 3.As shown in figure 2l, metal is filled
To groove 23, can be expires groove 23 for fillings such as metal such as Cu by the modes such as sputtering or being electroplated, while the first insulation is situated between
The surface of the second part 212 of matter layer also covers one layer of metal layer.Then, it such as is removed and is covered by way of chemical mechanical grinding
The metal layer on 222 surface of second part of the second insulating medium layer is covered, the second part 222 of the second insulating medium layer is exposed
With the surface (as shown in figure 2m) of the first connection gasket 31.The first part 221 of second insulating medium layer and the second insulating medium layer
Second part 222 form semiconductor devices the second insulating medium layer 22 (as shown in Figure 1).
Fig. 3 A-3K shows the mistake of formation the utility model semiconductor devices in another embodiment of the utility model
Journey.Process shown in Fig. 3 A-3H is identical as process shown in Fig. 2A -2H in this embodiment, and details are not described herein.
As shown in fig. 31, etching or other modes remove part third insulating medium layer 223 and the formation of liner dielectric layer 41
Groove 23 exposes the surface of separator 4 and the surface of metal connecting piece 32.
The second connection gasket 33 is formed finally, filling metal to groove 23.Second connection gasket 33 and 32 phase of metal connecting piece
Even.First connection gasket 31, metal connecting piece 32 and the second connection gasket 33 constitute metallic conductor 3.Metal is filled to groove 23
The fillings such as metal such as Cu can be expired groove 23 by the modes such as sputtering or being electroplated, while third is exhausted as shown in figure 3j by mode
The surface of edge dielectric layer 223 also covers one layer of metal layer.Then, such as by way of chemical mechanical grinding remove and be covered on
The metal layer on three insulating medium layers, 223 surface exposes surface (such as Fig. 3 K of third insulating medium layer 223 and the second connection gasket 33
It is shown).The first part 221 of third insulating medium layer 223, liner dielectric layer 41 and the second insulating medium layer forms semiconductor device
Second insulating medium layer 22 (as shown in Figure 1) of part.
Fig. 4 A-4J shows the mistake of formation the utility model semiconductor devices in another embodiment of the utility model
Journey.Process shown in Fig. 4 A-4F is identical as process shown in Fig. 2A -2F in this embodiment, and details are not described herein.
As shown in Figure 4 G, dielectric layer 224 is formed to cover first surface 721, second surface 722 and bottom surface 723.Liner is situated between
Matter layer 224 can be SiN etc., can form dielectric layer 224 by modes such as atomic layer depositions.Later, continued growth is to seal
First surface 721, second surface 722 and bottom surface 723 are formed with the wound hole 72 of dielectric layer.Wherein the upper end of wound hole 72 is filled out
The insulating dielectric materials filled form liner capping 42 and form separator 4, form the air gap 5 inside separator 4.
As shown at figure 4h, etching or other modes remove part dielectric layer 224 and form the surface that groove 23 exposes separator 4
With the surface of metal connecting piece 32.
The second connection gasket 33 is formed finally, filling metal to groove 23.Second connection gasket 33 and 32 phase of metal connecting piece
Even.First connection gasket 31, metal connecting piece 32 and the second connection gasket 33 constitute metallic conductor 3.Metal is filled to groove 23
The fillings such as metal such as Cu can be expired groove 23, while dielectric layer by the modes such as sputtering or being electroplated as shown in fig. 41 by mode
224 surface also covers one layer of metal layer.Then, such as by way of chemical mechanical grinding remove and be covered on dielectric layer 224
The metal layer on surface exposes the surface (as shown in fig. 4j) of dielectric layer 224 and the second connection gasket 33.Dielectric layer 224 and second is absolutely
The first part 221 of edge dielectric layer forms the second insulating medium layer 22 (as shown in Figure 1) of semiconductor devices.
It is uniform with the air gap in the semiconductor devices of the utility model method preparation, improve the reliable of semiconductor devices
Property.
Certainly, the utility model can also have other various embodiments, without departing substantially from the spirit of the present invention and its essence
In the case of, those skilled in the art work as can make various corresponding changes and modifications, but these according to the utility model
Corresponding changes and modifications all should belong to the protection scope of the utility model the attached claims.
Claims (6)
1. a kind of semiconductor devices, including at least one interconnection structure, which is characterized in that the interconnection structure includes:
Substrate, the substrate have upper surface and the lower surface opposite with the upper surface；
The first insulating medium layer positioned at the substrate lower surface；
Positioned at the second insulating medium layer of the upper surface of substrate；
First connection gasket is set in first insulating medium layer；
Metal connecting piece, through the second part, the substrate and second insulating medium layer of first insulating medium layer
First part, to connect first connection gasket, wound hole is formed in around the metal connecting piece, and the wound hole is extremely
Appear the first surface of the metal connecting piece, the second surface for appearing the substrate and bottom surface less；
Liner dielectric layer is formed in the wound hole and covers the first surface, the second surface and the bottom surface, institute
Gap half of the film thickness of liner dielectric layer less than the wound hole by the first surface to the second surface is stated,
To form the air gap；
Liner capping, is formed on the liner dielectric layer, and with the gas-tight sealing the air gap, the air gap surrounds institute
State metal connecting piece；And
Second connection gasket is set in second insulating medium layer and is located in liner capping, second connection gasket
Connect the metal connecting piece.
2. semiconductor devices according to claim 1, which is characterized in that the substrate includes silicon, germanium, SiGe, carbonization
One of silicon and GaAs are a variety of.
3. semiconductor devices according to claim 1, which is characterized in that first insulating medium layer and described second is absolutely
Edge dielectric layer includes one of silicon nitride, silica and silicon oxynitride or a variety of.
4. semiconductor devices according to claim 1, which is characterized in that first connection gasket, the metal connecting piece
It with second connection gasket include one of tungsten, copper, aluminium, silver, platinum and their alloy or a variety of.
5. semiconductor devices according to claim 1, which is characterized in that the wound hole runs through first dielectric
The first part of second part of layer, the substrate and second insulating medium layer.
6. semiconductor devices according to claim 1, which is characterized in that the first surface to the second surface hangs down
Straight distance is 0.1-5 μm.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821514032.3U CN208753310U (en) | 2018-09-14 | 2018-09-14 | Semiconductor devices |
| PCT/CN2019/105588 WO2020052630A1 (en) | 2018-09-14 | 2019-09-12 | Semiconductor device and methods for manufacturing thereof |
| US17/199,328 US11776848B2 (en) | 2018-09-14 | 2021-03-11 | Semiconductor device and methods for manufacturing thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821514032.3U CN208753310U (en) | 2018-09-14 | 2018-09-14 | Semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208753310U true CN208753310U (en) | 2019-04-16 |
Family
ID=66084522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821514032.3U Active CN208753310U (en) | 2018-09-14 | 2018-09-14 | Semiconductor devices |
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| CN (1) | CN208753310U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020052630A1 (en) * | 2018-09-14 | 2020-03-19 | Changxin Memory Technologies, Inc. | Semiconductor device and methods for manufacturing thereof |
| CN110911383A (en) * | 2018-09-14 | 2020-03-24 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
-
2018
- 2018-09-14 CN CN201821514032.3U patent/CN208753310U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020052630A1 (en) * | 2018-09-14 | 2020-03-19 | Changxin Memory Technologies, Inc. | Semiconductor device and methods for manufacturing thereof |
| CN110911383A (en) * | 2018-09-14 | 2020-03-24 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| US11776848B2 (en) | 2018-09-14 | 2023-10-03 | Changxin Memory Technologies, Inc. | Semiconductor device and methods for manufacturing thereof |
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