CN103681390B - A kind of wafer scale silicon substrate preparation method based on TSV technique - Google Patents
A kind of wafer scale silicon substrate preparation method based on TSV technique Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 97
- 239000000758 substrate Substances 0.000 title claims abstract description 90
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 18
- 239000010703 silicon Substances 0.000 title claims abstract description 18
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 238000009792 diffusion process Methods 0.000 claims abstract description 24
- 238000002161 passivation Methods 0.000 claims abstract description 23
- 238000000708 deep reactive-ion etching Methods 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 38
- 239000010949 copper Substances 0.000 claims description 31
- 238000000151 deposition Methods 0.000 claims description 29
- 229910052802 copper Inorganic materials 0.000 claims description 27
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 25
- 230000004888 barrier function Effects 0.000 claims description 22
- 238000009713 electroplating Methods 0.000 claims description 22
- 238000001259 photo etching Methods 0.000 claims description 20
- 238000004528 spin coating Methods 0.000 claims description 18
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 238000000608 laser ablation Methods 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 abstract description 12
- 238000005516 engineering process Methods 0.000 abstract description 7
- 238000004806 packaging method and process Methods 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract description 4
- 238000005538 encapsulation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 78
- 238000010586 diagram Methods 0.000 description 6
- 238000011049 filling Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000005429 filling process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of wafer scale silicon substrate preparation method based on TSV technique, comprise the following steps: use DRIE technique to prepare the first blind hole in substrate wafer；First blind hole inwall deposition insulating layer, stick/diffusion impervious layer and Seed Layer metal；Electro-coppering in first blind hole, and use CMP to carry out electro-coppering planarization；Pad and passivation layer is prepared at substrate back；DRIE technique is used to prepare the second blind hole in substrate wafer front；Second blind hole inwall deposition insulating layer, and remove bottom insulation layer；/ diffusion impervious layer, Seed Layer is sticked in deposit in second blind hole；Electro-coppering in second blind hole, and planarize；Wiring metal, passivation layer and pad are prepared in substrate wafer front.The present invention can realize the processing of 20:1～30:1 high-aspect-ratio silicon substrate, reduce through-hole side wall deposition insulating layer, stick/diffusion impervious layer and Seed Layer metal and the electroplates in hole technology difficulty, can be used for high density, the processing of small size of systems level encapsulation super thick TSV base plate for packaging.
Description
Technical Field
The invention relates to a preparation method of a wafer-level silicon substrate with a high aspect ratio TSV, and belongs to the technical field of modules and system-level packaging.
Background
The trend of electronic products to be increasingly miniaturized, portable, multifunctional, low in power consumption and low in cost is that two-dimensional and three-dimensional semiconductor packaging technologies cannot meet the requirements.
The TSV (Through Silicon Via) technology can be used for vertically interconnecting the chip and the substrate, effectively shortens an information transmission path, and can realize more functions, higher power and lead-out ends with the same packaging area. TSV technology is the most efficient approach for semiconductor system-in-package. Currently, one of the main applications of Through Silicon Via (TSV) technology is to prepare interposer substrates for chip scale packaging and system packaging.
The traditional TSV adapter substrate manufacturing process comprises the following steps: 1) preparing blind holes in a substrate; 2) depositing a through hole side wall passivation layer on a single surface of the substrate by PECVD; 3) depositing a through hole side wall adhesion/diffusion barrier layer and seed layer metal on the single surface of the substrate by magnetron sputtering; 4) completing through hole metal filling by an electroplating process; 5) flattening the through hole metal; 6) thinning the through hole metal exposed out of the back surface of the substrate; 7) and manufacturing metal wiring, a bonding pad and a protective layer thereof. The traditional TSV transiting substrate preparation method has the following defects or shortcomings:
(1) the PECVD deposited deep hole side wall passivation layer has poor uniformity, the thickness of the bottom insulating layer of the deep hole is only about 1/5 on the top, the coverage rate of the bottom insulating layer is poor, and discontinuous defects are easily generated to seriously influence the insulating effect and the reliability. This also limits the aspect ratio deposition capability of the passivation layer deposition process.
(2) The uniformity of the adhesion/diffusion barrier layer and the seed layer on the side wall of the deep hole deposited by magnetron sputtering is poor, the thickness of the bottom of the deep hole is only 1/5 at the top, the coverage rate of the bottom of the deep hole is poor, and discontinuous defects are easily generated to cause holes during electroplating, so that the reliability of the through hole is seriously influenced. Currently, the deep hole aspect ratio deposition capability of most advanced magnetron sputtering equipment is less than 15:1, which limits the TSV aspect ratio deposition capability.
(3) The depth-to-width ratio is 20: 1-30: 1 deep holes, and the difficulty in realizing a hole-free electroplating filling process is high.
(4) The conventional TSV interposer substrate is limited to the above-mentioned conventional TSV interposer substrate manufacturing process, and the thickness of the TSV interposer substrate is usually less than 200 μm, and the TSV interposer substrate can only be used as an interposer substrate and cannot be directly assembled with a whole circuit board.
Disclosure of Invention
The invention aims to solve the technical problems of deep hole side wall passivation layer, adhesion/diffusion barrier layer, non-uniform deposition thickness of seed layer and insufficient coverage rate of the bottom of a through hole in the traditional TSV substrate processing technology, and provides a preparation method of a high-aspect-ratio TSV wafer level silicon substrate, which reduces the difficulty of deep hole electroplating filling technology and improves the deep hole aspect ratio capacity of 10: 1-15: 1 to 20: 1-30: 1.
The preparation method of the wafer-level silicon substrate based on the TSV process comprises the following process steps:
the method comprises the following steps: preparing a first blind hole on the back of the substrate wafer by adopting a deep reactive ion etching process;
step two: depositing a first insulating layer, a first adhesion layer, a diffusion barrier layer and seed layer metal on the inner wall of the first blind hole and the back surface of the substrate wafer;
step three: electroplating copper in the first blind hole, and performing electroplating copper planarization by adopting a CMP (chemical mechanical polishing) process;
step four: preparing a first bonding pad and a first passivation layer on the back of the substrate wafer;
step five: preparing a second blind hole on the front surface of the substrate wafer by adopting a deep reactive ion etching process;
step six: depositing a second insulating layer on the inner wall of the second blind hole, removing the second insulating layer at the bottom of the second blind hole and exposing the first adhesion barrier layer, the diffusion barrier layer and the seed layer metal in the first blind hole;
step seven: depositing a second adhesion, diffusion barrier layer and seed layer metal on the inner wall of the second blind hole;
step eight: electroplating copper in the second blind hole, and performing electroplating copper planarization by adopting a CMP (chemical mechanical polishing) process;
step nine: and preparing wiring metal, a second passivation layer and a second bonding pad on the front surface of the substrate wafer.
The depth-to-width ratio of the first blind hole is 10: 1-15: 1, and the depth-to-width ratio of the second blind hole is 10: 1-15: 1.
The invention has the beneficial effects that: the method improves the deposition thickness uniformity of the passivation layer, the adhesion/diffusion barrier layer and the seed layer of the TSV deep hole side wall and the coverage rate of the bottom of the through hole, reduces the difficulty of the electroplating filling process of the TSV through hole, and improves the depth-to-width ratio film deposition capacity of the traditional TSV process to 20: 1-30: 1 from 10: 1-12: 1. Can be used for preparing thicker package substrates.
Drawings
Fig. 1 to 9 are process flow diagrams and typical example process flow diagrams of a method for preparing a wafer-level silicon substrate based on a TSV process according to the present invention; wherein,
FIG. 1 is a schematic diagram of etching a first blind via in a silicon substrate wafer.
FIG. 2 is a schematic view of an insulating layer, an adhesion/diffusion barrier layer and a seed layer deposited on the inner wall of the first blind via.
FIG. 3 is a schematic view of copper electroplating and CMP planarization in the first blind via.
FIG. 4 is a schematic diagram of fabricating a back pad and passivation layer.
FIG. 5 illustrates a second blind via etched in a substrate.
FIG. 6 is a schematic view showing the deposition of an insulating layer on the inner wall of the second blind via and the removal of the bottom insulating layer to expose the filling metal.
FIG. 7 is a schematic view of an adhesion/diffusion barrier layer and a seed layer deposited in the second blind via.
FIG. 8 is a schematic view of copper electroplating and CMP planarization in the second blind via.
Fig. 9 is a schematic diagram of substrate wiring and passivation layer preparation.
The reference numbers in the figures illustrate: the substrate wafer 1, a first insulating layer 2 on the side wall of the through hole, a first adhesion/diffusion barrier layer and seed layer 3 on the side wall of the through hole, electroplated copper 4 in the first blind hole, a first pad 5 on the back side, a first passivation layer 6 on the back side, a second insulating layer 7 on the side wall of the through hole, a second adhesion/diffusion barrier layer and seed layer 8 on the side wall of the through hole, electroplated copper 9 in the second blind hole, wiring metal 10 on the front side of the substrate, a second passivation layer 11 on the front side of the substrate, and a second pad 12 on the front side.
Detailed Description
The preparation method of the wafer-level silicon substrate based on the TSV process comprises the following steps of:
the method comprises the following steps: and preparing a first blind hole on the back surface of the substrate wafer by adopting a Deep Reactive Ion Etching (DRIE) process.
Step two: and depositing an insulating layer, an adhesion/diffusion barrier layer and a seed layer on the inner wall of the first blind hole and the back surface of the substrate wafer.
Step three: and electroplating copper in the first blind hole, and performing electroplating copper planarization by adopting a CMP (chemical mechanical polishing) process.
Step four: and preparing a bonding pad and a passivation layer on the back of the substrate wafer.
Step five: and preparing a second blind hole on the front surface of the substrate wafer by adopting a DRIE (drilling DRIE) process.
Step six: and depositing an insulating layer on the inner wall of the second blind hole, and removing the insulating layer at the bottom of the second blind hole to expose the adhesion/diffusion barrier layer and the seed layer metal in the first blind hole.
Step seven: depositing adhesion/diffusion barrier layer and seed layer metal in the second blind hole.
Step eight: and electroplating copper in the second blind hole, and performing electroplating copper planarization by adopting a CMP (chemical mechanical polishing) process.
Step nine: and preparing wiring metal, a passivation layer and a bonding pad on the front surface of the substrate wafer.
Fig. 1 to 9 are process flow diagrams of typical examples of a method for manufacturing a wafer-level silicon substrate based on a TSV process according to the present invention. The preparation method comprises the following process steps:
the method comprises the following steps: firstly, selecting an 8-inch silicon wafer as a substrate material, wherein the thickness of the substrate is 500 mu m; spin-coating photoresist on the back of the substrate wafer 1, and forming a pattern opening through a photoetching process; thirdly, etching a first blind hole I on the substrate wafer 1 by adopting a Deep Reactive Ion Etching (DRIE) process based on a BOSCH technology, wherein the diameter of the first blind hole I is 20-35 mu m, and the depth of the first blind hole I is 300 mu m; and fourthly, stripping the photoresist. As in fig. 1.
① adopting PECVD (plasma enhanced chemical vapor deposition) process to deposit SiO with the thickness of 1-2 mu m on the back surface of the substrate wafer 1 and the inner wall of the first blind hole I2The method comprises the steps of preparing an insulating layer material (a first insulating layer 2), depositing 1000-2000 Å (angstrom) Ti and 5000-8000 Å Cu on the back surface of a substrate wafer 1 and the inner wall of a first blind hole I respectively by adopting a magnetron sputtering process ② to serve as an adhesion/diffusion barrier layer and seed layer metal 3, and referring to fig. 2.
Step three: spin-coating photoresist on the back of a substrate wafer 1, forming a pattern opening through a photoetching process, and exposing a first blind hole I; electroplating copper 4 in the first blind hole I; peeling the photoresist on the surface of the substrate wafer 1; fourthly, removing redundant Ti and Cu on the surface of the substrate wafer 1 by adopting a wet etching process; and fifthly, flattening the electroplated copper 4 by adopting a CMP process. See fig. 3.
① depositing 6000-8000 Å aluminum on the back of the substrate wafer 1 after the third step by adopting a magnetron sputtering process, ② spin-coating photoresist on the surface of the deposited aluminum, forming a pattern opening by adopting a photoetching process, removing excess aluminum on the surface of the substrate wafer 1 by adopting a wet etching process to form a first bonding pad 5, removing the photoresist by ③, and ④ sequentially depositing 6000-8000 Å SiO on the back of the substrate wafer 1 by adopting a PECVD process2And 2000 to 4000 Å Si3N4As a passivation layer 6 over the first pad 5 ⑤ on Si3N4Spin-coating photoresist, forming pattern opening by photolithography process, and etching SiO by dry etching process2And Si3N4Exposing the first pads 5, ⑥ removing the photoresist, see fig. 4.
Step five: spin-coating photoresist on the front side of a substrate wafer 1, forming a pattern opening through a photoetching process, and manufacturing a second blind hole II through a deep reactive ion etching process, wherein the diameter of the second blind hole II is 15-25 mu m, and the depth of the second blind hole II is 200 mu m; and stripping the photoresist. See fig. 5.
① adopting PECVD (plasma enhanced chemical vapor deposition) process to deposit SiO with the thickness of 1-2 mu m on the front surface of the substrate wafer 1 and the inner wall of the second blind hole II2The insulating layer material (second insulating layer 7); ② the laser ablation technique is used to remove the insulating layer 7 material at the bottom of the second blind via II to expose the underlying adhesion/diffusion barrier layer and seed layer metal 3. see FIG. 6.
Step seven: and sequentially depositing 1000-2000A Ti and 5000-8000A Cu on the front surface of the substrate wafer 1 and the inner wall of the second blind hole II which are subjected to the sixth step by adopting a magnetron sputtering process to serve as seed layers 8. See fig. 7.
Step eight: spin-coating photoresist on the front side of the substrate wafer 1 subjected to the seventh step, forming a pattern opening through a photoetching process, and exposing a second blind hole II; electroplating copper 9 in the second blind hole II; peeling the photoresist on the surface of the substrate wafer 1; fourthly, removing redundant Ti and Cu on the surface of the substrate wafer 1 by adopting a wet etching process; and fifthly, flattening the electroplated copper 9 by adopting a CMP process. See fig. 8.
① depositing 6000-8000 Å aluminum on the surface of the substrate wafer 1 after the third step by adopting a magnetron sputtering process, spin-coating photoresist on the surface of the deposited aluminum, forming a pattern opening by a photoetching process, removing excess aluminum on the surface of the substrate wafer 1 by adopting a wet etching process to form wiring metal 10, finally removing the photoresist, ② depositing 6000-8000 Å SiO 2 on the front surface of the substrate wafer 1 on which the wiring metal 10 is formed by adopting a PECVD process2And 2000 to 3000 Å Si3N4As passivation layer material 11; spin-coating photoresist on the surface of the passivation layer material 11, forming a photoetching pattern opening through a photoetching process, and removing redundant SiO in the photoresist opening by adopting a dry etching process2And Si3N4Exposing the wiring metal 10, finally removing the photoresist, ③ performing magnetron sputtering 800-2000 Å Ti, 2000-5000 Å Ni and 100-600 Å Au on the surface of the passivation layer 10 with the opening, spin-coating the photoresist on the surface of the sputtered Au, forming a photoetching pattern opening through a photoetching process, then removing the redundant Ti, Ni and Au on the surface of the substrate wafer 1 by adopting a wet etching process to form a second bonding pad 12, ④ finally removing the photoresist, and referring to fig. 9.
The method fully carries out the two steps of TSV (through silicon via) through hole manufacturing, through hole side wall insulation, deposition of the adhesion/diffusion barrier layer, seed layer and through hole copper electroplating filling, improves the metal uniformity of the through hole side wall insulation layer, the adhesion/diffusion barrier layer and the seed layer, and improves the deposition capacity of the deep hole side wall insulation layer, the adhesion/diffusion barrier layer and the seed layer by 2 times; the deep hole copper electroplating process difficulty is reduced, hole-free copper electroplating in the deep hole can be ensured, and the reliability is improved. The method can ensure that the processing capacity of the TSV process in the aspect ratio is changed from 10: 1-15: 1, and is increased to 20: 1-30: 1.
Claims (3)
1. A preparation method of a wafer-level silicon substrate based on a TSV process is characterized by comprising the following process steps:
the method comprises the following steps: firstly, selecting an 8-inch silicon wafer as a substrate material, wherein the thickness of the substrate is 500 mu m; spin-coating photoresist on the back of the substrate wafer (1) and forming a pattern opening through a photoetching process; thirdly, etching a first blind hole on the substrate wafer (1) by adopting a deep reactive ion etching process, wherein the diameter of the first blind hole is 20-35 mu m, and the depth of the first blind hole is 300 mu m; and fourthly, stripping the photoresist:
① adopting plasma enhanced chemical vapor deposition processSiO with the thickness of 1-2 mu m is deposited on the back surface of the substrate wafer (1) and the inner wall of the first blind hole2② depositing 1000-2000 Å Ti and 5000-8000 Å Cu as an adhesion/diffusion barrier layer and seed layer metal (3) on the back of the substrate wafer (1) and the inner wall of the first blind hole respectively by adopting a magnetron sputtering process;
step three: spin-coating photoresist on the back of a substrate wafer (1), forming a pattern opening through a photoetching process, and exposing a first blind hole; electroplating copper (4) in the first blind hole; peeling the photoresist on the surface of the substrate wafer (1); fourthly, removing redundant Ti and Cu on the surface of the substrate wafer (1) by adopting a wet etching process; adopting CMP process to planarize the electroplated copper (4);
① depositing 6000-8000 Å aluminum on the back of the substrate wafer (1) after the third step by adopting a magnetron sputtering process, ② spin-coating photoresist on the surface of the deposited aluminum, forming a pattern opening by adopting a photoetching process, removing excess aluminum on the surface of the substrate wafer (1) by adopting a wet etching process to form a first bonding pad (5), ③ removing the photoresist, ④ sequentially depositing 6000-8000 Å SiO on the back of the substrate wafer (1) by adopting a PECVD process2And 2000 to 4000 Å Si3N4As a passivation layer (6) over the first pad (5); ⑤ on Si3N4Spin-coating photoresist, forming pattern opening by photolithography process, and etching SiO by dry etching process2And Si3N4Exposing the first pad (5), ⑥ removing the photoresist:
step five: spin-coating photoresist on the front side of a substrate wafer (1), forming a pattern opening through a photoetching process, and manufacturing a second blind hole through a deep reactive ion etching process, wherein the diameter of the second blind hole is 15-25 mu m, and the depth of the second blind hole is 200 mu m; stripping the photoresist:
① adopting a plasma enhanced chemical vapor deposition process to deposit SiO with the thickness of 1-2 mu m on the front surface of the substrate wafer (1) and the inner wall of the second blind hole2② removing the material of the second blind hole bottom insulating layer (7) by laser ablation technique to expose the lower adhesion/diffusion barrier layer and seed layer metal (3);
step seven: depositing 1000-2000A Ti and 5000-8000A Cu in sequence on the front surface of the substrate wafer (1) subjected to the sixth step and the inner wall of the second blind hole by adopting a magnetron sputtering process to serve as a seed layer (8);
step eight: spin-coating photoresist on the front side of the substrate wafer (1) subjected to the seventh step, forming a pattern opening through a photoetching process, and exposing the second blind hole; electroplating copper (9) in the second blind hole; peeling the photoresist on the surface of the substrate wafer (1); fourthly, removing redundant Ti and Cu on the surface of the substrate wafer (1) by adopting a wet etching process; adopting CMP process to planarize the electroplated copper (9);
① depositing 6000-8000 Å aluminum on the surface of the substrate wafer (1) after the third step by adopting a magnetron sputtering process, spin-coating photoresist on the surface of the deposited aluminum, forming a pattern opening by adopting a photoetching process, removing excess aluminum on the surface of the substrate wafer (1) by adopting a wet etching process to form wiring metal (10), finally removing the photoresist, and depositing 6000-8000 Å SiO 2 on the front surface of the substrate wafer (1) on which the wiring metal (10) is formed by adopting a PECVD process by adopting ②2And 2000 to 3000 Å Si3N4As passivation layer material (11); spin-coating photoresist on the surface of the passivation layer material (11), forming a photoetching pattern opening through a photoetching process, and then removing redundant SiO in the photoresist opening by adopting a dry etching process2And Si3N4Exposing the wiring metal (10), finally removing the photoresist, ③ magnetron sputtering 800-2000 Å Ti, 2000-5000 Å Ni and 100-600 Å Au on the surface of the passivation layer (10) with the opening, spin-coating the photoresist on the surface of the sputtered Au, forming a photoetching pattern opening through a photoetching process, then removing the redundant Ti, Ni and Au on the surface of the substrate wafer (1) by adopting a wet etching process to form a second bonding pad (12), and ④ finally removing the photoresist.
2. The method of claim 1, wherein the first blind via aspect ratio is 10:1 to 15: 1.
3. The method of claim 1 or 2, wherein the second blind via aspect ratio is 10:1 to 15: 1.
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| CN108448217A (en) * | 2018-03-01 | 2018-08-24 | 西南科技大学 | The radio frequency microstrip structure of Ti/Ni/Ag material systems |
| CN109622968A (en) * | 2019-02-19 | 2019-04-16 | 南通理工学院 | TSV packaging 3D printer and printing method |
| CN110791746B (en) * | 2019-11-08 | 2021-10-15 | 北京工业大学 | Method and device for rapidly filling vertical silicon through hole with liquid alloy |
| CN110867429A (en) * | 2019-12-09 | 2020-03-06 | 上海先方半导体有限公司 | TSV (through silicon via) adapter plate interconnection structure |
| CN111968953A (en) * | 2020-08-26 | 2020-11-20 | 中国电子科技集团公司第十三研究所 | Through silicon via structure and preparation method thereof |
| CN113161289B (en) * | 2021-04-22 | 2023-05-12 | 浙江集迈科微电子有限公司 | Electroplating process of TSV metal column with high depth-to-width ratio |
| CN113174620B (en) * | 2021-04-22 | 2022-05-03 | 浙江集迈科微电子有限公司 | Electroplating method of plating solution flow velocity reinforced TSV metal column |
| CN113410175B (en) * | 2021-06-15 | 2023-06-02 | 西安微电子技术研究所 | TSV conductive through hole structure preparation method |
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