CN117253872B - Interconnect structure and method for manufacturing interconnect structure - Google Patents
Interconnect structure and method for manufacturing interconnect structure Download PDFInfo
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- CN117253872B CN117253872B CN202311514961.XA CN202311514961A CN117253872B CN 117253872 B CN117253872 B CN 117253872B CN 202311514961 A CN202311514961 A CN 202311514961A CN 117253872 B CN117253872 B CN 117253872B
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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Abstract
The application provides an interconnection structure and a preparation method of the interconnection structure, wherein the interconnection structure comprises a substrate, a first conductive piece, a second conductive piece, a first insulating layer and a second insulating layer, wherein a first groove is formed on one side of a first surface of the substrate, a second groove is formed on one side of a second surface of the substrate, the groove bottom of the second groove is spaced from the first surface, and one end of the first groove is positioned in the second groove and communicated with the second groove; the first conductive piece is positioned in the first groove, the second conductive piece is positioned in the second groove, the first insulating layer is positioned between the first conductive piece and the groove wall of the first groove, and the second insulating layer is positioned between the second conductive piece and the groove wall of the second groove; the first conductive piece is equipped with the portion of inserting towards the one end of second surface, and the second conductive piece is equipped with the groove of inserting towards the one end of first surface, and the portion of inserting inserts the groove, and with inserting the cell wall butt in groove. Therefore, the interconnection structure and the preparation method of the interconnection structure can reduce the contact resistance of the first conductive piece and the second conductive piece.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to an interconnection structure and a method for manufacturing the interconnection structure.
Background
The power signal may reach the transistor through a power supply network (power delivery network, simply PDN) on the front side of the wafer. As moore's law evolves, transistors get smaller, density gets higher, and the number of stacked layers gets more and more. In order to transmit a power supply signal to the transistor, the power supply network needs to pass through multiple layers of the stack, and the electrons lose energy in the process of transmitting to the transistor, so that an IR drop phenomenon occurs, and power loss occurs.
In the related art, in order to improve the IR drop, a wafer back side power supply (backside power delivery networks, abbreviated as BSPDN) technology may be used to transmit a power signal to a transistor, and the BSPDN may connect a pre-buried power rail (buried power rail, abbreviated as BPR) on the front side of the wafer through a through-silicon via (through silicon via, abbreviated as TSV) on the back side of the wafer to implement interconnection between the front side and the back side of the wafer, and transfer a power supply network to the back side of the wafer with sufficient space resources.
However, the contact resistance between the through silicon vias and the embedded power rail is large.
Disclosure of Invention
In view of at least one technical problem described above, embodiments of the present application provide an interconnection structure and a method for manufacturing the interconnection structure, which can reduce contact resistance between a first conductive member and a second conductive member.
The embodiment of the application provides the following technical scheme:
a first aspect of embodiments of the present application provides an interconnect structure, including: the substrate comprises a first surface and a second surface which are opposite in the thickness direction and are arranged at intervals, one side of the first surface of the substrate is provided with a first groove, one side of the second surface of the substrate is provided with a second groove, the bottom of the second groove is arranged at intervals with the first surface, and one end of the first groove, which is close to the second surface, is positioned in the second groove and is communicated with the second groove; the first conductive piece is positioned in the first groove, the second conductive piece is positioned in the second groove, the first insulating layer is positioned between the first conductive piece and the groove wall of the first groove, and the second insulating layer is positioned between the second conductive piece and the groove wall of the second groove; the first conductive piece is provided with the portion of inserting towards the one end of second surface, and the second conductive piece is provided with the groove of inserting towards the one end of first surface, and the portion of inserting is located in the groove of inserting, and with the cell wall butt in the groove of inserting.
According to the interconnection structure provided by the embodiment of the application, the insertion part is arranged at one end, facing the second surface, of the first conductive piece, the insertion groove is arranged at one end, facing the first surface, of the second conductive piece, and the insertion part is arranged in the insertion groove and is abutted with the groove wall of the insertion groove. So set up, the portion of inserting of first electrically conductive piece is arranged in the portion of inserting of second electrically conductive piece, the size of inserting the second electrically conductive piece of groove department is greater than the size of inserting the first electrically conductive piece of portion department this moment, the size of inserting the second electrically conductive piece of groove department is great, can reduce the photoetching alignment degree of difficulty of first electrically conductive piece and second electrically conductive piece, reduce the photoetching alignment error between first electrically conductive piece and the second electrically conductive piece, be favorable to increasing the area of contact between first electrically conductive piece and the second electrically conductive piece, reduce the contact resistance between first electrically conductive piece and the second electrically conductive piece, realize effective electric connection between first electrically conductive piece and the second electrically conductive piece. In addition, as the inserting part is positioned in the inserting groove, the end face of the inserting part facing the second surface and the side wall of the inserting part can be contacted with the groove wall of the inserting groove, so that the contact area between the first conductive piece and the second conductive piece is larger, and the contact resistance between the first conductive piece and the second conductive piece can be further reduced. In the embodiment of the invention, the second conductive element is positioned in the second groove of the substrate, the groove bottom of the second groove is spaced from the first surface, namely the second conductive element is positioned in the substrate, the second conductive element is spaced from the first surface, and the second conductive element does not extend into the dielectric layer, so that the second conductive element does not occupy the area of the active area, and the area of the substrate for arranging the active area is not reduced, thereby avoiding adverse effects on the device integration density caused by the extension of the second conductive element into the dielectric layer.
In one possible embodiment, the first insulating layer also extends between the side wall of the first conductive member and the second insulating layer of the bottom wall of the second trench.
In one possible embodiment, at least one of the first insulating layer and the second insulating layer further extends between the insertion portion and a wall of the insertion groove.
In one possible embodiment, at least a portion of the second insulating layer near the bottom of the second trench has a first thickness, and the second insulating layer near the notch of the second trench has a second thickness, the first thickness being greater than the second thickness;
and/or at least one of the first conductive member and the second conductive member comprises a conductive body and a barrier layer, the barrier layer being located between the conductive body and the substrate;
and/or the interconnection structure further comprises a dielectric layer and a plurality of active regions, wherein the dielectric layer is positioned on the first surface, the dielectric layer is positioned between two adjacent active regions, and the first groove extends from the substrate into the dielectric layer.
A second aspect of an embodiment of the present application provides a method for manufacturing an interconnect structure, including: providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite in the thickness direction and are arranged at intervals; forming a first trench on one side of a first surface of a substrate; forming a first insulating layer, wherein the first insulating layer covers the wall of the first groove; forming a first conductive piece which is positioned on the first insulating layer and fills the first groove, wherein an inserting part is formed at one end of the first conductive piece facing the second surface; forming a second groove on one side of the second surface of the substrate, wherein the groove bottom of the second groove is arranged at intervals with the first surface, the second groove exposes the groove bottom wall of the first groove and the first insulating layer on part of the groove side wall of the first groove, and one end of the first groove, which is close to the second surface, is positioned in the second groove and is communicated with the second groove; forming a second insulating layer, wherein the second insulating layer covers the wall of the second groove; removing at least a portion of the first insulating layer exposed in the second trench to expose the first conductive member to the second trench, the remaining first insulating layer being located between the first conductive member and a wall of the first trench; and forming a second conductive piece, wherein the second conductive piece is positioned on the second insulating layer and fills the second groove, an inserting groove is formed at one end of the second conductive piece facing the first surface, and the inserting part is positioned in the inserting groove and is abutted with the groove wall of the inserting groove.
The preparation method of the interconnection structure can be used for preparing the interconnection structure, an inserting portion is arranged at one end, facing the second surface, of the first conductive piece, an inserting groove is formed at one end, facing the first surface, of the second conductive piece, and the inserting portion is arranged in the inserting groove and is in butt joint with the groove wall of the inserting groove. So set up, the portion of inserting of first electrically conductive piece is arranged in the portion of inserting of second electrically conductive piece, the size of inserting the second electrically conductive piece of groove department is greater than the size of inserting the first electrically conductive piece of portion department this moment, the size of inserting the second electrically conductive piece of groove department is great, can reduce the photoetching alignment degree of difficulty of first electrically conductive piece and second electrically conductive piece, reduce the photoetching alignment error between first electrically conductive piece and the second electrically conductive piece, be favorable to increasing the area of contact between first electrically conductive piece and the second electrically conductive piece, reduce the contact resistance between first electrically conductive piece and the second electrically conductive piece, realize effective electric connection between first electrically conductive piece and the second electrically conductive piece. In addition, as the inserting part is positioned in the inserting groove, the end face of the inserting part facing the second surface and the side wall of the inserting part can be contacted with the groove wall of the inserting groove, so that the contact area between the first conductive piece and the second conductive piece is larger, and the contact resistance between the first conductive piece and the second conductive piece can be further reduced. In the embodiment of the invention, the second conductive element is positioned in the second groove of the substrate, the groove bottom of the second groove is spaced from the first surface, namely the second conductive element is positioned in the substrate, the second conductive element is spaced from the first surface, and the second conductive element does not extend into the dielectric layer, so that the second conductive element does not occupy the area of the active area, and the area of the substrate for arranging the active area is not reduced, thereby avoiding adverse effects on the device integration density caused by the extension of the second conductive element into the dielectric layer.
In one possible embodiment, the material of the substrate comprises silicon, the material of the second insulating layer comprises silicon oxide, and the etching selectivity ratio of the first insulating layer to the substrate is greater than or equal to 5:1; forming the second insulating layer and exposing the first conductive member includes: firstly, exposing the first conductive piece; and oxidizing the substrate at the wall of the second trench to form a second insulating layer.
In one possible embodiment, forming the second insulating layer and exposing the first conductive member includes: a second insulation is formed first, and then the first conductive member is exposed.
In one possible embodiment, the material of the substrate comprises silicon, the material of the second insulating layer comprises silicon oxide, and the etching selectivity ratio of the first insulating layer to the second insulating layer is greater than or equal to 5:1; forming the second insulating layer includes: the substrate at the wall of the second trench is oxidized to form a second insulating layer.
In one possible embodiment, forming the second insulating layer further includes: forming a second insulating layer on the first insulating layer exposed in the second trench; forming a first sacrificial layer which is positioned on the second insulating layer and fills the second groove; forming a third groove, wherein the third groove is positioned in the first sacrificial layer in the second groove, the bottom of the third groove exposes the second insulating layer, the reserved first sacrificial layer covers the second insulating layer on the wall of the second groove, and a first mask layer is formed; exposing the first conductive element includes: taking the first mask layer as a mask, and removing part of the first insulating layer and part of the second insulating layer; and removing the first mask layer.
In one possible embodiment, forming the second insulating layer further includes: the second insulating layer fills the second groove with partial depth and forms a filling part, and the filling part covers the end face of the first conductive piece facing the second surface; forming a second sacrificial layer, wherein the second sacrificial layer fills a second groove with the other part of depth; forming a fourth groove, wherein the fourth groove is positioned in the second sacrificial layer in the second groove, the bottom of the fourth groove exposes the filling part, and the reserved second sacrificial layer forms a second mask layer; exposing the first conductive element includes: removing part of the first insulating layer and part of the filling part by taking the second mask layer as a mask, wherein the thickness of at least part of the reserved filling part is larger than that of the rest part of the second insulating layer; and removing the second mask layer.
In one possible embodiment, forming the second insulating layer includes: forming an insulating material layer, wherein the insulating material layer covers the wall of the second groove and is exposed on the first insulating layer in the second groove, and the insulating material layer forms a second insulating layer; a fifth groove is formed between the side wall of the first insulating layer in the second groove and the groove side wall of the second groove, and the thickness of the insulating material layer is twice larger than the width of the notch of the fifth groove, so that the insulating material layer fills the fifth groove and a filling part is formed;
Alternatively, the second insulating layer includes a first insulating material layer and a second insulating material layer; forming the second insulating layer includes: forming a first insulating material layer, wherein the first insulating material layer covers the wall of the second groove and is exposed on the first insulating layer in the second groove; and forming a second insulating material layer, wherein the second insulating material layer fills a second groove with partial depth, and the first insulating material layer and the second insulating material layer close to the bottom of the second groove jointly form a filling part.
In one possible embodiment, the remaining first insulating layer also extends between the side wall of the first conductive member and the second insulating layer of the bottom wall of the second trench; alternatively, the remaining first insulating layer also extends between the insertion portion and the wall of the insertion groove.
In one possible embodiment, the remaining second insulating layer also extends between the insertion part and the wall of the insertion groove.
The construction of the present application, as well as other objects and advantages thereof, will be more readily understood from the description of the preferred embodiments taken in conjunction with the accompanying drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an interconnection structure provided in an embodiment of the present application;
FIG. 2 is another schematic illustration of an interconnect structure provided in an embodiment of the present application;
FIG. 3 is another schematic diagram of an interconnect structure provided in an embodiment of the present application;
fig. 4 is a schematic flow chart of a method for manufacturing an interconnection structure according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a substrate provided in an embodiment of the present application;
fig. 6 is a schematic structural diagram of forming a first sub-dielectric layer and a fin structure according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of the first trench after formation according to the embodiment of the present application;
fig. 8 is a schematic structural diagram of the first insulating layer and the first conductive member after forming in the embodiment of the present application;
fig. 9 is a schematic structural diagram of the etched back portion of the first conductive member according to the embodiment of the present application;
fig. 10 is a schematic structural diagram of a second sub-dielectric layer after formation according to an embodiment of the present application;
fig. 11 is a schematic structural diagram of an epitaxial layer and a portion of a third sub-dielectric layer after formation according to an embodiment of the present application;
fig. 12 is a schematic structural diagram of a first interconnect, a second interconnect, and another portion of a third sub-dielectric layer according to an embodiment of the present disclosure;
Fig. 13 is a schematic structural view of a carrier formed according to an embodiment of the present disclosure;
fig. 14 is a schematic structural diagram of a passivation layer formed according to an embodiment of the present application;
fig. 15 is a schematic structural diagram of a second trench formed according to an embodiment of the present disclosure;
fig. 16 is a schematic structural diagram of a second insulating layer formed according to an embodiment of the present disclosure;
fig. 17 is a schematic structural diagram of a portion of a first insulating layer after removal according to an embodiment of the present disclosure;
fig. 18 is a schematic structural diagram of the second insulating layer formed and a portion of the first insulating layer removed according to the embodiment of the present application;
fig. 19 is a schematic structural diagram of the second conductive element after forming according to the embodiment of the present application;
fig. 20 is a schematic diagram of another structure after forming a second insulating layer according to an embodiment of the present disclosure;
FIG. 21 is a schematic diagram of a structure after forming a first sacrificial layer according to an embodiment of the present disclosure;
fig. 22 is a schematic structural diagram of a third trench formed according to an embodiment of the present disclosure;
fig. 23 is a schematic structural diagram of the embodiment of the present application after removing a portion of the first insulating layer and a portion of the second insulating layer;
fig. 24 is a schematic structural diagram of the first mask layer removed according to the embodiment of the present application;
Fig. 25 is a schematic view of another structure after forming a second conductive element according to an embodiment of the present disclosure;
fig. 26 is a schematic structural diagram of the filling portion after forming according to the embodiment of the present application;
fig. 27 is a schematic structural view of a first insulating material layer according to an embodiment of the present disclosure;
fig. 28 is a schematic structural view of a second insulating material layer according to an embodiment of the present disclosure;
fig. 29 is a schematic structural diagram of a second mask layer after formation according to an embodiment of the present application;
fig. 30 is a schematic diagram of another structure after removing a portion of the first insulating layer and a portion of the second insulating layer according to an embodiment of the present disclosure;
fig. 31 is a schematic structural diagram of the embodiment of the present application after removing the second mask layer;
fig. 32 is a schematic diagram of another structure after forming the second conductive element according to the embodiment of the present application.
Reference numerals illustrate:
100: an interconnect structure; 101: a substrate; 101a: a first surface;
101b: a second surface; 110: a first conductive member; 111: an insertion portion;
120: a second conductive member; 121: inserting grooves; 1311: a first barrier layer;
1312: a second barrier layer; 1313: a third barrier layer; 1321: a first conductive body;
1322: a second conductive body; 1323: a third conductive body; 141: a first insulating layer;
1411: a first extension; 1412: a second extension; 1413: a third extension;
142: a second insulating layer; 142a: an insulating material layer; 142b: a first layer of insulating material;
142c: a second layer of insulating material; 1421: a filling part; 1424: a fourth extension;
1425: a fifth extension; 1426: a sixth extension; 151: a first trench;
152: a second trench; 153: a third trench; 154: a fourth trench;
155: a fifth groove; 161: a first dielectric layer; 1611: a first sub-dielectric layer;
1612: a second sub-dielectric layer; 1613: a third sub-dielectric layer; 162: a second dielectric layer;
1711: a first sacrificial layer; 1721: a first mask layer; 1722: a second mask layer;
181: a first interconnect; 182: a second interconnect; 183: a third interconnect;
191: a protective layer; 192: an active region; 1921: a fin structure;
1922: an epitaxial layer; 193: a carrier; 194: an auxiliary substrate;
195: a stop layer; 196: and a passivation layer.
Detailed Description
In the related art, in the wafer back power supply technology, the wafer may include a silicon substrate, the through silicon via may include a first connection end near the pre-buried power supply rail, the pre-buried power supply rail may include a second connection end near the through silicon via, both the first connection end and the second connection end may be located in the silicon substrate, and the through silicon via and the pre-buried power supply rail may be electrically connected through the first connection end and the second connection end. The dimensions of the through silicon vias and the embedded power rails are both nano-scale. The dimensions (e.g., widths) of the first and second connection ends may be the same.
However, when the wafer is in a heating process (e.g., thermocompression bonding), the wafer is prone to warpage, which can easily result in a large positional shift (e.g., a positional shift of not less than 10 nm) of the embedded power supply rail. If the first connecting end and the second connecting end are the same in size, the photoetching alignment difficulty between the through silicon via and the embedded power rail is increased, and the photoetching alignment error between the through silicon via and the embedded power rail is increased, so that the contact area between the through silicon via and the embedded power rail is small, the contact resistance between the through silicon via and the embedded power rail is large, and even the power supply network is possibly invalid.
In some examples, the front surface of the silicon substrate may be provided with a plurality of active regions at intervals, and a dielectric layer is provided between each two adjacent active regions, and the dielectric layer may be used to isolate the two adjacent active regions. The silicon through hole can penetrate through the silicon substrate, extend into the dielectric layer and wrap the outer side of the second connecting end, namely the first connecting end extends into the dielectric layer, so that the first connecting end can be prevented from being contacted with the silicon substrate to be conducted. In addition, because the first connecting end wraps up in the outside of second connecting end, the size of first connecting end is greater than the size of second connecting end this moment, and the size of first connecting end is great, can reduce the photoetching alignment degree of difficulty between through silicon hole and the pre-buried power rail, reduces the photoetching alignment error between through silicon hole and the pre-buried power rail, is favorable to increasing the area of contact between through silicon hole and the pre-buried power rail, reduces contact resistance between through silicon hole and the pre-buried power rail, realizes effective electric connection between through silicon hole and the pre-buried power rail. However, since the first connection end of the through silicon via has a larger size and extends into the dielectric layer, the through silicon via may occupy the area of the active region on the front surface of the silicon substrate, so that the area of the silicon substrate for disposing the active region is reduced, resulting in a reduction in the number of active regions, thereby reducing the integration density of devices.
Based on at least one technical problem described above, an embodiment of the present application provides an interconnection structure and a method for manufacturing the interconnection structure, where the interconnection structure includes a substrate, a first conductive member, a second conductive member, a first insulating layer and a second insulating layer, the substrate includes a first surface and a second surface that are opposite and spaced apart along a thickness direction, a first trench is formed on one side of the first surface of the substrate, a second trench is formed on one side of the second surface of the substrate, a bottom of the second trench is spaced apart from the first surface, and one end of the first trench, which is close to the second surface, is located in the second trench and is communicated with the second trench. The first conductive piece is located in the first groove, the second conductive piece is located in the second groove, the first insulating layer is located between the first conductive piece and the groove wall of the first groove, and the second insulating layer is located between the second conductive piece and the groove wall of the second groove. The first conductive piece is provided with the portion of inserting towards the one end of second surface, and the second conductive piece is provided with the groove of inserting towards the one end of first surface, and the portion of inserting is located in the groove of inserting, and with the cell wall butt in the groove of inserting. So set up, the portion of inserting of first electrically conductive piece is arranged in the portion of inserting of second electrically conductive piece, the size of inserting the second electrically conductive piece of groove department is greater than the size of inserting the first electrically conductive piece of portion department this moment, the size of inserting the second electrically conductive piece of groove department is great, can reduce the photoetching alignment degree of difficulty of first electrically conductive piece and second electrically conductive piece, reduce the photoetching alignment error between first electrically conductive piece and the second electrically conductive piece, be favorable to increasing the area of contact between first electrically conductive piece and the second electrically conductive piece, reduce the contact resistance between first electrically conductive piece and the second electrically conductive piece, realize effective electric connection between first electrically conductive piece and the second electrically conductive piece. In addition, as the inserting part is positioned in the inserting groove, the end face of the inserting part facing the second surface and the side wall of the inserting part can be contacted with the groove wall of the inserting groove, so that the contact area between the first conductive piece and the second conductive piece is larger, and the contact resistance between the first conductive piece and the second conductive piece can be further reduced. In the embodiment of the invention, the second conductive element is positioned in the second groove of the substrate, the groove bottom of the second groove is spaced from the first surface, namely the second conductive element is positioned in the substrate, the second conductive element is spaced from the first surface, and the second conductive element does not extend into the dielectric layer, so that the second conductive element does not occupy the area of the active area, and the area of the substrate for arranging the active area is not reduced, thereby avoiding the adverse effect on the device integration density caused by the extension of the second conductive element into the dielectric layer.
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The interconnect structure 100 provided in the embodiments of the present application will be described below with reference to fig. 1-32.
The present embodiment provides an interconnect structure 100, and the interconnect structure 100 may be applied to chips, such as memory chips, logic chips, and chiplets (Chaplet), and the chips may be advanced process chips of 3nm and below.
Referring to fig. 1, an interconnect structure 100 may include a substrate 101, and the substrate 101 may provide a support foundation for other structural layers on the substrate 101. The substrate 101 may include a first surface 101a and a second surface 101b that are opposite and spaced apart in a thickness direction (Z direction).
By way of example, the material of the substrate 101 may include, but is not limited to, any one or more of monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium compounds, gallium arsenic compounds, gallium phosphorous compounds, gallium sulfur compounds, and the like. The substrate 101 may be a Bulk Silicon (Bulk Silicon) substrate or a Silicon-on-insulator (Silicon On Insulator, SOI) substrate.
For example, referring to fig. 1, 7 and 15, one side of the first surface 101a of the substrate 101 may have a first groove 151 and one side of the second surface 101b of the substrate 101 may have a second groove 152. Both the walls of the first trench 151 and the walls of the second trench 152 may be formed of the substrate 101. One end of the first groove 151 near the second surface 101b may be located in the second groove 152, and one end of the first groove 151 near the second surface 101b may communicate with the second groove 152. For example, the substrate 101 at an end of the first trench 151 near the second surface 101b may be removed, which corresponds to a trench wall at an end of the first trench 151 near the second surface 101b being removed, thereby achieving communication with the second trench 152.
Illustratively, the shape of the cross section of any one of the first groove 151 and the second groove 152 along the cross section parallel to the substrate 101 may include a circle, an ellipse, a bar, or the like.
For example, referring to fig. 1, the interconnect structure 100 may include a first conductive member 110 and a second conductive member 120, the first conductive member 110 may be positioned in a first trench 151, and the second conductive member 120 may be positioned in a second trench 152. An end of the first conductive member 110 facing the second surface 101b may be provided with an insertion portion 111, an end of the second conductive member 120 facing the first surface 101a may be provided with an insertion groove 121, the insertion portion 111 may be located in the insertion groove 121, and the insertion portion 111 abuts against a groove wall of the insertion groove 121, thereby achieving electrical connection of the first conductive member 110 and the second conductive member 120. Wherein at least one of an end surface of the insertion portion 111 facing the second surface 101b and a side wall of the insertion portion 111 may be in contact with a groove wall of the insertion groove 121. The embodiment of the present application will be described taking an example in which both the end surface of the insertion portion 111 facing the second surface 101b and the side wall of the insertion portion 111 are in contact with the groove wall of the insertion groove 121.
So configured, the insertion portion 111 of the first conductive element 110 is located in the insertion groove 121 of the second conductive element 120, at this time, the size of the second conductive element 120 at the insertion groove 121 is larger than the size of the first conductive element 110 at the insertion portion 111, and the size of the second conductive element 120 at the insertion groove 121 is larger (for example, the size may be the width along the first direction X in fig. 1), which can reduce the difficulty of photo-etching alignment between the first conductive element 110 and the second conductive element 120, reduce the photo-etching alignment error between the first conductive element 110 and the second conductive element 120, and advantageously increase the contact area between the first conductive element 110 and the second conductive element 120, reduce the contact resistance between the first conductive element 110 and the second conductive element 120, and realize effective electrical connection between the first conductive element 110 and the second conductive element 120. In addition, since the insertion portion 111 is located in the insertion groove 121, both the end surface of the insertion portion 111 facing the second surface 101b and the side wall of the insertion portion 111 can be in contact with the groove wall of the insertion groove 121, so that the contact area between the first conductive member 110 and the second conductive member 120 is large, and the contact resistance between the first conductive member 110 and the second conductive member 120 can be further reduced. In the embodiment where the plurality of active regions 192 are disposed on one side of the first surface 101a of the substrate 101 and the dielectric layer (i.e., the first dielectric layer 161) is disposed between two adjacent active regions 192, since the second conductive element 120 is disposed in the second trench 152 of the substrate 101, the bottom of the second trench 152 is spaced from the first surface 101a, i.e., the second conductive element 120 is disposed in the substrate 101, the second conductive element 120 is spaced from the first surface 101a, and the second conductive element 120 does not extend into the first dielectric layer 161, so that the second conductive element 120 does not occupy the area of the active region 192, and the area of the substrate 101 for disposing the active region 192 is not reduced, thereby avoiding adverse effects caused by the integration density of devices due to the second conductive element 120 extending into the first dielectric layer 161.
For example, referring to fig. 1, the number of the first conductive members 110 and the second conductive members 120 may be plural, and at least a portion of the first conductive members 110 and at least a portion of the second conductive members 120 may be disposed at intervals along the first direction X. The first direction X may be parallel to the substrate 101. The second conductive member 120 may have a size greater than that of the first conductive member 110 along the first direction X.
For example, referring to fig. 1, the interconnect structure 100 may include a first insulating layer 141 and a second insulating layer 142. The first insulating layer 141 may be at least between the first conductive member 110 and a wall of the first trench 151, and the first insulating layer 141 may be used to electrically isolate the first conductive member 110 from the substrate 101. In the substrate 101, since the groove wall at the end of the first groove 151 near the second surface 101b is removed, at this time, the groove wall of the first groove 151 may be located at the end of the first groove 151 remote from the second surface 101b, and the first insulating layer 141 may be located between the substrate 101 and the first conductive member 110 at the end of the first groove 151 remote from the second surface 101 b. In addition, the second insulating layer 142 may be at least between the second conductive member 120 and the wall of the second trench 152. The second insulating layer 142 may be used to electrically isolate the second conductive member 120 from the substrate 101. Since the groove bottom wall of the second groove 152 is perforated by the first groove 151 to form a notch, the second insulating layer 142 may be located on the groove side wall of the second groove 152 and the groove bottom wall of the second groove 152 except for the notch.
The first insulating layer 141 provided in the embodiment of the present application is described below.
Referring to fig. 1 to 3, the first insulating layer 141 may include a first extension 1411, the first extension 1411 may be located outside the second trench 152, and the first extension 1411 may be located between the first conductive member 110 and a wall of the first trench 151 to electrically isolate the first conductive member 110 from the substrate 101.
1-3, the first insulating layer 141 may include a second extension 1412, the second extension 1412 may be located within the second trench 152, and the second extension 1412 may be connected to the first extension 1411. The second extension 1412 may be located between the sidewall of the first conductive member 110 and the second insulating layer 142 of the bottom wall of the second trench 152. Equivalently, the first insulating layer 141 may extend between the sidewall of the first conductive member 110 and the second insulating layer 142 of the bottom wall of the second trench 152. Thus, the second extension 1412 can increase the area of the first insulating layer 141, so as to improve the isolation effect of the first insulating layer 141 on the first conductive element 110 and the substrate 101, and avoid the first insulating layer 141 from being over etched to expose the wall of the first trench 151 due to process errors (e.g., over etching), thereby effectively avoiding the contact between the first conductive element 110 and the wall of the first trench 151.
For example, referring to fig. 1 and 2, the first insulating layer 141 may include a third extension 1413, the third extension 1413 may be located at a side of the second extension 1412 facing away from the first extension 1411, and the third extension 1413 may be connected to the second extension 1412. The third extension 1413 may be located between the insertion portion 111 and a wall of the insertion groove 121. The first insulating layer 141 may extend between the insertion portion 111 and the wall of the insertion groove 121. In this way, the third extension portion 1413 can further increase the area of the first insulating layer 141 to further improve the isolation effect of the first insulating layer 141 on the first conductive element 110 and the substrate 101, and the principle is similar to that of the second extension portion 1412, which is not described herein.
In the substrate 101, the first insulating layer 141 may include a first extension 1411, or a first extension 1411 and a second extension 1412, or a first extension 1411, a second extension 1412, and a third extension 1413.
The second insulating layer 142 provided in the embodiment of the present application is described below.
Referring to fig. 1-3, the second insulating layer 142 may include a fourth extension 1424 and a fifth extension 1425 connected, and the fourth extension 1424 and the fifth extension 1425 may be located outside the insertion groove 121. The fourth extension 1424 may be located on a sidewall of the second trench 152, and the fifth extension 1425 may be located on a bottom wall of the second trench 152, so as to electrically isolate the second conductive element 120 from the substrate 101.
For example, referring to fig. 2, the second insulating layer 142 may include a sixth extension 1426, the sixth extension 1426 may be located at a side of the fifth extension 1425 facing away from the fourth extension 1424, and the sixth extension 1426 may be connected to the fifth extension 1425. The sixth extension 1426 may be located between the insertion portion 111 and the groove wall of the insertion groove 121. Equivalently, the second insulating layer 142 may extend between the insertion portion 111 and the groove wall of the insertion groove 121. In this way, the sixth extension portion 1426 can increase the area of the second insulating layer 142, so as to improve the isolation effect of the second insulating layer 142 on the second conductive element 120 and the substrate 101, and the principle is similar to that of the second extension portion 1412, which is not described herein.
For example, at least a portion of the second insulating layer 142 near the bottom of the second trench 152 may have a first thickness, and the second insulating layer 142 near the notch of the second trench 152 may have a second thickness, and the first thickness may be greater than the second thickness. For example, referring to fig. 3, the fourth extension 1424 near the bottom end of the second groove 152 and the fifth extension 1425 may have a first thickness, and the notch end of the fourth extension 1424 near the second groove 152 may have a second thickness, and the first thickness may be greater than the second thickness. Thus, since the first thickness is set larger, the isolation effect of the second insulating layer 142 at the first thickness on the second conductive member 120 and the substrate 101 can be improved.
In the substrate 101, the second insulating layer 142 may include a fourth extension portion 1424 and a fifth extension portion 1425, or a fourth extension portion 1424, a fifth extension portion 1425, and a sixth extension portion 1426. At least one of the first insulating layer 141 and the second insulating layer 142 may extend between the insertion portion 111 and the groove wall of the insertion groove 121.
The first conductive member 110 and the second conductive member 120 provided in the embodiment of the present application are described below.
For example, at least one of the first conductive member 110 and the second conductive member 120 may include a conductive body and a barrier layer, which may be located between the conductive body and the substrate 101. The barrier layer may be used to block diffusion of elements (e.g., metallic elements) in the conductive body into the substrate 101. For example, the barrier layer may be a metal nitride such as TiN. Referring to fig. 1, in an embodiment in which the first conductive member 110 includes a conductive body and a barrier layer, the conductive body and the barrier layer of the first conductive member 110 may be a first conductive body 1321 and a first barrier layer 1311, respectively, and the first barrier layer 1311 may be located on an end surface of the first conductive body 1321 facing the second surface 101b and a sidewall of the first conductive body 1321. In embodiments where the second conductive member 120 includes a conductive body and a barrier layer, the conductive body and the barrier layer of the second conductive member 120 may be the second conductive body 1322 and the second barrier layer 1312, respectively, and the second barrier layer 1312 may be located on an end surface of the second conductive body 1322 facing the first surface 101a and a sidewall of the second conductive body 1322. In other examples, at least one of the first conductive member 110 and the second conductive member 120 may include only the conductive body.
For example, the first conductive element 110 may be a pre-buried power rail or other interconnect rail. The embodiment of the present application is described taking the first conductive element 110 as an embedded power rail as an example. The second conductive element 120 may be a through silicon via or other interconnect structure. By arranging the embedded power rail and the through silicon via which are electrically connected, the power supply on the back of the wafer can be realized, the IR voltage drop of a power supply network can be reduced, and the power transmission performance of the power supply network can be improved. The electrically connected embedded power supply rail and the through silicon via can be applied to a vertical interconnection scene in a 3D integrated circuit architecture, for example, a nanoscale small-size interconnection scene and a microscale TSV interconnection scene in the advanced packaging field.
The following describes a structural layer on the first surface 101a side of the substrate 101 provided in the embodiment of the present application.
The device chip may be formed through a process flow on the first surface 101a side of the substrate 101.
Referring to fig. 1, 7, and 15, the interconnect structure 100 may include a first dielectric layer 161, the first dielectric layer 161 may be located on the first surface 101a, and the first trench 151 may extend from the substrate 101 into the first dielectric layer 161. At least one of the first conductive member 110 and the first extension 1411 may extend from the substrate 101 into the first dielectric layer 161. In the first dielectric layer 161, the first extension 1411 may be located at a wall of the first trench 151, and the first conductive member 110 may be located at a side of the first extension 1411 facing away from the substrate 101 and fill at least part of the first trench 151.
Illustratively, referring to fig. 12, the first dielectric layer 161 may include a plurality of sub-dielectric layers in a thickness direction of the substrate 101, and the plurality of sub-dielectric layers may include a first sub-dielectric layer 1611, a second sub-dielectric layer 1612, a third sub-dielectric layer 1613, and the like. At least a part of the number of sub-dielectric layers may be stacked in the thickness direction of the substrate 101. The materials of any two sub-dielectric layers may be the same or may be different. The material of any one of the sub-dielectric layers may be an oxide (e.g., silicon oxide). Any one of the sub-dielectric layers can be of a single-layer structure or a multi-layer stacked structure.
By way of example, the interconnect structure 100 may include transistors, which may include Fin Field-Effect Transistor (FinFET), full-Around Gate FET (GAA), fork-slice transistor (fork-see), complementary Field-effect transistor (Complementary FET, CFET), and the like. The embodiments of the present application will be described by taking a transistor as a fin field effect transistor as an example.
For example, referring to fig. 1, a plurality of fin structures 1921 may be disposed on a first surface 101a of a substrate 101 at intervals, and the fin structures 1921 may be used to form an active region 192. Since the second conductive member 120 is located in the second trench 152 of the substrate 101, that is, the second conductive member 120 is located in the substrate 101, the second conductive member 120 is spaced from the first surface 101a, and the second conductive member 120 does not extend into the first dielectric layer 161, so that the area of the active region 192 is not occupied by the second conductive member 120, and the area of the substrate 101 for setting the active region 192 is not reduced, thereby avoiding adverse effects on the device integration density caused by the extension of the second conductive member 120 into the first dielectric layer 161.
For example, referring to fig. 1, the interconnect structure 100 may include a first interconnect 181 and a second interconnect 182. The fin structures 1921 may be electrically connected to the first conductive elements 110 through the first interconnect 181. The side of the fin structure 1921 facing away from the substrate 101 may be provided with an epitaxial layer 1922, and the size of the epitaxial layer 1922 may be larger than the size of the fin structure 1921, and the fin structure 1921 may be electrically connected to the first interconnect 181 through the epitaxial layer 1922, so that a connection area between the first interconnect 181 and the active region 192 may be increased, contact resistance between the first interconnect 181 and the active region 192 may be reduced, and connection stability between the first interconnect 181 and the active region 192 may be improved. Wherein the epitaxial layer 1922 and the fin structure 1921 may together form the active region 192. The second interconnection 182 may be electrically connected with the first conductive element 110 through the first interconnection 181. The second interconnect 182 may be electrically connected to an external circuit, for example, an external signal line. Wherein fin structure 1921, epitaxial layer 1922, first interconnect 181, and second interconnect 182 may all be located in first dielectric layer 161.
For example, referring to fig. 1, a side of the first dielectric layer 161 facing away from the substrate 101 may be provided with a carrier 193. The carrier 193 may be used to protect the interconnect structure 100 when preparing a structural layer on the second surface 101b side of the substrate 101. For example, carrier 193 may be a bonding pad, which may include, but is not limited to, a blank pad and any integrated circuit carrier having other functions. The interconnect structure 100 may be bonded to a bonding pad that may be removed or may remain in a later process.
The following describes a structural layer on the second surface 101b side of the substrate 101 provided in the embodiment of the present application.
For example, referring to fig. 1, the second surface 101b may be provided with a passivation layer 196, the second trench 152 may extend into the passivation layer 196, and the passivation layer 196 may be used to form protection for the substrate 101 during formation of the second trench 152. The second insulating layer 142 may cover the walls of the second trenches 152 in the substrate 101, or the second insulating layer 142 may extend from within the second trenches 152 in the substrate 101 into the second trenches 152 in the passivation layer 196. For example, the second conductive member 120 extends from the second trench 152 in the substrate 101 into the second trench 152 in the passivation layer 196, and the second conductive member 120 may fill the second trench 152. The material of the passivation layer 196 may include an oxide (e.g., silicon oxide).
For example, referring to fig. 1, a side of the second conductive member 120 and the passivation layer 196 facing away from the substrate 101 may be provided with a second dielectric layer 162, a third interconnection 183 may be provided in the second dielectric layer 162, and the third interconnection 183 may be electrically connected to the second conductive member 120. The third interconnection 183 may be electrically connected to an external circuit, for example, may be electrically connected to an external power line. For example, third interconnect 183 may include a conductive body (i.e., third conductive body 1323) and a barrier layer (i.e., third barrier layer 1313), and third barrier layer 1313 may be located on an end surface and sidewalls of third conductive body 1323 facing first surface 101 a. In other examples, third interconnect 183 may include only conductive bodies.
The following describes a method for manufacturing the interconnect structure 100 according to the embodiment of the present application.
The method for manufacturing the interconnect structure 100 provided in the embodiment of the present application may be used to manufacture the interconnect structure 100 in the above embodiment. Referring to fig. 4, the method of fabricating the interconnect structure 100 may include:
s100: a substrate is provided, the substrate including a first surface and a second surface opposite and spaced apart in a thickness direction.
Referring to fig. 5, a substrate 101 is provided, the substrate 101 may provide a support foundation for other structural layers on the substrate 101. The substrate 101 may include a first surface 101a and a second surface 101b that are opposite and spaced apart in the thickness direction.
For example, referring to fig. 5, a protective layer 191 may be formed on the first surface 101a of the substrate 101, and the protective layer 191 may serve to protect the substrate 101. The material of the protective layer 191 may be oxide (e.g., silicon oxide). A stop layer 195 and an auxiliary substrate 194 may be formed on the second surface 101b of the substrate 101, the stop layer 195 being located between the second surface 101b and the auxiliary substrate 194. The material of the auxiliary substrate 194 may be the same as that of the substrate 101, or may be different. The auxiliary substrate 194 may be used to protect the substrate 101, and the stop layer 195 may be used to stop the removal process when the auxiliary substrate 194 is subsequently removed.
Wherein the auxiliary substrate 194 may be removed by chemical mechanical polishing (chemical mechanical polishing, abbreviated as CMP) or an etching process. The other removed structural layers in the embodiments of the present application are similar to those described above, and will not be described again.
Referring to fig. 6, after providing the substrate 101, it may include forming a fin structure 1921 and a first sub-dielectric layer 1611 on the first surface 101a, the fin structure 1921 may be used to form the active region 192. The first sub-dielectric layer 1611 may be located between two adjacent fin structures 1921 and may cover a side of the fin structures 1921 facing away from the substrate 101. The first sub-dielectric layer 1611 may be used to form an isolation structure (e.g., shallow trench isolation structure) to isolate adjacent two active regions 192. Prior to forming first sub-dielectric layer 1611 and fin structure 1921, may include removing protective layer 191.
Illustratively, the first sub-dielectric layer 1611 may be formed by deposition, spin-coating, or the like. Deposition may include atomic layer deposition (atomic layer deposition, ALD for short), physical vapor deposition (physical vapor deposition, PVD for short), chemical vapor deposition (chemical vapor deposition, CVD for short), or the like. Other structural layers in the embodiments of the present disclosure may also be formed by deposition, spin coating, and the like, which are not described in detail.
S200: a first trench is formed in one side of the first surface of the substrate.
Referring to fig. 7, after forming fin structure 1921 and first sub-dielectric layer 1611, forming first trench 151 may include forming first trench 151 extending through first sub-dielectric layer 1611 and into substrate 101 to a partial thickness, i.e., a bottom of first trench 151 is located in substrate 101.
S300: a first insulating layer is formed, and the first insulating layer covers the wall of the first trench.
Referring to fig. 8, after forming the first trench 151, it may include forming a first insulating layer 141 on a wall of the first trench 151 and a surface of the first sub-dielectric layer 1611 facing away from the substrate 101. For example, the first insulating layer 141 may be formed by conformal deposition, thereby making the preparation of the first insulating layer 141 simpler.
S400: and forming a first conductive piece which is positioned on the first insulating layer and fills the first groove, wherein an inserting part is formed at one end of the first conductive piece facing the second surface.
Referring to fig. 8, after forming the first insulating layer 141, it may include forming the first conductive member 110 on the first insulating layer 141, and the first conductive member 110 may fill the first trench 151. An end of the first conductive member 110 facing the second surface 101b may be formed with an insertion portion 111.
Referring to fig. 8, forming the first conductive member 110 may include forming a first barrier layer 1311, and the first barrier layer 1311 may be located on the first insulating layer 141. Then, a first conductive body 1321 is formed, the first conductive body 1321 may be located on the first blocking layer 1311, and the first conductive body 1321 may fill the first trench 151.
Referring to fig. 9, after forming the first conductive member 110, it may include, etching back to remove a portion of the first conductive member 110, leaving another portion of the first conductive member 110 located in the first trench 151. In embodiments where first conductive element 110 includes first barrier layer 1311 and first conductive body 1321, remaining first barrier layer 1311 may be located on a sidewall of remaining first conductive body 1321 and an end surface of first conductive body 1321 proximate second surface 101 b.
Referring to fig. 10, after removing a portion of the first conductive member 110, forming a second sub-dielectric layer 1612 may include forming the second sub-dielectric layer 1612 on the first conductive member 110 and the first insulating layer 141, and the second sub-dielectric layer 1612 may fill the first trench 151 exposed by the back etching. Then, a portion of the second sub-dielectric layer 1612 and a portion of the first insulating layer 141 are removed along a side of the first sub-dielectric layer 1611 facing away from the substrate 101 (i.e., a top surface of the first sub-dielectric layer 1611 in fig. 9). Both the remaining second sub-dielectric layer 1612 and the remaining first insulating layer 141 may be located in the first trench 151.
Referring to fig. 11, after removing a portion of second sub-dielectric layer 1612 and a portion of first insulating layer 141, it may include removing a portion of first sub-dielectric layer 1611, a portion of second sub-dielectric layer 1612, and a portion of first insulating layer 141 along a side of fin structure 1921 facing away from substrate 101 to expose fin structure 1921. Then, an epitaxial layer 1922 is formed on the fin structure 1921, so that the contact resistance between the first interconnection 181 and the active region 192 may be reduced, and the connection stability between the first interconnection 181 and the active region 192 may be improved, and the principle thereof is already described and will not be described again. Wherein the epitaxial layer 1922 and the fin structure 1921 may together form the active region 192.
Referring to fig. 11 and 12, after forming the epitaxial layer 1922, forming the third sub-dielectric layer 1613, the first interconnect 181, and the second interconnect 182 may include forming the third sub-dielectric layer 1613 on a side of the first sub-dielectric layer 1611 and the second sub-dielectric layer 1612 facing away from the substrate 101, and the first interconnect 181, the second interconnect 182, and the epitaxial layer 1922 are all located in the third sub-dielectric layer 1613. The third sub-dielectric layer 1613 may be a multi-layered stack structure. Wherein the first interconnect 181 may be used to electrically connect the epitaxial layer 1922 and the first conductive element 110, the first interconnect 181 may also be used to electrically connect the first conductive element 110 and the second interconnect 182. The first sub-dielectric layer 1611, the second sub-dielectric layer 1612, and the third sub-dielectric layer 1613 may collectively form the first dielectric layer 161.
Referring to fig. 13, after forming the third sub-dielectric layer 1613, the first interconnect 181, and the second interconnect 182, it may include forming a carrier 193, and the carrier 193 may be located on the third sub-dielectric layer 1613. The carrier 193 may be used to protect the interconnect structure 100. For example, after the carrier 193 is disposed on the third sub-dielectric layer 1613, the interconnect structure 100 is flipped 180 ° and then the process on the second surface 101b side of the substrate 101 is performed. Alternatively, the interconnect structure 100 may be flipped 180 ° before the carrier 193 is disposed on the side of the third sub-dielectric layer 1613 facing away from the substrate 101, and then the process flow is performed on the side of the second surface 101b of the substrate 101.
Referring to fig. 13 and 14, after forming the carrier 193, removing the auxiliary substrate 194 may be included, and the removing process of the auxiliary substrate 194 is stopped at the stop layer 195. Then, the stop layer 195 is removed. A passivation layer 196 is formed on the second surface 101b of the substrate 101, the passivation layer 196 may be used to protect the substrate 101.
S500: and forming a second groove on one side of the second surface of the substrate, wherein the groove bottom of the second groove is arranged at intervals with the first surface, the second groove exposes the groove bottom wall of the first groove and the first insulating layer on part of the groove side wall of the first groove, and one end of the first groove, which is close to the second surface, is positioned in the second groove and communicated with the second groove.
Referring to fig. 15, after forming the passivation layer 196, forming the second trench 152 may include, the second trench 152 penetrating the passivation layer 196 and extending into the substrate 101, and a bottom of the second trench 152 may be located in the substrate 101. The second trench 152 may expose the first insulating layer 141 on the trench bottom wall of the first trench 151 and a portion of the trench sidewall of the first trench 151. In forming the second trench 152, the substrate 101 at an end of the first trench 151 near the second surface 101b is removed, and an end of the first trench 151 near the second surface 101b may be located in the second trench 152 and communicate with the second trench 152. In the substrate 101, the substrate 101 at an end of the first trench 151 near the first surface 101a is left, and a groove wall of a part of the first trench 151 is formed. The bottom wall of the second groove 152 is penetrated by the first groove 151 to form a notch.
S600: forming a second insulating layer, wherein the second insulating layer covers the wall of the second groove; and removing at least part of the first insulating layer exposed in the second groove so that the first conductive member is exposed by the second groove, and the reserved first insulating layer is positioned between the first conductive member and the groove wall of the first groove.
Referring to fig. 16 to 18, 20 to 24, and 26 to 31, the second insulating layer 142 is formed on at least a portion of the wall of the second trench 152, and the second insulating layer 142 may be formed on the bottom wall and at least a portion of the sidewall of the second trench 152, and the second insulating layer 142 may be used to electrically isolate the substrate 101 from the second conductive member 120. At least a portion of the first insulating layer 141 exposed in the second trench 152 is removed so that the second trench 152 exposes the first conductive member 110 to facilitate the contact of the subsequently formed second conductive member 120 with the first conductive member 110 for electrical connection. The remaining first insulating layer 141 may be located between the first conductive member 110 and the wall of the first trench 151. In embodiments where first conductive element 110 includes first barrier layer 1311 and first conductive body 1321, first conductive element 110 is exposed, i.e., first barrier layer 1311 is exposed.
Illustratively, forming the second insulating layer 142 and exposing the first conductive member 110 may include forming the second insulating layer 142 and then exposing the first conductive member 110. Alternatively, the first conductive element 110 is exposed, and then the second insulating layer 142 is formed.
A first implementation of forming the second insulating layer 142 and then exposing the first conductive element 110 according to the embodiment of the present application is described below.
Referring to fig. 16 and 18, forming the second insulating layer 142 may include oxidizing the substrate 101 at a wall of the second trench 152 to form the second insulating layer 142. Then, at least a portion of the first insulating layer 141 exposed in the second trench 152 is removed so that the second trench 152 exposes the first conductive member 110. Wherein the remaining first insulating layer 141 may include the first extension 1411, or the remaining first insulating layer 141 may include the first extension 1411 and the second extension 1412, or, referring to fig. 19, the remaining first insulating layer 141 may include the first extension 1411, the second extension 1412, and the third extension 1413. The oxidized second insulating layer 142 may include a fourth extension 1424 and a fifth extension 1425, and the second insulating layer 142 does not cover the first insulating layer 141 exposed in the second trench 152.
Illustratively, the material of the substrate 101 may include silicon, and the material of the second insulating layer 142 may include silicon oxide, which is oxidized to silicon oxide by an oxidation process, so that the second insulating layer 142 may be selectively formed at the wall of the second trench 152 without changing the material property of the first insulating layer 141 exposed to the second trench 152. The materials of the first insulating layer 141 and the second insulating layer 142 are different, and the material of the first insulating layer 141 may include nitride (e.g., silicon nitride). In exposing the first conductive member 110, the first insulating layer 141 may have a high etching selectivity with respect to the second insulating layer 142, which is equivalent to that the first insulating layer 141 is etched at a faster rate than the second insulating layer 142, for example, when the first insulating layer 141 is etched, the second insulating layer 142 may not be etched, thereby realizing selective etching of the first insulating layer 141, reducing difficulty in exposing the first conductive member 110, and reducing damage to the second insulating layer 142. For example, the etching selectivity ratio of the first insulating layer 141 to the second insulating layer 142 may be greater than or equal to 5:1, thereby achieving selective etching of the first insulating layer 141. The etching selectivity of the first insulating layer 141 to the second insulating layer 142 may be 5:1, 6:1, 7:1, 9:1, 10:1, or any value greater than 5:1.
Wherein, the etching selectivity refers to the ratio of the etching rate of the etched material to the etching rate of another material. For example, a high etch selectivity may be achieved to etch only a material with a relatively fast etch rate, not another material with a relatively slow etch rate.
A second implementation of forming the second insulating layer 142 and then exposing the first conductive element 110 according to the embodiment of the present application is described below.
Referring to fig. 20, forming the second insulating layer 142 may include: a second insulating layer 142 is formed on the first insulating layer 141 exposed in the second trench 152 and on the wall of the second trench 152. For example, the second insulating layer 142 may be formed by conformal deposition, thereby making the preparation of the second insulating layer 142 simpler. The material of any one of the first insulating layer 141 and the second insulating layer 142 may include an oxide (e.g., silicon oxide) and a nitride (e.g., silicon nitride). The etching rates of the first insulating layer 141 and the second insulating layer 142 may be the same or different.
Referring to fig. 21, after forming the second insulating layer 142, forming the first sacrificial layer 1711 may include, the first sacrificial layer 1711 may be located on the second insulating layer 142 and the passivation layer 196, and the first sacrificial layer 1711 may fill the second trench 152. The material of the first sacrificial layer 1711 may include an organic material or a semiconductor material of Si, siGe, or the like. Referring to fig. 22, a portion of the first sacrificial layer 1711 is removed to form a third trench 153, the third trench 153 may be located in the first sacrificial layer 1711 in the second trench 152, the size of the third trench 153 may be smaller than that of the second trench 152, and a bottom of the third trench 153 may expose the second insulating layer 142, thereby achieving a half-filling effect of the first sacrificial layer 1711. The remaining first sacrificial layer 1711 may cover the second insulating layer 142 on the wall of the second trench 152, and the remaining first sacrificial layer 1711 may form the first mask layer 1721. In the subsequent etching process, the first mask layer 1721 can protect the second insulating layer 142 on the wall of the second trench 152, so as to prevent the second insulating layer 142 from being damaged, so as to ensure electrical isolation between the second conductive element 120 and the substrate 101. Referring to fig. 23, exposing the first conductive member 110 may include removing a portion of the first insulating layer 141 and a portion of the second insulating layer 142 on the first conductive member 110 located in the second trench 152 using the first mask layer 1721 as a mask to expose the first conductive member 110. After exposing the first conductive element 110, removing the first mask layer 1721 may be included.
Wherein the remaining first insulating layer 141 may include the first extension 1411, or the remaining first insulating layer 141 may include the first extension 1411 and the second extension 1412, or, referring to fig. 25, the remaining first insulating layer 141 may include the first extension 1411, the second extension 1412, and the third extension 1413. The remaining second insulating layer 142 may include a fourth extension 1424 and a fifth extension 1425. Alternatively, referring to fig. 25, the remaining second insulating layer 142 may include a fourth extension 1424, a fifth extension 1425, and a sixth extension 1426.
A third embodiment of forming the second insulating layer 142 and then exposing the first conductive member 110 according to the embodiment of the present application is described below.
Referring to fig. 26, forming the second insulating layer 142 may further include, the second insulating layer 142 may fill a portion of the second trench 152, a portion of the second insulating layer 142 filling the second trench 152 may form a filling portion 1421, and the filling portion 1421 may cover an end surface of the first conductive member 110 facing the second surface 101b, i.e., the filling portion 1421 may have a thickness greater than that of the first conductive member 110 exposed in the second trench 152. Referring to fig. 29, a second sacrificial layer is formed, which may fill the second trench 152 of another partial depth. Then, a portion of the second sacrificial layer is removed to form a fourth trench 154, the fourth trench 154 may be located in the second sacrificial layer in the second trench 152, the fourth trench 154 may have a smaller size than the second trench 152, and a bottom of the fourth trench 154 may expose the filling portion 1421, thereby achieving a half-filling effect of the second sacrificial layer and the second insulating layer 142. The remaining second sacrificial layer may cover the edge of the filling portion 1421, may also cover the second insulating layer 142 over the filling portion 1421, and may form the second mask layer 1722. The filling portion 1421 may serve as an etch stop layer of the second sacrificial layer, so that a half-filling process window of the second sacrificial layer may be enlarged. In the subsequent etching process, the second mask layer 1722 can protect the filling portion 1421 covered by the second mask layer 1722 and the second insulating layer 142 above the filling portion 1421, so as to avoid the filling portion 1421 and the second insulating layer 142 above the filling portion 1421 from being damaged, which is beneficial to improving the electrical isolation between the second conductive element 120 and the substrate 101. Referring to fig. 30, exposing the first conductive member 110 may include removing a portion of the first insulating layer 141 and a portion of the filling portion 1421 on the first conductive member 110 located in the second trench 152 using the second mask layer 1722 as a mask. Referring to fig. 31, after exposing the first conductive member 110, removing the second mask layer 1722 may be included.
Wherein the remaining first insulating layer 141 may include the first extension 1411, or, referring to fig. 32, the remaining first insulating layer 141 may include the first extension 1411 and the second extension 1412, or, the remaining first insulating layer 141 may include the first extension 1411, the second extension 1412, and the third extension 1413. Referring to fig. 32, the remaining second insulating layer 142 may include a fourth extension 1424 and a fifth extension 1425. One ends of the fifth extension portion 1425 and the fourth extension portion 1424 near the bottom of the second trench 152 are formed by the remaining filling portion 1421, and one end of the fourth extension portion 1424 near the notch of the second trench 152 is formed by the second insulating layer 142 above the filling portion 1421. At least a portion of the remaining fill 1421 may have a thickness greater than the remaining portion of the second insulating layer 142, i.e., the second insulating layer 142 above the fill 1421. Wherein the thickness of the filling portion 1421 (i.e., the first thickness) located on the groove sidewall of the second trench 152 may be greater than the thickness of the remaining portion of the second insulating layer 142 (i.e., the second thickness). The thickness of the filling portion 1421 located on the groove bottom wall of the second groove 152 may be greater than, equal to, or less than the thickness of the remaining portion of the second insulating layer 142.
Illustratively, the material of any one of the first insulating layer 141 and the second insulating layer 142 may include an oxide (e.g., silicon oxide) and a nitride (e.g., silicon nitride). The material of the second sacrificial layer may comprise an organic material or a semiconductor material such as Si, siGe, etc. The etching rates of the first insulating layer 141 and the second insulating layer 142 may be the same or different.
In some examples, referring to fig. 26, forming the second insulating layer 142 may include forming an insulating material layer 142a, the insulating material layer 142a may cover a wall of the second trench 152 and the first insulating layer 141 exposed in the second trench 152, and the insulating material layer 142a may form the second insulating layer 142. A fifth trench 155 may be formed between the sidewall of the first insulating layer 141 located in the second trench 152 and the trench sidewall of the second trench 152, the fifth trench 155 being located in the second trench 152. The thickness of the insulating material layer 142a may be twice greater than the width W of the notch of the fifth trench 155 so that the insulating material layer 142a may fill the fifth trench 155 and form a filling portion 1421. By this arrangement, the insulating material layer 142a (i.e., the second insulating layer 142) can be formed by one-step conformal deposition, and the half-filling effect of the second insulating layer 142 is achieved, so that the preparation of the second insulating layer 142 is simpler. In another example, referring to fig. 27 and 28, the second insulating layer 142 may include a first insulating material layer 142b and a second insulating material layer 142c. Referring to fig. 27, forming the second insulating layer 142 may include forming a first insulating material layer 142b, and the first insulating material layer 142b may cover a wall of the second trench 152 and the first insulating layer 141 exposed in the second trench 152. For example, the first layer of insulating material 142b may be formed by conformal deposition, thereby making the preparation of the first layer of insulating material 142b simpler. Then, referring to fig. 28, a second insulating material layer 142c is formed, the second insulating material layer 142c may fill the second trench 152 of a partial depth, and the first insulating material layer 142b and the second insulating material layer 142c near the bottom of the second trench 152 may together form a filling portion 1421. The second insulating material layer 142c may be formed in a bottom-up selective growth manner (bottom-up growth), the second insulating material layer 142c may be deposited using a material having fluidity, and then annealed and cured, and the second insulating material layer 142c may fill the fifth trench 155 and cover the end surface of the first conductive member 110 facing the second surface 101b to achieve a half-filling effect of the second insulating layer 142. During the exposure of the first conductive element 110, the second insulating material layer 142c and the second mask layer 1722 may completely cover the first insulating material layer 142b, so that the first insulating material layer 142b may be protected from damage of the first insulating material layer 142b to ensure electrical isolation between the second conductive element 120 and the substrate 101.
The following description is given of the first conductive element 110 being exposed and the second insulating layer 142 being formed in this embodiment.
Referring to fig. 17, exposing the first conductive member 110 may include removing at least a portion of the first insulating layer 141 exposed in the second trench 152 such that the second trench 152 exposes the first conductive member 110. The first insulating layer 141 and the substrate 101 are different in material. The first insulating layer 141 may have a high etching selectivity with respect to the substrate 101, thereby achieving selective etching of the first insulating layer 141 and reducing damage to the substrate 101. The etching selectivity of the first insulating layer 141 to the substrate 101 may be greater than or equal to 5:1, for example, the etching selectivity of the first insulating layer 141 to the substrate 101 may be 5:1, 6:1, 7:1, 9:1, 10:1, or any value greater than 5:1. The principle is already described and will not be described again.
Illustratively, the material of the substrate 101 may include silicon, and the material of the first insulating layer 141 may include oxide (e.g., silicon oxide) or nitride (e.g., silicon nitride).
Then, referring to fig. 18, after exposing the first conductive member 110, it may include oxidizing the substrate 101 at the wall of the second trench 152 to form the second insulating layer 142. The second insulating layer 142 may be selectively formed at the wall of the second trench 152 by an oxidation process without changing the material property of the first conductive member 110 exposed in the second trench 152, and without forming the second insulating layer 142 on the portion of the first conductive member 110. Since the second insulating layer 142 is not formed on the exposed first conductive member 110, there is no need to consider the etching selection ratio of the second insulating layer 142 to the first insulating layer 141, thereby expanding the selection range of the material of the second insulating layer 142, and in addition, damage to the second insulating layer 142 can be completely avoided, so as to better ensure electrical isolation between the second conductive member 120 and the substrate 101.
Illustratively, the material of the second insulating layer 142 may include an oxide (e.g., silicon oxide formed after oxidation of the substrate silicon).
Wherein the remaining first insulating layer 141 may include the first extension 1411, or the remaining first insulating layer 141 may include the first extension 1411 and the second extension 1412, or, referring to fig. 19, the remaining first insulating layer 141 may include the first extension 1411, the second extension 1412, and the third extension 1413. The oxidized second insulating layer 142 may include a fourth extension portion 1424 and a fifth extension portion 1425.
S700: and forming a second conductive piece, wherein the second conductive piece is positioned on the second insulating layer and fills the second groove, an inserting groove is formed at one end of the second conductive piece facing the first surface, and the inserting part is positioned in the inserting groove and is abutted with the groove wall of the inserting groove.
Referring to fig. 19, 25, and 32, after forming the second insulating layer 142 and exposing the first conductive member 110, forming the second conductive member 120 may include, the second conductive member 120 may be located on the second insulating layer 142, and the second conductive member 120 may fill the second trench 152. An end of the second conductive member 120 facing the first surface 101a may be formed with an insertion groove 121, the insertion portion 111 may be located in the insertion groove 121, and the insertion portion 111 may abut against a groove wall of the insertion groove 121, so as to electrically connect the first conductive member 110 and the second conductive member 120. At least a portion of the first conductive member 110 located in the second trench 152 may form the insertion portion 111, wherein in an embodiment in which both the first conductive member 110 and the second conductive member 120 include a barrier layer and a conductive body, the insertion portion 111 abuts against a wall of the insertion groove 121, that is, the first barrier layer 1311 and the second barrier layer 1312.
In embodiments in which the second conductive member 120 includes the second barrier layer 1312 and the second conductive body 1322, forming the second conductive member 120 may include forming the second barrier layer 1312, the second barrier layer 1312 being located on the second insulating layer 142 and the interposer 111, and then forming the second conductive body 1322, the second conductive body 1322 being located on the second barrier layer 1312, and the second conductive body 1322 may fill the second trench 152.
Referring to fig. 1-3, after forming the second conductive member 120, forming the third interconnection member 183 and the second dielectric layer 162 may include, the second dielectric layer 162 may cover a side of the second conductive member 120 and the passivation layer 196 facing away from the substrate 101, the third interconnection member 183 may be electrically connected with the second conductive member 120, and the third interconnection member 183 may be located in the second dielectric layer 162. Wherein third interconnect 183 may include third barrier layer 1313 and third conductive body 1323, third barrier layer 1313 may be located on an end face and sidewalls of third conductive body 1323 facing first surface 101 a.
By selective growth is meant that a certain material is deposited/grown by a certain process means only on a certain location or on a certain substrate material. By material half-filling is meant that a non-complete filling of a certain material is achieved in the structure of the holes or grooves by means of a certain process. Bottom-up growth refers to the realization of Bottom-up growth of a material in a structure of holes or trenches by means of a process, which may be one of the means of material half-filling.
It should be noted that, the numerical values and the numerical ranges referred to in the embodiments of the present application are approximate values, and may have a certain range of errors under the influence of the manufacturing process, and those errors may be considered to be negligible by those skilled in the art.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (13)
1. An interconnect structure, comprising: the substrate comprises a first surface and a second surface which are opposite in the thickness direction and are arranged at intervals, one side of the first surface of the substrate is provided with a first groove, one side of the second surface of the substrate is provided with a second groove, the bottom of the second groove is arranged at intervals with the first surface, and one end of the first groove, which is close to the second surface, is positioned in the second groove and is communicated with the second groove;
The first conductive piece is positioned in the first groove, the second conductive piece is positioned in the second groove, the first insulating layer is positioned between the first conductive piece and the wall of the first groove, and the second insulating layer is positioned between the second conductive piece and the wall of the second groove;
the first conductive piece is towards one end of the second surface is provided with an inserting portion, one end of the second conductive piece is towards the first surface is provided with an inserting groove, the inserting portion is located in the inserting groove and is abutted to the groove wall of the inserting groove, and the end face of the inserting portion towards the second surface and the side wall of the inserting portion are in contact with the groove wall of the inserting groove.
2. The interconnect structure of claim 1, wherein the first insulating layer further extends between the sidewall of the first conductive member and the second insulating layer of the bottom wall of the second trench.
3. The interconnect structure of claim 1, wherein at least one of the first insulating layer and the second insulating layer further extends between the interposer and a wall of the interposer slot.
4. The interconnect structure of any of claims 1-3, wherein at least a portion of the second insulating layer proximate a bottom of the second trench has a first thickness, the second insulating layer proximate a notch of the second trench has a second thickness, the first thickness being greater than the second thickness;
And/or at least one of the first and second conductive members comprises a conductive body and a barrier layer between the conductive body and the substrate;
and/or the interconnection structure further comprises a dielectric layer and a plurality of active regions, wherein the dielectric layer is positioned between two adjacent active regions, and the first groove extends from the substrate into the dielectric layer.
5. A method of fabricating an interconnect structure, comprising:
providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite in the thickness direction and are arranged at intervals;
forming a first trench on one side of the first surface of the substrate;
forming a first insulating layer, wherein the first insulating layer covers the groove wall of the first groove;
forming a first conductive member which is positioned on the first insulating layer and fills the first groove, wherein an inserting part is formed at one end of the first conductive member facing the second surface;
forming a second groove on one side of the second surface of the substrate, wherein the groove bottom of the second groove is arranged at intervals with the first surface, the second groove exposes the groove bottom wall of the first groove and the first insulating layer on part of the groove side wall of the first groove, and one end of the first groove, which is close to the second surface, is positioned in the second groove and communicated with the second groove;
Forming a second insulating layer, wherein the second insulating layer covers the groove wall of the second groove; removing at least a portion of the first insulating layer exposed in the second trench to expose the second trench to the first conductive member, the remaining first insulating layer being located between the first conductive member and a wall of the first trench;
the second conductive piece is positioned on the second insulating layer and fills the second groove, an inserting groove is formed at one end of the second conductive piece, which faces the first surface, the inserting part is positioned in the inserting groove and is abutted to the groove wall of the inserting groove, and the end face of the inserting part, which faces the second surface, and the side wall of the inserting part are contacted with the groove wall of the inserting groove.
6. The method of manufacturing an interconnect structure according to claim 5, wherein the material of the substrate comprises silicon, the material of the second insulating layer comprises silicon oxide, and an etching selectivity ratio of the first insulating layer to the substrate is greater than or equal to 5:1;
forming the second insulating layer and exposing the first conductive member includes:
firstly exposing the first conductive element;
and oxidizing the substrate at the wall of the second trench to form the second insulating layer.
7. The method of manufacturing an interconnect structure of claim 5, wherein forming the second insulating layer and exposing the first conductive member comprises:
the second insulation is formed first, and then the first conductive member is exposed.
8. The method for manufacturing an interconnection structure according to claim 7, wherein a material of the substrate comprises silicon, a material of the second insulating layer comprises silicon oxide, and an etching selection ratio of the first insulating layer to the second insulating layer is greater than or equal to 5:1;
forming the second insulating layer includes: oxidizing the substrate at the wall of the second trench to form the second insulating layer.
9. The method of manufacturing an interconnect structure of claim 7, wherein,
forming the second insulating layer further includes: forming the second insulating layer on the first insulating layer exposed in the second trench;
forming a first sacrificial layer which is positioned on the second insulating layer and fills the second groove;
forming a third groove, wherein the third groove is positioned in the first sacrificial layer in the second groove, the bottom of the third groove exposes the second insulating layer, the reserved first sacrificial layer covers the second insulating layer on the wall of the second groove, and a first mask layer is formed;
Exposing the first conductive element comprises: taking the first mask layer as a mask, and removing part of the first insulating layer and part of the second insulating layer;
and removing the first mask layer.
10. The method of manufacturing an interconnect structure of claim 7, wherein,
forming the second insulating layer further includes: the second insulating layer fills the second groove with partial depth and forms a filling part, and the filling part covers the end face of the first conductive piece facing the second surface;
forming a second sacrificial layer, wherein the second sacrificial layer fills the second groove with the other part of depth;
forming a fourth groove, wherein the fourth groove is positioned in the second sacrificial layer in the second groove, the bottom of the fourth groove exposes the filling part, and the reserved second sacrificial layer forms a second mask layer;
exposing the first conductive element comprises: taking the second mask layer as a mask, removing part of the first insulating layer and part of the filling part, wherein the thickness of at least part of the remaining filling part is larger than that of the rest part of the second insulating layer;
and removing the second mask layer.
11. The method of fabricating an interconnect structure of claim 10, wherein,
Forming the second insulating layer includes: forming an insulating material layer covering a wall of the second trench and exposed on the first insulating layer in the second trench, the insulating material layer forming the second insulating layer; a fifth trench is formed between the side wall of the first insulating layer and the side wall of the second trench in the second trench, and the thickness of the insulating material layer is twice greater than the width of the notch of the fifth trench, so that the insulating material layer fills the fifth trench and the filling part is formed;
alternatively, the second insulating layer includes a first insulating material layer and a second insulating material layer;
forming the second insulating layer includes: forming a first insulating material layer covering a wall of the second trench and exposed on the first insulating layer in the second trench;
and forming a second insulating material layer, wherein the second insulating material layer fills the second groove with partial depth, and the first insulating material layer and the second insulating material layer which are close to the bottom of the second groove jointly form the filling part.
12. The method of manufacturing an interconnect structure according to any one of claims 5 to 11, wherein the first insulating layer remaining further extends between the side wall of the first conductive member and the second insulating layer of the bottom wall of the second trench;
Alternatively, the first insulating layer which remains also extends between the insertion portion and the wall of the insertion groove.
13. The method of manufacturing an interconnect structure according to claim 9, wherein the remaining second insulating layer further extends between the insertion portion and a wall of the insertion groove.
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