CN112885842B

CN112885842B - Three-dimensional memory and preparation method thereof

Info

Publication number: CN112885842B
Application number: CN202110301510.2A
Authority: CN
Inventors: 张坤; 周文犀; 夏志良
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-03-22
Filing date: 2021-03-22
Publication date: 2023-04-07
Anticipated expiration: 2041-03-22
Also published as: CN112885842A

Abstract

The application provides a three-dimensional memory and a preparation method thereof. The preparation method comprises the following steps: forming a laminated structure on a first side of a substrate, forming a channel structure penetrating the laminated structure and extending to the substrate, wherein the channel structure comprises: a functional layer and a channel layer sequentially formed on the inner wall of the channel hole, the functional layer including a charge trapping layer; removing a portion of the substrate from a second side of the substrate opposite the first side; carrying out high doping on the exposed channel layer after part of the substrate is removed; removing a portion of the charge trapping layer to form an air gap layer in a portion of the functional layer adjacent the second side; forming a cap layer at an end of the air gap layer proximate the second side; and forming a conductive layer connecting the channel layer at the second side. By the manufacturing method, an air gap layer can be formed in the functional layer of the three-dimensional memory, and the situation that when an erasing operation is carried out, the generated grid-induction-drain-leakage (GIDL) auxiliary body bias voltage is too high to break down partial functional layer is prevented.

Description

Three-dimensional memory and preparation method thereof

Technical Field

The present application relates to the field of semiconductor design and manufacturing, and more particularly, to a structure of a three-dimensional memory (3D NAND) and a method for fabricating the same.

Background

In a conventional three-dimensional memory fabrication process, a channel layer formed in a channel hole needs to be connected to a well layer in a substrate to form a circuit loop in which a memory cell operates.

However, the number of stacked layers of the three-dimensional memory is larger than 200 at present, and as the number of stacked layers increases, the aspect ratio of the channel hole increases, and the process requirements of a larger number of stacked structures, such as a deep hole etching process, a process for forming an epitaxial layer at the bottom of the channel hole, a dry etching process and a wet etching process for removing the sacrificial layer and the functional layer of the substrate extending to the substrate in the gate line gap, and the like, are difficult to support.

In addition, as the number of stacked layers increases, ductility between different layers in the stacked structure becomes poor, and leakage current between the word line and the common source increases. Further, due to the increase in the number of lamination layers, the overlay accuracy (OVL) of the plurality of layers with respect to each other becomes difficult to control due to the influence of stress and the like.

These technical problems ultimately affect the electrical performance of the fabricated three-dimensional memory, resulting in degraded reliability or low wafer test yield.

Disclosure of Invention

The present application provides a three-dimensional memory and a method of fabricating the same that can at least partially solve the above-mentioned problems in the prior art.

One aspect of the present application provides a method of fabricating a three-dimensional memory, the method including: forming a stack structure on a first side of a substrate, forming a channel structure through the stack structure and extending to the substrate, the channel structure comprising: the functional layer and the channel layer are sequentially formed on the inner wall of the channel hole, and the functional layer comprises a charge trapping layer; removing a portion of the substrate from a second side of the substrate opposite the first side; carrying out high doping on the exposed channel layer after part of the substrate is removed; removing a portion of the charge trapping layer to form an air gap layer in a portion of the functional layer adjacent the second side; forming a cap layer at an end of the air gap layer proximate the second side; and forming a conductive layer connecting the channel layer at the second side.

In one embodiment of the present application, the functional layer further comprises a tunneling layer, wherein forming an air gap layer at a portion of the functional layer proximate to the second side further comprises: and removing a part of the tunneling layer corresponding to a part of the charge trapping layer to form an air gap layer on a part of the functional layer close to the second side.

In one embodiment of the present application, the stacked structure includes a plurality of stacked layers, each of the stacked layers includes a pair of dielectric layers and a gate layer, wherein forming an air gap layer at a portion of the functional layer near the second side includes: removing portions of the charge-trapping layer and the first stack layer or portions of the charge-trapping layer and the tunneling layer on the substrate and the first stack layer, respectively, to form the air gap layer, wherein the first stack layer is closest to the substrate among the plurality of stack layers.

In one embodiment of the present application, the first stack layer includes at least one source select gate layer.

In one embodiment of the present application, forming a conductive layer connecting the channel layer at the second side includes: and forming a highly doped semiconductor layer connected with the channel layer on the second side.

In one embodiment of the present application, forming the highly doped semiconductor layer at the second side further comprises: and carrying out an excimer laser annealing process on the highly doped semiconductor layer.

In one embodiment of the present application, before processing the substrate from a second side of the substrate opposite to the first side, the method further comprises: and connecting a peripheral circuit chip on one side of the laminated structure far away from the substrate.

In one embodiment of the present application, the substrate includes a base plate, an etching stop layer, and a substrate semiconductor layer, which are sequentially disposed, and the removing a portion of the substrate includes: and removing the base plate and the etching stop layer, and part of the channel structure to stop at the substrate semiconductor layer.

Another aspect of the present application provides a three-dimensional memory, including: a conductive layer; and a stacked structure disposed on the conductive layer, the stacked structure including gate layers and dielectric layers alternately stacked; and the channel structure penetrates through the laminated structure and is in contact with the conducting layer, the channel structure comprises a channel hole, and a functional layer and a channel layer which are sequentially arranged on the inner side wall of the channel hole, wherein the functional layer comprises a charge trapping layer and a first air gap layer arranged between the charge trapping layer and the conducting layer.

In one embodiment of the present application, the functional layer further comprises a first capping layer disposed between the first air gap layer and the conductive layer.

In an embodiment of the present application, the functional layer further includes a tunneling layer and a second air gap layer disposed between the tunneling layer and the conductive layer, wherein the second air gap layer and the first air gap layer jointly constitute the air gap layer of the functional layer.

In one embodiment of the present application, the functional layer further includes a second cap layer disposed between the second air gap and the conductive layer, and the second cap layer is the same material as the first cap layer.

In one embodiment of the present application, the first air gap layer or the air gap layer is located at a portion of the functional layer corresponding to a first stacked layer adjacent to the conductive layer in the stacked structure.

In one embodiment of the present application, the conductive layer is a highly doped semiconductor layer.

In one embodiment of the present application, the highly doped semiconductor layer is a highly doped polysilicon layer.

According to the three-dimensional memory and the preparation method thereof provided by the embodiment of the application, the channel layer is led out from the back surface, a deep hole etching process is avoided, and the preparation method of the three-dimensional memory is simplified. According to at least one embodiment of the present application, the present application provides a manufacturing method, in which an air gap layer is formed between a functional layer and a conductive layer by removing a portion of a charge trapping layer or removing a portion of the charge trapping layer and a portion of a tunneling layer, respectively, and the air gap layer can ensure stability of a gate-induced-drain-leakage (GIDL) sub-body bias generated when an erase operation ("GIDL erase" in the present application) is performed on a three-dimensional memory.

In addition, according to another embodiment of the present disclosure, by selecting a highly doped semiconductor layer as a conductive layer for connecting to a channel layer and performing, for example, a chemical mechanical polishing process (Buffer CMP) with a low grinding rate and an excimer Laser annealing process (Laser Anneal) on the highly doped semiconductor layer, good electrical connection between the conductive layer and the channel layer is achieved, and electrical properties of a three-dimensional memory are improved.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, which proceeds with reference to the accompanying drawings. Wherein:

FIG. 1 is a flow chart of a method for fabricating a three-dimensional memory according to one embodiment of the present application;

fig. 2 to 18 are process schematic views of a manufacturing method according to an embodiment of the present application, respectively; and

fig. 19 to 20 are process diagrams of a conventional method for fabricating a three-dimensional memory.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that in this specification the expressions first, second, third etc. are only used to distinguish one feature from another, and do not indicate any limitation of features, in particular any order of precedence. Thus, a first side discussed in this application may also be referred to as a second side, and a first window may also be referred to as a second window, and vice versa, without departing from the teachings of this application.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than merely individual elements of the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Further, when "connected" or "coupled" is used in this application, it may mean either direct contact or indirect contact between the respective components, unless there is an explicit other limitation or can be inferred from the context.

Fig. 1 is a flow chart of a method 1000 of fabricating a three-dimensional memory according to one embodiment of the present application. As shown in fig. 1, a method 1000 for manufacturing a three-dimensional memory provided by the present application includes:

s1, forming a laminated structure on a first side of a substrate, and forming a channel structure penetrating through the laminated structure and extending to the substrate, wherein the channel structure comprises: and the functional layer and the channel layer are sequentially formed on the inner wall of the channel hole, and the functional layer comprises a charge trapping layer.

And S2, removing a part of the substrate from a second side of the substrate, which is opposite to the first side.

And S3, carrying out high doping on the exposed channel layer after removing part of the substrate.

And S4, removing part of the charge trapping layer to form an air gap layer on the part, close to the second side, of the functional layer.

And S5, forming a cover layer at the end part of the air gap layer close to the second side.

And S6, forming a conducting layer connected with the channel layer on the second side.

The specific processes of the steps of the above-described manufacturing method 1000 will be described in detail below with reference to fig. 2 to 18.

Step S1

Fig. 2 is a schematic cross-sectional structure of a substrate 100 provided in a manufacturing method according to an embodiment of the present application. Fig. 3 is a schematic cross-sectional view of a structure formed after forming a channel structure 300 in the stacked structure 200 according to one embodiment of the fabrication method of the present application.

As shown in fig. 2 and 3, step S1 forms a stacked structure on a first side of a substrate, and forms a channel structure penetrating the stacked structure and extending to the substrate, the channel structure including: the functional layer and the channel layer sequentially formed on the inner wall of the channel hole, the functional layer including the charge trap layer may include, for example: preparing a substrate 100; forming a stacked structure 200 on a first side 101 of a substrate 100; forming a step region 500 in the stacked structure 200; forming a channel hole 310 in the stacked structure 200, the channel hole 310 penetrating the stacked structure 200 in a thickness direction of the stacked structure 200 and extending into the substrate 100; a channel structure including a channel layer 330 and a functional layer 320 is sequentially formed on the inner wall of the channel hole 310, wherein the functional layer 320 includes a blocking layer, a charge trapping layer, and a tunneling layer sequentially disposed on the inner wall of the channel hole 310.

Specifically, in one embodiment of the present application, the substrate 100 may be made of any suitable semiconductor material, such as monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide, or other iii-v compounds. Further, the substrate 100 may be selected from single crystal silicon.

In one embodiment of the present application, the substrate 100 may be, for example, a composite substrate for supporting device structures thereon. A plurality of layers made of different materials may be sequentially disposed through a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof to form the substrate 100. For example, the substrate 100 may include a base plate (not shown), an etch stop layer 130, and a substrate semiconductor layer 120, which are sequentially formed.

Etch stop layer 130 may comprise a single layer, multiple layers, or suitable composite layers. For example, the etch stop layer 130 may include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Alternatively, the etch stop layer 130 may be a high-k dielectric layer, and alternatively, the etch stop layer 130 may include a dielectric layer, a sacrificial layer and a dielectric layer sequentially disposed, wherein the dielectric layer may be a silicon nitride layer, and the sacrificial layer may be a silicon oxide layer. Alternatively, etch stop layer 130 may comprise any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, the sacrificial layer may be single crystalline silicon or polycrystalline silicon, and particularly, in one embodiment of the present application, an exemplary material forming the sacrificial layer may be polycrystalline silicon.

A well region doped with N-type or P-type dopants through an ion implantation or diffusion process may also be formed in a portion of the substrate 100, for example, in the substrate semiconductor layer 120. The dopant may include any one or combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of the present application, the well regions may be prepared by selecting the same dopant or different dopants, and further, the doping concentration of the well regions may be the same or different, which is not limited in the present application.

The substrate 100 has opposite first and

second sides

101, 102. After forming the substrate 100, the stacked structure 200 may be formed on the first side 101 of the substrate 100 by one or more thin film deposition processes, which may include, but are not limited to, CVD, PVD, ALD, or any combination thereof, which is not limited in this application. The stack structure 200 may include a plurality of pairs of dielectric layers 210 and gate sacrificial layers 220 alternately stacked on each other. For example, the stacked structure 200 may include 64 pairs, 128 pairs, or more than 128 pairs of dielectric layers 210 and gate sacrificial layers 220. In some embodiments, the dielectric layer 210 and the gate sacrificial layer 220 may include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. Exemplary materials for forming the dielectric layer 210 and the gate sacrificial layer 220 may include silicon oxide and silicon nitride, respectively. A silicon oxide layer may be used as the isolation stack layer and a silicon nitride layer may be used as the sacrificial stack layer. The sacrificial stack layer can then be etched away and replaced with a conductor layer comprising a conductive material.

The method of making the single laminate structure 200 is described above. In fact, with the increasing memory requirement of the three-dimensional memory, the memory stack size gradually increases. In order to break through the limitation of the traditional process limit, a double-stack technology or a multi-stack technology can be adopted, and a stack structure is formed by sequentially stacking N (N is more than or equal to 2) sub-stack structures in the thickness direction of the stack structure, wherein each sub-stack structure can comprise a plurality of insulating layers and gate sacrificial layers which are alternately stacked. The number of layers of each sub-stack structure may be the same or different. However, it will be understood by those skilled in the art that subsequent fabrication processes may be performed on the basis of a multi-stack structure or a single-stack structure.

The stair-step structure 500 may be formed by performing a plurality of "trim-etch" cycles on edge portions of the stacked structure 200 such that the stacked structure 200 has one or more sloped edges and a top (away from the substrate 100) dielectric layer pair that is shorter than a bottom (closer to the substrate 100) dielectric layer pair (dielectric layer 210 and gate sacrificial layer 220). Any suitable etching process (including any one or combination of a dry etching process and a wet etching process) may be used in the step formation process. Further, a dielectric layer 510 may also be formed to cover the step.

The channel hole 310 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes. Other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, may also be performed. The channel hole 310 may have a cylindrical or pillar shape penetrating the stacked structure 200 and extending to the substrate 100. In one embodiment of the present application, the channel hole 310 penetrates the stack 200 and extends into the etch stop layer 130.

In some embodiments of the present application, the channel hole 310 may be formed after the step structure 500 is formed. In some other embodiments, the channel hole 310 may also be formed before the step structure 500 is formed.

Further, after the multi-stack technology is adopted to form the stack structure, the stack structure may include N sub-stack structures, and correspondingly, the channel hole may also include N sub-channel holes, where the N sub-stack structures correspond to the N sub-channel holes one to one, and N is greater than or equal to 2. Forming the channel hole in the stacked structure using the multi-stack technique may include: forming a first sub-stack structure on one side of the substrate and forming a first sub-channel hole penetrating the first sub-stack structure and extending into the substrate; continuing to form subsequent sub-laminated structures and sub-channel holes until an Nth sub-laminated structure and an Nth sub-channel hole are formed, wherein N-1 hole-filling sacrificial layers are correspondingly filled in N-1 sub-channel holes except the Nth sub-channel hole; and removing the N-1 hole filling sacrificial layers based on the Nth sub-channel hole, so that the upper and lower adjacent sub-channel holes in the N sub-channel holes are at least partially aligned with each other, and obtaining the channel hole.

The channel structure 300 includes a channel hole 310 filled with a semiconductor layer and a composite dielectric layer. The functional layer 320 and the channel layer 330 may be formed on the inner wall of the channel hole 310 by a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof.

Specifically, the functional layer 320 may include a blocking layer (not shown) formed on an inner wall of the channel hole 310 to block outflow of charges, a charge trapping layer (not shown) on a surface of the blocking layer to store charges during operation of the three-dimensional memory, and a tunneling layer (not shown) on a surface of the charge trapping layer. The barrier layer may include one or more layers, which may include one or more materials. Materials for the barrier layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, and the like. The charge trapping layer may comprise one or more layers, which may comprise one or more materials. Materials for the charge trapping layer may include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide band gap material, and the like. The tunneling layer may include one or more layers, which may include one or more materials. Materials for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, and the like.

In some embodiments, the functional layer 320 may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 320 may have a structure different from the ONO configuration. For example, the functional layer 320 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

The channel layer 330 can be used to transport desired charges (electrons or holes). According to an exemplary embodiment of the present application, the channel layer 330 may be formed on the surface of the tunneling layer through a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof.

In some embodiments, the channel layer 330 may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The material of the channel layer 330 includes, but is not limited to, P-type doped polysilicon. Similar to the channel hole 310, the channel layer 330 also extends through the stacked-layer structure 200 and into the substrate 100.

In one embodiment of the present application, the functional layer 320 including the blocking layer, the charge trapping layer, the tunneling layer, and the channel layer 330 penetrate the stacked structure 200 and extend into the etch stop layer 130.

The method 1000 for manufacturing a three-dimensional memory according to an embodiment of the present application further includes: a channel plug (not shown) is formed on the top of the channel hole 310 away from the substrate 100.

In particular, the channel hole 310 may be filled with a filling dielectric layer. The filling dielectric layer can comprise an oxide dielectric layer, such as silicon oxide. Further, in the filling process, a plurality of insulating gaps can be formed in the filling dielectric layer by controlling the channel filling process so as to relieve the structural stress. A trench plug is then formed in the portion of the filling dielectric layer that is on top of the channel hole 310. The material of the channel plug may be selected from the same material as the channel layer 330, such as P-type doped polysilicon.

Fig. 4 is a schematic cross-sectional view of a structure formed after forming a gate line gap structure 400 and a gate electrode layer 230 in a stacked structure 200 according to a fabrication method of an embodiment of the present application.

Further, as shown in fig. 4, a method 1000 for manufacturing a three-dimensional memory according to an embodiment of the present application further includes: a gate line gap structure 400 having a distance from the channel structure 300 is formed in the stacked structure 200, and the gate line gap structure 400 penetrates the stacked structure 200 in a thickness direction of the stacked structure 200 and extends into the substrate 100.

The gate line gap 410 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes. The gate line gap 410 may extend through the stacked structure 200, and extend through the stacked structure 200 and into the substrate 100 in a thickness direction of the stacked structure 200.

According to an embodiment of the present application, the method 1000 for fabricating a three-dimensional memory further includes a step of disposing the gate layer 230 in the stacked structure 200. The step of disposing the gate layer 230 may, for example, include: removing the gate sacrificial layer based on the gate line gap 410 to form a sacrificial gap; a gate layer 230 is formed within the sacrificial gap.

Specifically, the gate line gap 410 may be used as a path for providing an etchant and a chemical precursor, and all of the gate sacrificial layer 220 (as shown in fig. 3) in the stacked structure 200 may be removed by a process such as wet etching to form a sacrificial gap. Gate layer 230 may be formed in the sacrificial gap using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The gate layer 230 may be made of a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide.

The gate layer 230 may extend laterally (perpendicular to the thickness direction of the stacked structure 200) as a word line, terminating at one or more of the stair-step structures 500 of the stacked structure 200.

After forming the gate layer 230, the gate line gap structure 400 may be formed by filling the gate line gap 410. Specifically, a dielectric layer may be filled in the gate line gap 410 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

In a conventional three-dimensional memory fabrication process, a channel layer formed in a channel hole needs to be connected to a well layer in a substrate to form a circuit loop in which a memory cell operates. As shown in fig. 19, in a conventional method for manufacturing a three-dimensional memory, a functional layer 32, such as a silicon oxide-silicon nitride-silicon oxide structure (ONO), may be deposited in a trench hole 31, and then deep-hole etching may be performed on the bottom of the trench hole 31 to destroy the portion of the functional layer 32 located at the bottom of the trench hole 31, so as to expose the epitaxial layer 14 in the deep-hole, and connect the epitaxial layer 14 with a subsequently formed channel layer 33 in the trench hole 31. As shown in fig. 20, in a conventional three-dimensional memory manufacturing method, the substrate 10 may also be N-doped by a process such as ion implantation to form the well layer 11, and the lateral portion of the functional layer 32 extending into the substrate 10 is removed to expose a portion of the channel layer 33, so that a circuit loop for operating the memory cell is formed by connecting the well layer 11 and the exposed channel layer 33.

However, the number of stacked layers of the three-dimensional memory is greater than 200 at present, the aspect ratio of the channel hole increases with the increase of the number of stacked layers, and the deep hole etching process and the process of forming the epitaxial layer at the bottom of the channel hole are difficult to support the process requirements of a larger number of stacked structures. In addition, as the number of stacked layers increases, both dry etching processes and wet etching processes used to remove the sacrificial layer of the substrate and to remove the portion of the functional layer extending into the substrate in the gate line gap become very difficult, and ductility between different layers in the stacked structure also becomes poor. These technical problems ultimately affect the electrical performance of the fabricated three-dimensional memory, resulting in degraded reliability or low wafer test yield.

According to at least one embodiment of the present application, a channel layer is led out from the back surface, so that a deep hole etching process is avoided, and a three-dimensional memory manufacturing method is simplified. Further, according to the manufacturing method provided by one embodiment of the present application, an air gap layer is formed between the functional layer and the conductive layer by removing a portion of the charge trapping layer or removing a portion of the charge trapping layer and a portion of the tunneling layer, respectively, and the air gap layer can be formed by, for example, removing the charge trapping layer or the tunneling layer damaged by a high doping process during the manufacturing process. The air gap layer can ensure stability of a gate-induced-drain-leakage (GIDL) assisted body bias generated when the three-dimensional memory performs an erase operation ("GIDL erase" in the present application).

In addition, according to the method for manufacturing the three-dimensional memory provided by another embodiment of the present application, by selecting the highly doped semiconductor layer as the conductive layer for connecting the channel layer, and performing a chemical mechanical polishing process (Buffer CMP) with a low grinding rate and an excimer Laser annealing process (Laser Anneal) on the highly doped semiconductor layer, good electrical connection between the conductive layer and the channel layer is achieved, and electrical properties of the three-dimensional memory are improved.

Specifically, a specific process will be described in detail with reference to fig. 5 to 18.

Step S2

Fig. 5 is a schematic cross-sectional view of a structure formed after forming a peripheral contact 171 and a wordline contact 172 in a stepped region 500 according to one embodiment of the present disclosure. Fig. 6 is a schematic cross-sectional view of a structure formed after a peripheral circuit chip 3000 is connected to a side of the stacked-layer structure 200 remote from the substrate 100 according to a manufacturing method of an embodiment of the present application. Fig. 7 is a schematic cross-sectional view of a structure formed after thinning a substrate 100 according to a fabrication method of an embodiment of the present application. Fig. 8 is a schematic cross-sectional view of a structure formed after removing portions of the blocking layer, the charge trapping layer, the tunneling layer, and the channel layer 330, respectively, in the etch stop layer 130 according to a fabrication method of an embodiment of the present application.

As shown in fig. 5 to 8, the step S2 of removing a portion of the substrate from a second side of the substrate opposite to the first side may, for example, comprise: forming a peripheral contact 171 and a wordline contact 172 in the stepped region 500; a peripheral circuit chip 3000 is connected to the side of the laminated structure 200 away from the substrate 100; thinning the substrate 100 from the second side 102 of the substrate 100 to expose the etch stop layer 130; and removing portions of the blocking layer, the charge trapping layer, the tunneling layer, and the channel layer 330 at the etch stop layer 130, respectively.

As shown in fig. 5, the method 1000 of fabricating a three-dimensional memory further includes forming a word line contact 172 electrically connected to the gate layer 230 in the stacked structure 200; and forming a peripheral contact 171 in the stacked structure 200 to form an ohmic contact with the substrate well layer.

Specifically, after the gate line slit 410 is filled, openings for the peripheral contacts 171 and the word line contacts 172 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes. The openings for the peripheral contacts 171 and wordline contacts 172 are then filled with a conductive material by CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The conductive material forming peripheral contacts 171 and wordline contacts 172 may include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or a combination of two or more of these materials. In some embodiments, when preparing peripheral contacts 171 and wordline contacts 172, a layer of conductive material (e.g., titanium nitride TiN) may be deposited as a contact layer prior to depositing another conductive material.

The opening for the via may then be formed by a dry etching process or a combination of dry and wet etching processes. Some vias are configured for peripheral contact 171 and wordline contact 172. Some other vias are configured for each bit line contact that electrically contacts the upper end of the corresponding memory cell and individually addresses the corresponding memory cell.

Further, openings may be made similar to the via formation process and then filled to form

contacts

176, 177, and 178 that serve as interconnects to peripheral devices. The contacts 176 to 178 are electrically connected to the vias, respectively.

As shown in fig. 6, after forming the interconnect contacts 176 to 178, the method 1000 of fabricating a three-dimensional memory according to an embodiment of the present application further includes: the peripheral circuit chip 3000 is connected to the side of the stacked structure 200 remote from the substrate 100.

Specifically, the peripheral circuit chip 3000 may be placed over the top surface of the array chip 2000 (including the substrate 100 and the stacked-layer structure 200) on which the contacts 176 to 178 are provided. Then, an alignment step (for example, the interconnection contacts of the two chips may be aligned respectively) is performed, and thereafter, one surface of the peripheral circuit chip 3000 is bonded and bonded to the top surface of the array chip 2000.

In some embodiments, solder or a conductive adhesive may be used to bond each interconnect contact 176-178 with a corresponding contact of the peripheral circuit chip 3000 and to electrically connect the interconnect contacts 176-178 to corresponding contacts of the peripheral circuit chip 3000, respectively, such that the array chip 2000 and the peripheral circuit chip 3000 are in electrical communication.

The peripheral circuitry may include one or more of page buffers, decoders (e.g., row and column decoders), drivers, charge pumps, current or voltage references, or any active or passive components (e.g., transistors, diodes, resistors, or capacitors) required in the circuitry. In some embodiments, the peripheral circuitry may be formed by CMOS technology, but is not limited thereto.

The peripheral circuit chip 3000 and the bonding process can be performed by conventional processes, and are not described herein.

Fig. 7 is a schematic structural view of the structure of fig. 6, which is turned by 180 ° and then thinned. Referring to fig. 7, the substrate 100 may be subjected to a grinding and thinning process from the second side 102 using, for example, a Mechanical Chemical polishing (CMP) process until the etch stop layer 130 is exposed and the surface 103 of the thinned substrate 100 is formed. In other words, the etch stop layer 130 may act as a stop for the substrate thinning process to facilitate the substrate thinning step.

As shown in fig. 8, the exposed functional layer 320 may be removed based on the surface 103 (as shown in fig. 7) by using a plurality of times, for example, a dry etching process or a combination of dry and wet etching processes, in other words, the portions of the blocking layer, the charge trapping layer and the tunneling layer exposed at the surface 103 may be sequentially removed by using a plurality of times, for example, a dry etching process or a combination of dry and wet etching processes, and the portions of the blocking layer, the charge trapping layer and the tunneling layer formed in the etch stop layer 130 (as shown in fig. 7) may be continuously removed downward.

In some embodiments, the functional layer 320 including the blocking insulating layer, the charge storage layer, and the tunneling layer may have an oxide-nitride-oxide (ONO) structure surrounding the channel layer 330. An ONO removal process may be performed to sequentially remove portions of the layers of the channel layer 320 formed in the etch stop layer 130.

Further, based on the surface 103, a plurality of times, for example, a dry etching process or a combination of dry and wet etching processes, may be employed to remove the portion of the channel layer 330 exposed at the surface 103, and continue to remove the portion of the channel layer 330 formed in the etch stop layer 130 downward.

In one embodiment of the present application, the above-described thinning of the substrate 100 and removal of portions of the functional layer 320 and the channel layer 330 may be stopped at the substrate semiconductor layer 120. In other words, the above process of removing the substrate and the etch stop layer 130 (including a portion of the channel structure 300) may stop at the substrate semiconductor layer 120.Step S3

Referring again to fig. 8, the step S3 of heavily doping the channel layer exposed after removing a portion of the substrate may include, for example: carrying out planarization treatment on the substrate semiconductor layer 120 left after the etching stop layer 130 is removed to form a surface 112; and highly N-doped to the channel layer 330 exposed at the surface 112.

Specifically, after removing the etch stop layer 130 and, in turn, the portions of the functional layer 320 and the channel layer 330 formed in the etch stop layer 130, a planarization process may be performed on the newly formed substrate surface 112 by, for example, a mechanochemical polishing CMP process. Thereafter, the channel layer 330 may be doped N-type through the substrate surface 112 by a process such as ion implantation of IMP.

The N-type doping may include any suitable N-type dopant, such as phosphorus (P), arsenic (Ar), or antimony (Sb), to contribute free electrons and increase the conductivity of the intrinsic semiconductor.

Step S4

FIG. 9 is a cross-sectional view of a structure formed after an air gap layer 321 is formed in a functional layer 320 according to a fabrication method of an embodiment of the present application.

In a conventional three-dimensional memory manufacturing process, the doping process such as ion implantation may damage a portion of the structure in the functional layer, which may cause a higher gate-induced-drain-leakage (GIDL) auxiliary body bias voltage generated when the three-dimensional memory performs an erase operation (in this application, "GIDL erase"), thereby affecting the electrical performance of the finally formed three-dimensional memory.

According to the manufacturing method provided by the application, an air gap layer is formed between the functional layer and the subsequently formed conductive layer by removing part of the charge trapping layer or respectively removing part of the charge trapping layer and part of the tunneling layer, and the air gap layer can be formed by removing the charge trapping layer (or the damaged charge trapping layer and the tunneling layer) damaged due to a high doping process in the manufacturing process, so that the stability of a gate-induced-drain-leakage (GIDL) auxiliary body bias generated when the three-dimensional memory performs an erasing operation can be ensured.

Specifically, as shown in fig. 9, any suitable etching process (including any one or combination of a dry etching process and a wet etching process) may be used to remove the charge trapping layer damaged when the channel layer 330 is N-doped, for example, by a process such as ion implantation, to form the air gap layer 321. Alternatively, portions of the charge trapping layer located on and near the substrate semiconductor layer 120 are removed to form the air gap layer 321.

In one embodiment of the present application, any suitable etching process (including any one or combination of a dry etching process and a wet etching process) may be used to remove the charge trapping layer and the tunneling layer damaged when the channel layer 330 is N-doped, for example, by ion implantation, to form the air gap layer 321. Alternatively, portions of the charge trapping layer and the tunneling layer located on and near the substrate semiconductor layer 120 are removed to form the air gap layer 321. In other words, in the present embodiment, the air gap layer 321 of the functional layer 320 is constituted by a first air gap layer formed by removing the charge trapping layer and a second air gap layer formed by removing the tunneling layer.

In one embodiment of the present application, the stacked structure 200 includes a plurality of dielectric layers 210 and gate layers 230 stacked alternately, each dielectric layer 210 and an adjacent gate layer 230 form a stacked layer, wherein the dielectric layer and gate layer pair closest to the substrate semiconductor layer 120 is the first stacked layer 201. Alternatively, in one embodiment of the present application, any suitable etching process (including any one or combination of a dry etching process and a wet etching process) may be used to remove the portion including the charge trapping layer located on the substrate semiconductor layer 120 and the first stack layer 201 to form the air gap layer 321.

Alternatively, in another embodiment of the present application, any suitable etching process (including any one or combination of a dry etching process and a wet etching process) may be used to remove the portion including the charge trapping layer and the tunneling layer located on the substrate semiconductor layer 120 and the first stack layer 201 to form the air gap layer 321.

Further, in one embodiment of the present application, the first stack layer 201 includes at least one source selection gate layer.

The functional layer 320 is formed with an air gap layer 321, which can ensure that a gate-induced-drain-leakage (GIDL) auxiliary body bias voltage generated when the three-dimensional memory performs an erase operation is not too high to break down a portion of the functional layer, thereby affecting the electrical performance of the three-dimensional memory.

Step S5

Fig. 10 is a schematic cross-sectional view of a structure formed after forming a cap layer 322 in a functional layer 320 according to a fabrication method of an embodiment of the present application.

As shown in fig. 10, in one embodiment of the present application, the step of forming the functional layer 320 air gap layer further comprises: a cap layer 322 is formed at the end of the air gap layer 321 near the second side 102. Specifically, the cap layer 322 can be formed at an end portion of the air gap layer 321 near the second side 102 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The cap layer 322 may be a dielectric material, and an exemplary material for forming the cap layer 322 may include silicon oxide. Alternatively, the cap layer 322 may be made of the same material as that of the dielectric layer 210

In one embodiment of the present application, when the air gap layer 321 includes a first air gap layer and a second air gap layer, the cap layer 322 of the functional layer 320 also includes a first cap layer and a second cap layer corresponding to the first air gap layer and the second air gap layer, respectively. In one embodiment of the present application, the second cap layer may be made of the same material as the first cap layer.

In addition, the step of forming the cap layer 322 further includes: a chemical mechanical polishing process (Buffer CMP) such as a low polishing rate is performed on the substrate surface 112 so that the surface of the cap layer 322 on the 102 side is in the same plane as the substrate surface 112.

The provision of the capping layer at the end of the air gap layer remote from the stacked structure prevents a portion of the material in the subsequently formed conductive layer in contact with the channel layer from entering the air gap layer.

Step S6

Fig. 11 is a schematic cross-sectional view of a structure formed after forming a conductive layer 110 according to a method of manufacturing an embodiment of the present application. Fig. 12 is an enlarged top sectional view taken at a in fig. 11. Fig. 13-1 and 13-2 are enlarged top cross-sectional views at B in fig. 11, respectively, according to an embodiment of the present application.

As shown in fig. 11, step S6 forms a conductive layer on the second side, and the conductive layer connecting the channel layer may include, for example: forming a conductive layer 110 on the second side 102; performing planarization treatment on the surface of the conductive layer 110 away from the laminated structure 200; and annealing the conductive layer 110.

Specifically, in one embodiment of the present application, before forming the conductive layer 110 on the second side 102, the method for preparing the three-dimensional memory further includes: the oxide layer of the portions of the substrate surface 112 corresponding to the channel structure (functional layer 320 and channel layer 330) is removed by any suitable etching process, including any one or combination of a dry etching process and a wet etching process, to form recesses exposing the channel layer 330.

A conductive layer 110 covering the substrate surface 112 and connected to the exposed channel layer 330 may be formed on the second side 102 using a thin film deposition process, such as any one of Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), and Metal Organic Chemical Vapor Deposition (MOCVD), or any combination thereof.

In one embodiment of the present application, the conductive layer 110 may be a composite structure formed by a multiple thin film deposition process and other processes, for example, a composite structure formed by a semiconductor layer wrapping an insulating layer.

In another embodiment of the present application, the conductive layer 110 may also be a highly doped semiconductor layer formed on the second side 102 by any one or a combination of processes including, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, and metal organic chemical vapor deposition. The semiconductor layer 110 may be doped with any suitable N-type dopant, such as phosphorus (P), arsenic (Ar), or antimony (Sb), to contribute free electrons and increase the conductivity of the intrinsic semiconductor. Further, the conductive layer 110 may be a polysilicon layer doped with an N-type dopant (e.g., P, ar, or Sb).

In one embodiment of the present application, forming the conductive layer on the second side further comprises: the N-type semiconductor layer 110 is subjected to a chemical mechanical polishing process (Buffer CMP) with a low grinding rate, an excimer Laser annealing process (Laser Anneal) and the like, and the Buffer CMP and the Laser Anneal process can make crystal grains in the semiconductor layer 110 uniform and the layer thickness uniform and moderate, so that good electrical connection between the conductive layer 110 and the channel layer 330 is realized, and the electrical performance of the three-dimensional memory is improved.

By reforming the highly doped semiconductor layer on the side of the substrate away from the laminated structure to serve as a conductive layer for connecting the channel layer and performing chemical mechanical polishing (Buffer CMP) with a low grinding rate, excimer Laser annealing (Laser Anneal) and the like on the semiconductor layer, good electrical connection between the conductive layer and the channel layer is realized and the electrical performance of the three-dimensional memory is improved.

As shown in fig. 12, a is an enlarged schematic cross-sectional top view of a connecting portion between the conductive layer 110 and the channel layer 330 in the channel structure formed by the above process, and the channel layer 330 and the conductive layer 110 can be electrically connected well at a.

In one embodiment of the present application, as shown in fig. 11 and 13-1, point B is an enlarged top view cross-sectional schematic view of the first air gap layer 321 of the channel structure formed by the above process and the channel layer 330 corresponding to the first air gap layer 321. The functional layer includes a blocking layer 320-a, a charge trapping layer (not shown), and a tunneling layer 320-c, which are sequentially disposed, and the first air gap layer 321 can be formed by removing a portion of the charge trapping layer in the functional layer 320. Further, the charge trap layer may be formed by removing a charge trap layer damaged when the channel layer 330 is N-doped by a process such as ion implantation of IMP. Alternatively, the portion of the substrate including the charge trapping layer and the first stack layer may be removed. In addition, the first stack layer may include at least one source select gate layer. The first air gap layer 321 can ensure that a gate-induced-drain-leakage (GIDL) auxiliary body bias voltage generated when the three-dimensional memory performs an erase operation is not too high to break down a portion of the functional layer, thereby affecting the electrical performance of the three-dimensional memory. In the resulting three-dimensional memory structure, the functional layer 320 includes a charge trapping layer and a first air gap layer 321 disposed between the charge trapping layer and the conductive layer 110. In addition, the functional layer 320 further includes a first cap layer 322 disposed between the first air gap layer 321 and the conductive layer 110.

In another embodiment of the present application, as shown in fig. 11 and 13-2, B is an enlarged top cross-sectional view of the air gap layer 321 and the channel layer 330 corresponding to the air gap layer 321 in the channel structure formed by the above process. The functional layer includes a blocking layer 320-a, a charge trapping layer (not shown), and a tunneling layer (not shown) sequentially disposed, and the first air gap layer and the second air gap layer can be formed by removing the charge trapping layer and the tunneling layer respectively in the functional layer, and the first air gap layer and the second air gap layer together form the air gap layer 321 of the functional layer 320. Further, the charge trapping layer and the tunneling layer may be formed by removing a charge trapping layer and a tunneling layer that are damaged when the substrate is N-doped by a process such as ion implantation of IMP. The air gap layer 321 can ensure that a gate-induced-drain-leakage (GIDL) auxiliary body bias generated when the three-dimensional memory performs an erase operation is not too high to break down a portion of the functional layer, thereby affecting the electrical performance of the three-dimensional memory. In the resulting three-dimensional memory structure, the functional layer 320 includes an air gap layer 321 formed by a first air gap layer disposed between the conductive layer 110 and the charge trapping layer and a second air gap layer disposed between the conductive layer 110 and the tunneling layer. In addition, the functional layer 320 further includes a cap layer 322 formed by a first cap layer and a second cap layer, the first cap layer is disposed between the first air gap layer and the conductive layer 110, and the second cap layer is disposed between the second air gap layer and the conductive layer 110.

Fig. 14 is a schematic cross-sectional view of a structure formed after forming the support layer 160, the contact recess 142a and the contact recess 144a in the substrate according to a fabrication method of an embodiment of the present application. Fig. 15 is a cross-sectional view of a structure formed after forming spacers 142b and 144b in

contact recesses

142a and 144a, respectively, and source contact recess 132a in support layer 160, according to a fabrication method of an embodiment of the present application. Fig. 16 is a schematic cross-sectional view of a structure formed after forming an adhesive layer 170 'and a metal layer 180', respectively, according to a fabrication method of an embodiment of the present application. Figure 17 is a cross-sectional schematic view of a structure formed after forming contact 142, contact 144, and source contact 132 according to a fabrication method of one embodiment of the present application. Fig. 18 is a schematic cross-sectional view of a structure formed after forming a passivation layer 190 according to a fabrication method of an embodiment of the present application.

As shown in fig. 14 to 18, the method 1000 for manufacturing a three-dimensional memory further includes: the steps of forming support layer 160, providing source contact 132, and providing

contacts

142 and 144 in substrate 100.

Also included in the finally formed three-dimensional memory structure is source contact 132 that faces away from stack 200 and is in contact with conductive layer 110. Source contact 132 may include one or more conductive layers, such as a metal layer (e.g., such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al)) or an adhesion layer (e.g., titanium nitride (TiN)).

In addition, the three-dimensional memory includes

contacts

142 and 144. In one embodiment, one end of

contacts

142 and 144 are in contact with peripheral contact 171. According to some embodiments,

contacts

142 and 144 may be Through Silicon Contacts (TSCs) since substrate semiconductor layer 120 may be an N-well layer, such as a P-type silicon substrate.

Contacts

142 and 144 may each include one or more metal layers (e.g., tungsten (W), cobalt (Co), copper (Cu), aluminum (Al)) or adhesion layers (e.g., titanium nitride (TiN)). In addition,

contacts

142 and 144 also include spacer layers 142b and 144b (e.g., dielectric layers) to insulate

contacts

142 and 144 from conductive layer 110.

Specifically, in one embodiment according to the present application, as shown in fig. 14, the support layer 160 may be formed on the surface of the conductive layer 110 away from the substrate semiconductor layer 120 by a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof. Alternatively, the support layer 160 may be made of an insulating material such as an oxide, for example, silicon oxide. Further, a portion of the support layer 160 not in contact with the conductive layer 110 may also include a polysilicon layer or a silicon nitride layer. Further, portions of the support layer 160, the conductive layer 110, and the substrate semiconductor layer 120 may be removed by any suitable etching process (including any one or a combination of a dry etching process and a wet etching process) to expose the substrate well region connected to the peripheral contact 171, forming the

recesses

144a and 142a.

As shown in fig. 15, spacer layers 142b and 144b are formed in the

grooves

144a and 142a. The spacer layers 142b and 144b may be made of a dielectric material. The portion of the supporting layer 160 corresponding to the channel structure 300 may be removed by any suitable etching process (including any one or a combination of a dry etching process and a wet etching process) to form the groove 132a until a portion of the conductive layer 110 is exposed.

As shown in fig. 16, an adhesive layer 170' may be formed on the surfaces of the

grooves

144a and 142a, the groove 132a, and the support layer 160 away from the conductive layer 110 by a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof. Alternatively, the adhesion layer 170' may be made of titanium nitride (TiN).

The metal layer 180 'may be formed on the surface of the adhesive layer 170' remote from the support layer 160 by a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof. The metal layer 180' may be made of, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or the like.

The source contact 132 may be formed by filling the adhesive layer 170 'and the metal layer 180' in the groove 132 a.

As shown in fig. 17, portions of the adhesion layer 170 'and the metal layer 180' between the recess 1424a and the recess 144a (shown in fig. 16) may be removed by any suitable etching process (including any one or combination of a dry etching process and a wet etching process) to form the adhesion layer 170 and the metal layer 180, respectively.

Contacts

142 and 144 may be formed by removing the adhesion and metal layers between recess 1424a and recess 144 a.

As shown in fig. 18, a passivation layer 190 may be formed on a surface of the metal layer 180 away from the adhesion layer 170 by a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof. The passivation layer 190 may passivate and protect the three-dimensional memory. Portions of the contacts, such as contact 144, may be exposed beyond passivation layer 190 as part of the contact pads.

Referring again to fig. 18, another aspect of the present application also provides a three-dimensional memory. The three-dimensional memory can be prepared by any preparation method. The three-dimensional memory may include: conductive layer 110, stacked structure 200 (including dielectric layer 210 and gate layer 230), and channel structure 300. Channel structure 300 includes a channel hole 310, a functional layer 320, and a channel layer 330. The functional layer 320 includes a blocking layer, a charge trapping layer, and a tunneling layer sequentially disposed on an inner sidewall of the channel hole 310. The functional layer 320 includes a charge trapping layer and a first air gap layer 321 disposed between the charge trapping layer and the conductive layer 110.

Further, the functional layer 320 further includes a first cap layer 322, and the first cap layer 322 is disposed between the first air gap layer 321 and the conductive layer 110.

In addition, as an option, the functional layer 320 further includes a tunneling layer and a second air gap layer disposed between the tunneling layer and the conductive layer 110, wherein the second air gap layer and the first air gap layer together form the air gap layer 321 of the functional layer 320.

Further, the functional layer 320 further includes a second cap layer disposed between the second air gap and the conductive layer 110, and the first cap layer and the second cap layer share the cap layer 322 of the functional layer. Further, the second cap layer may be made of the same material as the first cap layer.

The cap layer 322 of the functional layer 320 may prevent a portion of the material in the conductive layer 110 that is in contact with the channel layer 330 from entering the air gap layer 321.

In one embodiment of the present application, the air gap layer 321 may be formed by removing a damaged charge trapping layer (or damaged charge trapping layer and tunneling layer) during a three-dimensional memory fabrication process, such as during high doping of the channel layer after removing a portion of the substrate.

Further, as an option, the stacked structure 200 may include a plurality of stacked layers, each stacked layer including a pair of dielectric layers and a gate layer, wherein a first stacked layer is closest to the conductive layer 110 in the plurality of stacked layers, and in an embodiment of the present application, the first stacked layer includes at least one source selection gate layer. The air gap layer 321 formed by removing the charge trapping layer or formed by removing the charge trapping layer and the tunneling layer may be located at a portion of the functional layer 320 corresponding to the first stack layer.

In addition, the conductive layer 110 of the three-dimensional memory may be a highly doped semiconductor layer. Alternatively, the conductive layer 110 may be a highly doped polysilicon layer.

Since the contents and structures involved in describing the fabrication method 1000 above may be fully or partially applicable to the three-dimensional memory described herein, descriptions related or similar thereto are not repeated.

According to the three-dimensional memory provided by the embodiment of the application, the channel layer can be led out from the back surface, a deep hole etching process is avoided, and the reliability and the electrical property of the three-dimensional memory are improved.

According to at least one embodiment of the present application, the functional layer of the three-dimensional memory provided by the present application has an air gap layer formed by removing a portion of the charge trapping layer or removing a portion of the charge trapping layer and a portion of the tunneling layer, respectively, and the air gap layer is located at a portion of the functional layer close to the conductive layer, so as to ensure stability of a gate-induced-drain-leakage (GIDL) auxiliary body bias voltage generated when the three-dimensional memory performs an erase operation (in the present application, "GIDL erase").

In addition, according to another embodiment of the present disclosure, the conductive layer (the conductive layer for connecting to the channel layer) of the three-dimensional memory provided in the present disclosure is a highly doped semiconductor layer, and further, the highly doped semiconductor layer has uniform and moderate layer thickness and grain distribution by performing processes such as a chemical mechanical polishing process (Buffer CMP) with a low grinding rate and an excimer Laser annealing process (Laser Anneal), and the like, so that good electrical connection between the conductive layer and the channel layer is achieved, and the electrical performance of the three-dimensional memory is improved.

Although exemplary methods and structures of fabricating a three-dimensional memory are described herein, it will be understood that one or more features may be omitted, substituted, or added from the structure of the three-dimensional memory. For example, various well regions may be formed in the substrate as desired. Furthermore, the materials of the various layers illustrated are merely exemplary.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A method of fabricating a three-dimensional memory, the method comprising:

forming a stack structure on a first side of a substrate, forming a channel structure through the stack structure and extending to the substrate, the channel structure comprising: the functional layer and the channel layer are sequentially formed on the inner wall of the channel hole, and the functional layer comprises a charge trapping layer;

removing a portion of the substrate from a second side of the substrate opposite the first side;

carrying out high doping on the exposed channel layer after part of the substrate is removed;

removing a portion of the charge trapping layer to form an air gap layer in a portion of the functional layer adjacent the second side;

forming a cap layer at an end of the air gap layer proximate the second side; and

and forming a conductive layer connected with the channel layer on the second side.

2. The method of claim 1, the functional layer further comprising a tunneling layer, wherein forming an air gap layer in a portion of the functional layer proximate the second side further comprises:

removing a portion of the tunneling layer corresponding to a portion of the charge trapping layer to form an air gap layer at a portion of the functional layer proximate to the second side.

3. The method of claim 2, the stacked structure comprising a plurality of stacked layers, each of the stacked layers comprising a pair of dielectric layers and a gate layer, wherein forming an air gap layer in a portion of the functional layer proximate to the second side comprises:

removing portions of the charge-trapping layer and the first stack layer or portions of the charge-trapping layer and the tunneling layer on the substrate and the first stack layer, respectively, to form the air gap layer, wherein the first stack layer is closest to the substrate among the plurality of stack layers.

4. The method of claim 3,

the first stack layer includes at least one source select gate layer.

5. The method of claim 1, wherein forming a conductive layer on the second side to connect to the channel layer comprises:

and forming a highly doped semiconductor layer connected to the channel layer at the second side.

6. The method of claim 5, wherein forming the highly doped semiconductor layer at the second side further comprises:

and carrying out an excimer laser annealing process on the highly doped semiconductor layer.

7. The method of claim 1, wherein prior to processing the substrate from a second side of the substrate opposite the first side, further comprising:

and connecting a peripheral circuit chip on the side of the laminated structure far away from the substrate.

8. The method of claim 1 or 7, wherein the substrate comprises a base plate, an etch stop layer and a substrate semiconductor layer arranged in sequence, and wherein removing a portion of the substrate comprises:

and removing the base plate, the etching stop layer and part of the channel structure to stop at the substrate semiconductor layer.

9. A three-dimensional memory, comprising:

a conductive layer; and

a stacked structure disposed on the conductive layer, the stacked structure including gate layers and dielectric layers alternately stacked; and

a channel structure penetrating the laminated structure and contacting the conductive layer, the channel structure including a channel hole, and a functional layer and a channel layer sequentially disposed on an inner sidewall of the channel hole,

wherein the functional layer comprises a charge trapping layer and a first air gap layer disposed between the charge trapping layer and the conductive layer.

10. The memory of claim 9, wherein the functional layer further comprises a first capping layer disposed between the first air gap layer and the conductive layer.

11. The memory of claim 9, wherein the functional layer further comprises a tunneling layer and a second air gap layer disposed between the tunneling layer and the conductive layer, wherein the second air gap layer and the first air gap layer together comprise an air gap layer of the functional layer.

12. The memory of claim 11, wherein the functional layer further comprises a second cap layer disposed between the second air gap and the conductive layer, and wherein the second cap layer is the same material as the first cap layer.

13. The memory of claim 11,

the first air gap layer or the air gap layer of the functional layer is located at a portion of the functional layer corresponding to a first stacked layer close to the conductive layer in the stacked-layer structure.

14. The memory of claim 13, wherein the first stack layer comprises at least one source select gate layer.

15. The memory of claim 9,

the conductive layer is a highly doped semiconductor layer.

16. The memory of claim 15,

the highly doped semiconductor layer is a highly doped polysilicon layer.