CN114300474A

CN114300474A - Three-dimensional memory and preparation method thereof, and electronic device and control method thereof

Info

Publication number: CN114300474A
Application number: CN202111652992.2A
Authority: CN
Inventors: 颜丙杰
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-12-30
Filing date: 2021-12-30
Publication date: 2022-04-08

Abstract

The application provides a three-dimensional memory, a preparation method, an electronic device and a control method. The preparation method comprises the following steps: forming a laminated structure on a substrate, and forming a channel structure which penetrates through the laminated structure and extends to the substrate in the laminated structure, wherein the channel structure comprises a channel hole, and a functional layer and a channel layer which are sequentially formed on the inner wall of the channel hole; removing the substrate and removing a portion of the functional layer extending to the substrate to expose the channel layer; and forming a first semiconductor layer and a second semiconductor layer connected to the exposed channel layer. The first semiconductor layer contains an impurity of a first conductivity type, and the second semiconductor layer contains an impurity of a second conductivity type opposite to the first conductivity type. The double-layer semiconductor layers with opposite polarities are connected with the channel layer, so that the double-array common source with equal potential and opposite polarities can be formed in the memory, the stability of the memory is effectively improved, the memory has double process windows when erasing, reading, writing and programming operations are executed, and the stability of a system is improved.

Description

Three-dimensional memory and preparation method thereof, and electronic device and control method thereof

Technical Field

The present invention relates to the field of semiconductor design and manufacturing, and more particularly, to a structure of a three-dimensional memory (3D NAND), a method of manufacturing a three-dimensional memory, an electronic device, and a method of controlling an electronic device.

Background

With the development of planar memories, the manufacturing process of semiconductors has made great progress. In recent years, however, the development of planar memories has met various challenges, such as physical limits, existing development technology limits, and storage electron density limits. In this context, to address the difficulties encountered with planar memories and to pursue lower production costs per unit cell, three-dimensional memory structures have emerged that can have a greater number of memory cells per memory die in a memory device.

In the NAND memory, one way to increase the memory density is by using a vertical memory array, i.e. a 3D NAND memory, and the conventional 3D NAND memory is mainly prepared by the following processes: firstly, a laminated structure formed by alternately overlapping sacrificial layers and inter-gate dielectric layers is formed, then the sacrificial layers are removed and filled with conductive materials to form a gate layer, and the 3D NAND memory is obtained. With the development of the manufacturing process, the number of stacked layers in the 3D NAND memory also needs to be increased significantly to achieve higher storage density, for example, from 32 layers to 64 layers, even 128 layers, etc. However, as the number of layers stacked in the 3D NAND memory increases, the stability thereof decreases, and the difficulty of the manufacturing process increases.

Therefore, it is an urgent problem to provide a simple and easy method for effectively improving the stability of a three-dimensional memory without affecting the structural performance of the three-dimensional memory.

Disclosure of Invention

The present application provides a three-dimensional memory and a method of fabricating the same that can at least partially solve the above-mentioned problems in the related art.

One aspect of the present application provides a method of fabricating a three-dimensional memory, the method including: forming a laminated structure on a substrate, and forming a channel structure which penetrates through the laminated structure and extends to the substrate in the laminated structure, wherein the channel structure comprises a channel hole, and a functional layer and a channel layer which are sequentially formed on the inner wall of the channel hole; removing the substrate and removing a portion of the functional layer extending into the substrate to expose the channel layer corresponding to the removed portion of the functional layer; and forming a first semiconductor layer and a second semiconductor layer connected to the exposed channel layer, wherein the first semiconductor layer contains an impurity of a first conductivity type; and the second semiconductor layer contains an impurity of a second conductivity type opposite to the first conductivity type.

In one embodiment of the present application, the channel layer is a layer of undoped semiconductor material; or the channel layer is a semiconductor material layer containing the first conductive type or the second conductive type impurities, wherein the impurity doping concentration of the channel layer is less than that of the first semiconductor layer; and an impurity doping concentration of the channel layer is smaller than an impurity doping concentration of the second semiconductor layer.

In one embodiment of the present application, the first semiconductor layer has an impurity doping concentration of 10¹⁵～10¹⁷cm^-3(ii) a And the impurity doping concentration of the second semiconductor layer is 10¹⁵～10¹⁷cm^-3。

In one embodiment of the present application, the channel layer has an impurity doping concentration less than or equal to 10¹³cm^-3。

In one embodiment of the present application, forming a first semiconductor layer and a second semiconductor layer connected to the exposed channel layer includes: forming the first semiconductor layer on a bottom surface of the stacked structure and an exposed surface of the channel layer; carrying out planarization treatment on the first semiconductor layer to expose part of the channel layer again; and forming the second semiconductor layer on a surface of the first semiconductor layer to connect the re-exposed portion of the channel layer.

In one embodiment of the present application, the first conductive type is a P type, and the second conductive type is an N type, or the first conductive type is an N type and the second conductive type is a P type.

In one embodiment of the present application, after forming a first semiconductor layer and a second semiconductor layer connected to the exposed channel layer, the method further comprises: and forming a connecting layer on one side departing from the laminated structure, wherein one end of the connecting layer comprises two connecting ends which are respectively used for electrically connecting the first semiconductor layer and the second semiconductor layer, and the other end of the connecting layer is used for connecting a signal control source of the memory.

In one embodiment of the present application, the connection ends of the connection layer are a first connection end and a second connection end, respectively, and the method further comprises: connecting the first connection end and the second connection end with a first portion of the first semiconductor layer and a second portion of the second semiconductor layer, respectively, wherein the first portion is a portion of the first semiconductor layer except for a portion corresponding to the channel structure; and the second portion is a portion of the second semiconductor layer corresponding to the channel structure.

In one embodiment of the present application, forming the connection layer includes: removing a portion of the second semiconductor layer corresponding to the first portion to expose the first portion; and forming a capping layer on a surface of the second semiconductor layer and a surface of the exposed first portion; removing portions of the cover layer corresponding to the first portion and the second portion, respectively, to form an opening; forming a connection layer electrically connecting the first portion and the second portion in the opening and a surface of the cover layer.

In one embodiment of the present application, forming the stacked structure on the substrate includes: forming a spacer layer on the substrate; and forming the laminated structure on the spacer layer, wherein the process of removing a portion of the functional layer extending into the substrate stops at the spacer layer.

In one embodiment of the present application, prior to removing the substrate, the method comprises: and connecting a peripheral circuit chip on the side of the laminated structure far away from the substrate.

Another aspect of the present application provides a three-dimensional memory, including: a first semiconductor layer containing an impurity of a first conductivity type; a second semiconductor layer formed on a first surface of the first semiconductor layer and including impurities of a second conductive type opposite to the first conductive type; a dielectric stack structure formed on a second surface of the first semiconductor layer opposite to the first surface, the dielectric stack structure including gate layers and insulating layers alternately stacked; and a channel structure extending through the dielectric stack structure and the first semiconductor layer, wherein a channel layer of the channel structure includes sidewalls and a bottom surface in the first semiconductor layer; the side wall is electrically connected with the first semiconductor layer; and the bottom surface is electrically connected with the second semiconductor layer.

In an embodiment of the present application, the memory further includes a connection layer, one end of the connection layer includes two connection ends, which are respectively used for connecting the first semiconductor layer and the second semiconductor layer, and the other end of the connection layer is used for connecting a signal control source of the memory.

In one embodiment of the present application, the connection ends of the connection layer are a first connection end and a second connection end, respectively, and the first connection end and the second connection end are connected to a first portion of the first semiconductor layer and a second portion of the second semiconductor layer, respectively, wherein the first portion is a portion of the first semiconductor layer except for a portion corresponding to the channel structure; and the second portion is a portion of the second semiconductor layer corresponding to the channel structure.

In one embodiment of the present application, the connection layer is a metal material layer or a metal silicide layer.

In one embodiment of the present application, the memory further includes a peripheral circuit chip disposed on a side of the dielectric stack structure away from the first semiconductor layer.

Yet another aspect of the present application provides an electronic device, comprising: a processor for writing data to and reading data from the memory, and a memory according to any of the further aspects of the present application.

A further aspect of the present application provides a control method of an electronic device, applying a first level or a second level to a signal control source of the memory to electrically conduct the first semiconductor layer or the second semiconductor layer with the channel layer when the memory is in a read state, a program state, or an erase state, wherein the first level is less than the second level.

In one embodiment of the present application, the first semiconductor layer contains the N-type impurity, the second semiconductor layer contains the P-type impurity, the first level is applied to a signal control source of the memory when the memory is in a read state or a program state, a resistance value of a connection portion of the first semiconductor layer and the channel structure becomes low, and a resistance value of a connection portion of the second semiconductor layer and the channel structure becomes high, so that the first semiconductor layer and the channel layer are electrically conducted.

In one embodiment of the present application, the first semiconductor layer contains the impurity of the N-type, the second semiconductor layer contains the impurity of the P-type, the second level is applied to the signal control source of the memory when the memory is in an erased state, a resistance value of a connection portion of the first semiconductor layer and the channel structure becomes high, and a resistance value of a connection portion of the second semiconductor layer and the channel structure becomes low, so that the second semiconductor layer is electrically conducted with the channel layer.

In one embodiment of the present application, the first semiconductor layer contains the P-type impurity, the second semiconductor layer contains the N-type impurity, the first level is applied to a signal control source of the memory when the memory is in a read state or a program state, a resistance value of a connection portion of the first semiconductor layer and the channel structure becomes high, and a resistance value of a connection portion of the second semiconductor layer and the channel structure becomes low, so that the second semiconductor layer and the channel layer are electrically conducted.

In one embodiment of the present application, the first semiconductor layer contains the P-type impurity, the second semiconductor layer contains the N-type impurity, the second level is applied to a signal control source of the memory when the memory is in an erased state, a resistance value of a connection portion of the first semiconductor layer and the channel structure becomes low, and a resistance value of a connection portion of the second semiconductor layer and the channel structure becomes high, so that the first semiconductor layer and the channel layer are electrically conducted.

According to the three-dimensional memory, the preparation method of the three-dimensional memory, the electronic device and the control method of the electronic device provided by at least one embodiment of the application, the double-layer semiconductor layers with opposite polarities are used for connecting the channel layers, so that the double-array common source with equal potential and opposite polarities can be formed in the memory, the stability of the memory is effectively improved, the memory has double process windows when erasing, reading, writing and programming operations are performed, and the stability of a memory system is improved.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:

FIG. 1 is a flow chart of a method of fabricating a three-dimensional memory according to one embodiment of the present application;

FIGS. 2-11 are schematic diagrams of a manufacturing process according to one embodiment of the present application; and

fig. 12 is a schematic cross-sectional view of a three-dimensional memory formed after connecting one end of a connection layer to a first semiconductor layer and a second semiconductor layer, respectively, according to a fabrication method of an embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that in this specification the expressions first, second, third etc. are only used to distinguish one feature from another, and do not indicate any limitation of features, in particular any order of precedence. Thus, the first semiconductor layer discussed in this application may also be referred to as the second semiconductor layer, and vice versa, without departing from the teachings of this application.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Further, in this application, when "connected" or "coupled" is used, it may mean either direct contact or indirect contact between the respective components, unless there is an explicit other limitation or can be inferred from the context.

Fig. 1 is a flow chart of a method 1000 of fabricating a three-dimensional memory according to one embodiment of the present application. As shown in fig. 1, the present application provides a method 1000 for manufacturing a three-dimensional memory, including:

and S1, forming a laminated structure on the substrate, and forming a channel structure penetrating the laminated structure and extending to the substrate, wherein the channel structure comprises a channel hole and a functional layer and a channel layer which are sequentially formed on the inner wall of the channel hole.

And S2, removing the substrate, and removing a portion of the functional layer extending into the substrate to expose a channel layer corresponding to the removed portion of the functional layer.

S3, forming a first semiconductor layer and a second semiconductor layer connected to the exposed channel layer, wherein the first semiconductor layer includes an impurity of a first conductive type, and the second semiconductor layer includes an impurity of a second conductive type opposite to the first conductive type.

The specific processes of the steps of the above-described manufacturing method 1000 will be described in detail with reference to fig. 2 to 12.

Step S1

Fig. 2 is a schematic cross-sectional view of a structure formed after a stacked structure 200 is formed on a substrate 100 according to a fabrication method of an embodiment of the present application. Fig. 3 is a schematic cross-sectional view of a structure formed after forming a trench hole 310 in the stacked-layer structure 200 according to a fabrication method of an embodiment of the present application. Fig. 4 is a schematic cross-sectional view of a structure formed after forming a channel structure 300 according to one embodiment of the present disclosure.

As shown in fig. 2 to 4, the step S1 forms a stacked structure on the substrate, and forms a channel structure penetrating therethrough and extending to the substrate in the stacked structure, and the channel structure including a channel hole and a functional layer and a channel layer sequentially formed on an inner wall of the channel hole may include, for example: the method includes preparing a substrate 100, forming a stacked structure 200 on the substrate 100, and forming a channel structure 300 in the stacked structure 200 to extend through and to the substrate 100, the channel structure 300 including a channel hole 310 and a functional layer 320 and a channel layer 330 sequentially formed on an inner wall of the channel hole 310.

Specifically, as shown in fig. 2, in some embodiments, the substrate 100 may be selected according to actual requirements of the device, the substrate 100 may include a silicon (Si) substrate, a Germanium (Ge) substrate, a silicon Germanium (SiGe) substrate, a SOI (Si1 icon-on-insulator 1 atom, a GOI (Germanium-on-insulator) substrate, etc., in other embodiments, the substrate 100 may further include a substrate of other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, silicon carbide, etc., and the substrate 100 may also be a composite structure, such as a silicon stack or a silicon Germanium stack, etc., as examples.

In some embodiments, the substrate 100 may also be a substrate after ion doping, and specifically, the substrate 100 may be a P-type doped substrate or an N-type doped substrate, which is not limited in this application.

After forming the substrate 100, the stacked structure 200 may be formed on the substrate 100 by one or more thin film deposition processes, which may include, but are not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof, which is not limited in this application.

In addition, in the method 1000 for manufacturing a three-dimensional memory provided by the present application, the substrate 100 is completely removed in the subsequent steps, so that a common substrate structure is generally adopted without fabricating other structures therein, such as well regions and the like, which not only saves the cost, but also reduces the process difficulty.

After forming the substrate 100, the stacked structure 200 may be formed on the substrate 100 by one or more thin film deposition processes, which may include, but are not limited to, CVD, PVD, ALD, or any combination thereof, which is not limited in this application.

The stack structure 200 may include a plurality of pairs of insulating layers 210 and gate sacrificial layers 220 alternately stacked on each other. For example, the stack structure 200 may include 64 pairs, 128 pairs, or more than 128 pairs of the insulating layer 210 and the gate sacrificial layer 220. In some embodiments, the insulating layer 210 and the gate sacrificial layer 220 may include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. Exemplary materials for forming the insulating layer 210 and the gate sacrificial layer 220 may include silicon oxide and silicon nitride, respectively. A silicon oxide layer may be used as the isolation stack layer and a silicon nitride layer may be used as the sacrificial stack layer. The sacrificial stack layer can then be etched away and replaced with a conductor layer comprising a conductive material.

The method of making the single laminate structure 200 is described above. In fact, as the storage requirement of the three-dimensional memory is increased, the storage stack is gradually increased. In order to break through the limitation of the conventional process, a stacked structure may also be formed by sequentially stacking a plurality of sub-stacked structures in the thickness direction of the stacked structure 200 using a dual-stack technique or a multi-stack technique, wherein each sub-stacked structure may include a plurality of insulating layers and gate sacrificial layers alternately stacked. The number of layers of each sub-stack may be the same or different. Since the matters and structures related to the process for preparing a single stacked structure described above may be fully or partially applied to the stacked structure formed by a plurality of sub-stacked structures described herein, the matters related or similar thereto will not be described in detail. However, it will be understood by those skilled in the art that the subsequent fabrication process may be performed on the basis of a multi-stack structure or a single-stack structure.

In addition, referring again to fig. 2, in one embodiment of the present application, before forming the stacked-layer structure 200 on the substrate 100, the spacer layer 102 may be formed on the substrate 100, the spacer layer 102 covers the surface of the substrate 100, and then the stacked-layer structure 200 may be formed on the spacer layer 102. The spacer layer 102 may act as a stop layer and the process of removing portions of the functional layer extending into the substrate in step S2 may stop at the spacer layer to protect the stacked structure 200 from damage during this process. Spacer layer 102 may be formed on substrate 100 by one or more thin film deposition processes, and spacer layer 102 may be made of a semiconductor material such as polysilicon.

As shown in fig. 3, after the stacked structure 200 is formed, a channel hole 310 may be formed in the stacked structure 200, and the channel hole 310 may penetrate the stacked structure 200 in a thickness direction of the stacked structure 200 and extend into the substrate 100.

The channel hole 310 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, may also be performed. The channel hole 310 may have a cylindrical or pillar shape penetrating the stacked structure 200 and extending to the substrate 100.

Specifically, in one embodiment of the present application, the channel hole 310 may be formed by first forming a mask layer (not shown) on a top surface of the stacked structure 200 away from the substrate 100, the mask layer may be made of a material such as silicon nitride or titanium nitride, the mask layer may expose a portion of the top surface of the stacked structure 200 for defining a position of the subsequent channel hole 310 on the top surface of the stacked structure 200, and then forming the channel hole 310 extending through the stacked structure 200 and into the substrate 100 by using an etching process such as reactive ion etching.

Further, after the stacked structure is formed by using the dual-stack technique or the multi-stack technique, the stacked structure 200 may include N sub-stacked structures, and correspondingly, the channel hole may also include N × M sub-channel holes, where each sub-stacked structure may include M sub-channel holes, where M ≧ 1, and N ≧ 2. Forming the channel hole in the stacked structure using the dual stack technique or the multi stack technique may include: forming a first sub-stack structure on one side of the substrate and forming M first sub-channel holes penetrating through the first sub-stack structure and extending into the substrate; continuing to form subsequent sub-laminated structures and sub-channel holes until an Nth sub-laminated structure and M sub-channel holes in the Nth sub-laminated structure are formed, and filling hole filling sacrificial layers into corresponding sub-channel holes in the N-1 sub-laminated structures except the Nth sub-laminated structure; and removing the hole filling sacrificial layer in the N-1 sub-laminated structures based on the M sub-channel holes of the Nth sub-laminated structure, so that the upper and lower adjacent sub-channel holes in the N sub-laminated structures are at least partially aligned with each other to obtain M channel holes.

As shown in fig. 4, after the channel hole 310 is formed, a channel structure 300 may be formed in the channel hole 310, which may specifically include, for example: forming a channel structure 300 including a functional layer 320 and a channel layer 330 in the channel hole 310, wherein the functional layer 320 includes a blocking layer (not shown), a charge trapping layer (not shown), and a tunneling layer (not shown) sequentially formed in the channel hole 310; and forming a trench plug (not shown) and a filling dielectric layer (not shown) in the trench hole 310.

In some embodiments, the trench structure 300 includes a trench hole 310 filled with a semiconductor layer and a composite dielectric layer. The functional layer 320 and the channel layer 330 may be formed in the channel hole 310 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

Specifically, the functional layer 320 may include a blocking layer that blocks the outflow of charges; a charge trapping layer formed on a surface of the blocking layer and capable of storing charges during operation of the three-dimensional memory; and a tunneling layer formed on a surface of the charge trapping layer. The barrier layer may include one or more layers, which may include one or more materials. Materials for the barrier layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, and the like. The charge trapping layer may include one or more layers, which may include one or more materials. Materials for the charge trapping layer may include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide band gap material, and the like. The tunneling layer may include one or more layers, which may include one or more materials. Materials for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, and the like.

In some embodiments, the functional layer 320 may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 320 may have a structure different from the ONO configuration. For example, the functional layer 320 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

In some embodiments, channel layer 330 can be used to transport desired charges (electrons or holes). According to an exemplary embodiment of the present application, the channel layer 330 may be formed on the surface of the tunneling layer through a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof.

In some embodiments, the channel layer 330 may be a semiconductor layer, which may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. Further, similar to the channel hole 310, the channel layer 330 also extends through the stacked-layer structure 200 and into the substrate 100.

Alternatively, the channel layer 330 may be a non-doped semiconductor material layer; alternatively, the channel layer 330 may be a low-doped semiconductor material layer, in other words, the channel layer 330 has an impurity doping concentration less than that of a subsequently formed first semiconductor layer; and the channel layer 330 has an impurity doping concentration less than that of a subsequently formed second semiconductor layer.

In one embodiment of the present application, the impurity doping concentration of the channel layer 330 may be less than or equal to 10¹³cm^-3。

The method 1000 for manufacturing a three-dimensional memory according to an embodiment of the present application further includes: a channel plug (not shown) is formed on the top of the channel hole 310 away from the substrate 100.

Specifically, the channel hole 310 may be filled with a filling dielectric layer. The filling dielectric layer can comprise an oxide dielectric layer, such as silicon oxide. Furthermore, in the filling process, a plurality of insulating gaps can be formed in the filling dielectric layer by controlling the channel filling process so as to relieve the structural stress. Then, a trench plug is formed in a portion of the filling dielectric layer located at the top of the channel hole 310. The channel plug may be made of the same material as the channel layer 330.

In some embodiments, after completing the fabrication of the channel structure 300, the method 1000 for fabricating a three-dimensional memory provided herein further includes: a gate 230 is formed.

In particular, in conjunction with fig. 2 and 4, a gate gap (not shown) may be formed with a certain spacing from the channel structure 300 by, for example, a dry etching process or a combination of dry and wet etching processes. The gate gap may extend through the stacked structure 200 and into the substrate 100 along the thickness direction of the stacked structure 200.

Thereafter, the gate gap may be used as a path for providing an etchant and a chemical precursor, and the gate sacrificial layer 220 in the stack structure 200 may be entirely removed by a process such as wet etching to form a sacrificial gap.

After forming the sacrificial gap, a gate layer 230 may be formed in the sacrificial gap using a thin film deposition process, such as CVD, PVD, ALD, or any combination thereof. The gate layer 230 may be made of a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide.

In addition, before forming the gate layer 230, the method 1000 for fabricating a three-dimensional memory according to an embodiment of the present application further includes forming a dielectric layer (not shown) on the inner walls of the sacrificial gap and on the inner walls (or inner sidewalls) of the gate gap by using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and the dielectric layer may be a high-k dielectric layer as an option. Further, an adhesion layer (e.g., a TiN layer of titanium nitride, not shown) may also be formed between the insulating layer 210 and the gate layer 230 or between the dielectric layer and the gate layer 230 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

After the gate layer 230 is formed, a gate gap structure (not shown) may be formed by filling the gate gap. Specifically, a gate gap structure may be formed by filling a dielectric layer in the gate gap using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and the dielectric layer may be formed by a semiconductor material such as polysilicon, or an oxide material such as silicon oxide.

In addition, after the gate sacrificial layer 220 in the stacked structure 200 shown in fig. 2 is entirely replaced by the gate layer 230, the stacked structure 200 is formed into the dielectric stacked structure 200' shown in fig. 4.

Fig. 5 is a cross-sectional view of a structure formed after a peripheral circuit chip 3000 is connected to one side of the dielectric stack 200' according to a fabrication method of an embodiment of the present invention.

As shown in fig. 5, according to some embodiments of the present application, after forming the gate layer 230, the method 1000 for fabricating a three-dimensional memory provided by the present application further includes: a peripheral circuit chip 3000 is connected to the side of the dielectric stack 200' remote from the substrate 100.

In addition, according to other embodiments of the present application, after the first semiconductor layer and the second semiconductor layer having opposite polarities and connected to the channel layer 330 (as shown in fig. 4) are formed, the peripheral circuit chip 3000 may be connected to the side of the dielectric stack 200' away from the substrate 100.

The peripheral circuitry may include one or more of page buffers, decoders (e.g., row and column decoders), drivers, charge pumps, current or voltage references, or any active or passive components (e.g., transistors, diodes, resistors, or capacitors) required in the circuitry. In some embodiments, the peripheral circuitry may be formed by CMOS technology, but is not limited thereto.

Alternatively, the three-dimensional memory may include an array chip (not shown) and a peripheral circuit chip 3000. The array chip includes a substrate 100 and a dielectric stack structure 200' formed on the substrate 100. The peripheral circuit chip 3000 includes a substrate (not shown) and a peripheral circuit (not shown) formed on the substrate.

Specifically, in one embodiment of the present application, conductive contacts (e.g., word line contacts or peripheral contacts, not shown) and conductive contacts (not shown) electrically connected to the conductive contacts may be formed in the dielectric stack structure 200' prior to connecting the peripheral circuit chip 3000. The peripheral circuit chip 3000 may be placed on the top surface of the dielectric stack 200' where the conductive contacts are provided. Then, an alignment step is performed and one surface of the peripheral circuit chip 3000 and the top surface of the dielectric stack structure 200' are bonded together by, for example, a bonding process.

The peripheral circuit chip 3000 and the bonding process can be performed by conventional processes, and are not described herein.

Step S2

Fig. 6 is a cross-sectional view of a structure formed after removing the substrate 100 (shown in fig. 5) according to a fabrication method of an embodiment of the present application. Fig. 7 is a schematic cross-sectional view of a structure formed after removing an exposed portion of the functional layer 320 (shown in fig. 6) according to a fabrication method of an embodiment of the present application.

As shown in fig. 5 and 7, the step S2 of removing the substrate and removing the portion of the functional layer extending into the substrate to expose the channel layer corresponding to the removed portion of the functional layer may include, for example: the substrate 100 is removed sequentially using, for example, a Mechanical Chemical polishing (CMP) process, a dry etching process, or a combination of dry and wet etching processes, and a portion of the functional layer 320 extending into the substrate 100 is removed continuously using, for example, the CMP process, the dry etching process, or the combination of dry and wet etching processes, thereby exposing the channel layer 330 corresponding to the removed portion of the functional layer 320. Specifically, fig. 6 is a schematic structural view after the structure of fig. 5 is turned over by 180 ° and the substrate 100 is removed. As shown in fig. 5 and 6, in one embodiment of the present application, the substrate 100 may be removed to expose a portion of the functional layer 320 extending into the substrate 100 (e.g., a bottom portion of the functional layer 320 extending into the substrate 100 and a portion of the sidewall connected to the bottom portion). In addition, in the case where the substrate 100 is covered with the spacer layer 102, the spacer layer 102 may also be exposed through the above steps.

In addition, the step of removing the substrate 100 may be performed by controlling the operation time and the operation rate of the above-described dry etching process, wet etching process, or CMP process.

In one embodiment of the present application, in conjunction with fig. 6 and 7, after removing the substrate 100, the exposed functional layer 320 may be further continuously removed to expose the channel layer 330 corresponding to the removed portion of the functional layer 320.

Alternatively, the exposed functional layer 320 may be removed by employing multiple times, such as a dry etching process or a combination of dry and wet etching processes. In other words, the exposed blocking layer, charge trapping layer, and tunneling layer of the functional layer 320 may be sequentially removed using multiple times, for example, a dry etching process or a combination of dry and wet etching processes, until a portion of the channel layer 330 is exposed. In the case where the substrate 100 is covered with the spacer layer 102, the spacer layer 102 may act as a stop layer for this step (which may be understood as a step of removing the exposed functional layer 320) to protect the stack structure 200 (or the dielectric stack structure 200') from damage during this process.

In some embodiments, the functional layer 320 including the blocking layer, the charge storage layer, and the tunneling layer may have an oxide-nitride-oxide (ONO) structure surrounding the channel layer 330. An ONO removal process may be performed that sequentially removes the exposed layers of the functional layer 320 until a portion of the channel layer 330 is exposed.

Step S3

Fig. 8 is a schematic cross-sectional view of a structure formed after forming a semiconductor layer 111 on one side of a dielectric stack structure 200' according to a fabrication method of an embodiment of the present application. Fig. 9 is a schematic cross-sectional view of a structure after planarization of the first semiconductor layer 111 and re-exposure of the channel layer 330 according to a fabrication method of an embodiment of the present application. Fig. 10 is a schematic cross-sectional view of a structure after forming a second semiconductor layer 112 on the planarized first semiconductor layer 111 to connect the re-exposed portion of the channel layer 330 according to a fabrication method of an embodiment of the present application.

As shown in fig. 8 to 11, step S3 forms a first semiconductor layer and a second semiconductor layer connected to the exposed channel layer, wherein the first semiconductor layer contains impurities of the first conductive type; and the second semiconductor layer containing impurities of a second conductivity type opposite to the first conductivity type may include, for example: forming a first semiconductor layer 111 on a bottom surface of the dielectric stack structure 200' and a surface of the exposed channel layer 330; performing planarization on the first semiconductor layer 111 to expose a portion of the channel layer 330 again; and forming a second semiconductor layer 112 on the surface of the first semiconductor layer 111, the second semiconductor layer 112 connecting the re-exposed portion of the channel layer 330.

Specifically, as shown in fig. 8, a first semiconductor layer 111 may be formed on the bottom surface of the dielectric stack structure 200' using a thin film deposition process, such as CVD, PVD, ALD, or any combination thereof, and the first semiconductor layer 111 may be connected to the exposed channel layer 330.

In the case where the substrate 100 is covered with the spacer layer 102, the spacer layer 102 may be removed and the bottom surface of the dielectric stack structure 200' may be exposed, for example, by a dry etching process or a combination of dry and wet etching processes. Thereafter, on the bottom surface of the exposed dielectric stack structure 200', a first semiconductor layer 111 connecting the exposed channel layer 330 is formed through a thin film deposition process, such as CVD, PVD, ALD, or any combination thereof.

In the case where the substrate 100 is covered with the spacer layer 102, alternatively, the spacer layer 102 may not be removed, and a semiconductor layer may be formed directly on the exposed surface of the spacer layer 102 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and may form the first semiconductor layer 111 connecting the exposed channel layer 330 together with the remaining spacer layer 102. The first semiconductor layer is directly formed on the surface of the spacing layer, so that the overall performance of the three-dimensional memory is ensured, the process steps for preparing the three-dimensional memory are simplified, and the production cost of the three-dimensional memory is reduced.

As shown in fig. 9, after the first semiconductor layer 111 is formed, the first semiconductor layer 111 may be planarized using, for example, a CMP process, a dry etching process, or a combination of dry and wet etching processes, to expose a portion of the channel layer 330 again, for example, the bottom surface 331 of the channel layer 330.

As shown in fig. 10, after exposing a portion of the channel layer 330 (e.g., the bottom surface 331 of the channel layer 330), the second semiconductor layer 112 may be formed on the surface of the first semiconductor layer 111 through a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, the second semiconductor layer 112 being used to connect to the re-exposed channel layer 330 (e.g., the bottom surface 331 of the channel layer 330). The thicknesses of the first semiconductor layer 111 and the second semiconductor layer 112 may be determined according to the final structure and the manufacturing process of the three-dimensional memory, which is not limited in the present application.

In one embodiment of the present application, the first semiconductor layer 111 and the second semiconductor layer 112 are semiconductor layers having opposite conductivity. Thus, as an alternative, impurity doping may be performed in the first semiconductor layer 111 and the second semiconductor layer 112 using a process such as chemical vapor phase doping. Chemical vapor doping refers to a process of doping an impurity element into a thin film through a vapor phase while depositing a Chemical Vapor Deposition (CVD) thin film. In other words, while the first semiconductor layer 111 and the second semiconductor layer 112 are formed by the chemical vapor deposition process, the first semiconductor layer 111 containing impurities of a first conductivity type and the second semiconductor layer 112 containing impurities of a second conductivity type, which are opposite to each other, may be formed by passing an appropriate amount of dopants (impurity sources).

Specifically, the conductivity type of the first semiconductor layer 111 may be a P type, and the conductivity type of the second semiconductor layer 112 may be an N type; alternatively, the conductivity type of the first semiconductor layer 111 may be N-type, and the conductivity type of the second semiconductor layer 112 may be P-type.

In addition, in one embodiment of the present application, the impurity doping concentration of the first semiconductor layer 111 may be 10¹⁵～10¹⁷cm^-3. The impurity doping concentration of the second semiconductor layer 112 may be 10¹⁵～10¹⁷cm^-3。

For example, in some embodiments, the first semiconductor layer 111 may be doped with any suitable dopant, such as an N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)), to contribute free electrons and increase the conductivity of the intrinsic semiconductor. Further, the first semiconductor layer 111 may be a polysilicon layer doped with an N-type dopant (e.g., P, Ar or Sb) with a doping atom concentration of about 10¹⁵～10¹⁷cm^-3. The second semiconductor layer 112 may be doped with any suitable dopant, such as a P-type dopant (e.g., boron (B), gallium (Ga), or indium (In)), to absorb free electrons and increase the conductivity of the intrinsic semiconductor. Further, the second semiconductor layer 112 may be a polysilicon layer doped with a P-type dopant (e.g., B, Ga or In) having a doping atom concentration of about 10¹⁵～10¹⁷cm^-3。

In some embodiments, the first semiconductor layer 111 may be doped with any suitable dopant, such as a P-type dopant (e.g., boron (B), gallium (Ga), or indium (In)), to absorb free electrons and increase the conductivity of the intrinsic semiconductor. Further, the first semiconductor layer 111 may be doped with P-type dopantA polysilicon layer of a dopant (e.g., B, Ga or In) having a doping atom concentration of about 10¹⁵～10¹⁷cm^-3. The second semiconductor layer 112 may be doped with any suitable dopant, such as an N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)), to contribute free electrons and increase the conductivity of the intrinsic semiconductor. Further, the second semiconductor layer 112 may be a polysilicon layer doped with an N-type dopant (e.g., P, Ar or Sb) with an atomic concentration of about 10¹⁵～10¹⁷cm^-3。

Alternatively, in one embodiment, the impurity doping concentrations of the first semiconductor layer 111 and the second semiconductor layer 112 may be equal.

The first semiconductor layer 111 and the second semiconductor layer 112 are used to form electrical connections with the channel layer 330 in the channel structure 300, for example, the first semiconductor layer 111 is electrically connected with the sidewall 332 of the channel layer 330, and the second semiconductor layer 112 is electrically connected with the bottom surface 331 of the channel layer 330. Thus, the first and second semiconductor layers 111, 112 having opposite conductivity polarities as described hereinabove may be formed as source conductive connections for a string of memory cells (including the channel structure 300). In addition, the first and second semiconductor layers 111 and 112 may also be similarly conductively connected to sources of other memory cell strings, and thus form an Array Common Source (ACS) of the three-dimensional memory.

Therefore, according to the method for manufacturing the three-dimensional memory provided by at least one embodiment of the present application, the double-layer semiconductor layers with opposite polarities are used to connect the channel layer, so that the common source of the double arrays with the same potential and opposite polarities can be formed in the memory, thereby effectively improving the stability of the memory, enabling the memory to have double process windows when erasing, reading, writing and programming operations are performed, and improving the stability of the memory system.

In addition, in the above-described fabrication process of the channel layer 330, the channel layer 330 is a non-doped semiconductor material layer or a semiconductor material layer including impurities of the first conductive type or the second conductive type. When the channel layer 330 is a semiconductor material layer containing conductive impurities, the impurity doping concentration of the channel layer 330 is less than that of the first semiconductor layer 111, and likewise, the impurity doping concentration of the channel layer 330 is also less than that of the second semiconductor layer 112.

Since the channel layer of the three-dimensional memory is a critical channel for carrier migration, the current conduction capability of the channel layer has an important influence on the erasing and reading performance of the three-dimensional memory. Thus, when the first semiconductor layer and the second semiconductor layer (which may be understood as a common source) connecting the channel layer are equipotentially connected to the signal control source of the three-dimensional memory, since the concentration of carriers in the channel layer is much smaller than the concentrations of carriers in the first semiconductor layer and the second semiconductor layer, carriers mainly of the first conductive type impurity or carriers mainly of the second conductive type impurity can be caused to flow toward the channel layer by inputting different levels to the signal control source, thereby enabling the mobility of carriers in the channel layer to be maintained at a high level at all times, and further improving the current-conducting capability of the channel layer.

Fig. 11 is a schematic cross-sectional view of the structure after removing a portion of the second semiconductor layer 112 to expose a portion of the first semiconductor layer 111 according to a fabrication method of an embodiment of the present application. Fig. 12 is a schematic cross-sectional view of a three-dimensional memory 2000 formed after one end of a connection layer 120 is connected to a first semiconductor layer 111 and a second semiconductor layer 112, respectively, according to a fabrication method of an embodiment of the present application.

Further, as shown in fig. 11 and 12, in some embodiments, the connection layer 120 may also be formed on a side facing away from the dielectric stack structure 200'. Specifically, a portion of the second semiconductor layer 112 corresponding to the first portion 01 of the first semiconductor layer 111 may be removed by, for example, a combination of photolithography and etching processes to expose the first portion 01; forming a capping layer (not shown) on the surface of the second semiconductor layer 112 and the exposed surface of the first portion 01 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof; removing portions of the cover layer corresponding to the first portion 01 of the first semiconductor layer 111 and the second portion 02 of the second semiconductor layer 112, respectively, by a combination of, for example, photolithography and etching processes to form openings (not shown); and forming a connection layer 120 electrically connecting the first portion 01 and the second portion 02 in the surface and the opening of the cover layer.

In one embodiment of the present application, the connection layer 120 may be a metal material layer or a metal silicide layer. The metal material for forming the connection layer 120 may be selected from tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), and the like, which is not limited in this application.

As shown in fig. 12, in one embodiment of the present application, the connection layer 120 may include two opposite ends, wherein one end of the connection layer 120 may include two connection ends, a first connection end 121 and a second connection end 122, the first connection end 121, and the other end of the connection layer 120 may be used to connect a signal control source (not shown) of the three-dimensional memory 2000.

The first connection terminal 121 of the connection layer 120 may be electrically connected to the first semiconductor layer 111, and the second connection terminal 122 of the connection layer 120 may be electrically connected to the second semiconductor layer 112. Specifically, the first connection terminal 121 of the connection layer 120 may be electrically connected to a first portion 01 (a portion circled by a dotted oval in the drawing) of the first semiconductor layer 111, wherein the first portion 01 may be a portion of the first semiconductor layer 111 other than a portion corresponding to the channel structure 300. The second connection terminal 122 of the connection layer 120 may be electrically connected to a second portion 02 (a portion circled by a dotted oval in the drawing) of the second semiconductor layer 112, wherein the second portion 02 may be a portion of the second semiconductor layer 112 corresponding to the channel structure 300. By disposing a portion (which can be understood as a first portion) of the first semiconductor layer electrically connected to the connection layer and a portion (which can be understood as a second portion) of the second semiconductor layer electrically connected to the connection layer in a staggered manner, generation of leakage current can be prevented, and electrical characteristics of the three-dimensional memory can be improved.

In addition, the dielectric stack structure 200' may include a stepped region and a memory array region, and a plurality of channel structures 300 may be formed in the memory array region and electrically connect the gate layer 230 with an external circuit through a word line contact located at the stepped region. Alternatively, the memory array region may be disposed at the center of the dielectric stack structure, and the step region may be disposed at one or more side edges of the dielectric stack structure. Alternatively, the step region may be disposed at the center of the dielectric stack structure, and the memory array region may be disposed at the edge of the dielectric stack structure, and the relative positions and specific structures of the step region and the memory array region are not limited in this application.

The first portion 01 of the first semiconductor layer 111 electrically connected to the connection layer 120 may be disposed in a portion of the connection layer 120 corresponding to the step region, or disposed in a portion of the connection layer 120 corresponding to between the adjacent channel structures 300, which is not limited in this application. Accordingly, the first portion 01 of the first semiconductor layer 111 and the second portion 02 of the second semiconductor layer 112 disposed at the above positions may be alternately connected to the connection layer 120, thereby preventing the generation of leakage current and improving the electrical characteristics of the three-dimensional memory.

Referring again to fig. 12, another aspect of the present application also provides a three-dimensional memory 2000. The three-dimensional memory 2000 may be fabricated using any of the fabrication methods described above. The three-dimensional memory 2000 may include: a first semiconductor layer 111, a second semiconductor layer 112, a dielectric stack 200 ', and a channel structure 300, wherein the first semiconductor layer 111 contains impurities of a first conductivity type, and the second semiconductor layer 112 is formed on a first surface of the first semiconductor layer 111 (which may be understood as a surface of the first semiconductor layer 111 away from the dielectric stack 200', not shown) and contains impurities of a second conductivity type opposite to the first conductivity type. The dielectric stack structure 200 'is formed on a second surface (not shown) of the first semiconductor layer 111 opposite to the first surface, and the dielectric stack structure 200' includes gate layers 230 and insulating layers 210 that are alternately stacked. The channel structure 300 penetrates the dielectric stack structure 200' and the first semiconductor layer 111, and includes a channel layer 330. The channel layer 330 includes a sidewall 332 (shown in fig. 10) and a bottom surface 331 (shown in fig. 10) in the first semiconductor layer 111, the sidewall 332 of the channel layer 330 being electrically connected to the first semiconductor layer 111; and the bottom surface 331 of the channel layer 330 is electrically connected to the second semiconductor layer 112.

The first semiconductor layer 111 and the second semiconductor layer 112 are used to form electrical connections with the channel layer 330 in the channel structure 300, for example, the first semiconductor layer 111 is electrically connected with the sidewall 332 of the channel layer 330, and the second semiconductor layer 112 is electrically connected with the bottom surface 331 of the channel layer 330. Thus, the first and second semiconductor layers 111, 112 having opposite conductivity polarities as described hereinabove may be formed as source conductive connections for a string of memory cells (including the channel structure 300). In addition, the first and second semiconductor layers 111 and 112 may also be similarly conductively connected to sources of other memory cell strings, and thus form an Array Common Source (ACS) of the three-dimensional memory 2000.

According to the three-dimensional memory provided by at least one embodiment of the application, the double-layer semiconductor layers with opposite polarities are used for connecting the channel layer, so that the double-array common source with the same potential and opposite polarities can be formed in the memory, the stability of the memory is effectively improved, the memory has double process windows when erasing, reading, writing and programming operations are performed, and the stability of a memory system is improved.

In addition, in one embodiment of the present application, the channel layer 330 is a non-doped semiconductor material layer; or the channel layer 330 is a semiconductor material layer containing impurities of the first conductive type or the second conductive type, wherein the impurity doping concentration of the channel layer 330 may be less than that of the first semiconductor layer 111, and the impurity doping concentration of the channel layer 330 is less than that of the second semiconductor layer 112.

Alternatively, the impurity doping concentration of the first semiconductor layer 111 may be 10¹⁵～10¹⁷cm^-3(ii) a The impurity doping concentration of the second semiconductor layer 112 may be 10¹⁵～10¹⁷cm^-3。

Alternatively, the impurity doping concentration of the channel layer 330 may be less than or equal to 10¹³cm^-3。

In addition, in one embodiment of the present application, the conductivity type of the first semiconductor layer 111 may be a P type, and the conductivity type of the second semiconductor layer 112 may be an N type; alternatively, the conductivity type of the first semiconductor layer 111 may be N-type, and the conductivity type of the second semiconductor layer 112 may be P-type.

In one embodiment of the present application, the connection layer 120 may include two opposite ends, wherein one end of the connection layer 120 may include two connection ends, a first connection end 121 and a second connection end 122, and the other end of the connection layer 120 may be used to connect a signal control source (not shown) of the three-dimensional memory 2000.

In addition, in one embodiment of the present application, the three-dimensional memory 2000 further includes a peripheral circuit chip 3000 disposed on a side of the dielectric stack 200' away from the substrate 100. The peripheral circuit chip 3000 may include a substrate (not shown) and peripheral circuits (not shown) formed on the substrate.

Referring again to fig. 12, yet another aspect of the present application also provides an electronic device (not shown) including a processor (not shown) for writing data into the memory and reading data from the memory, and a three-dimensional memory 2000.

In addition, a further aspect of the present application also provides a control method of the above electronic device, which can electrically conduct the first semiconductor layer 111 or the second semiconductor layer 112 with the channel layer 330 by applying a first level or a second level to a signal control source of the three-dimensional memory 2000 when the three-dimensional memory 2000 is in a read state, a program state, or an erase state, wherein the first level is less than the second level.

Specifically, in some embodiments of the present application, when the first semiconductor layer 111 includes an impurity of an N-type and the second semiconductor layer 112 includes an impurity of a P-type, the signal control source of the three-dimensional memory 2000 may be set to a first level, which is approximately 0 volt, when the three-dimensional memory 2000 is in a read state or a program state. Further, the first level may be applied to the first semiconductor layer 111 and the second semiconductor layer 112 through the connection layer 120. With the first level, the resistance value of the connection portion between the first semiconductor layer 111 and the channel layer 330 is low, and low resistance is formed, and the resistance value of the connection portion between the second semiconductor layer 112 and the channel layer 330 is high, and high resistance is formed. Therefore, the first semiconductor layer 111 is electrically conducted with the channel layer 330, and carriers mainly including the first conductive type impurity flow toward the channel layer 330, so that the mobility of the carriers in the channel layer 330 can be always maintained at a high level, thereby improving the current conduction capability of the channel layer.

In some embodiments of the present application, when the first semiconductor layer 111 includes an impurity of an N-type and the second semiconductor layer 112 includes an impurity of a P-type, the signal control source of the three-dimensional memory 2000 may be set to a second level, which is 16 to 20 volts, when the three-dimensional memory 2000 is in an erased state. Further, the second level may be applied to the first semiconductor layer 111 and the second semiconductor layer 112 through the connection layer 120. When the second level is applied, the resistance value of the connection portion between the first semiconductor layer 111 and the channel structure 330 becomes high, thereby forming high resistance, and the resistance value of the connection portion between the second semiconductor layer 112 and the channel layer 330 becomes low, thereby forming low resistance. The second semiconductor layer 112 is thus electrically conducted with the channel layer 330, and carriers mainly containing the second conductive type impurities flow toward the channel layer 330, so that the mobility of the carriers in the channel layer 330 can be always maintained at a high level, thereby improving the current-conducting capability of the channel layer.

In some embodiments of the present application, when the first semiconductor layer 111 includes an impurity of a P-type and the second semiconductor layer 112 includes an impurity of an N-type, the signal control source of the three-dimensional memory 2000 may be set to a first level, which is approximately 0 volt, when the three-dimensional memory 2000 is in a read state or a program state. Further, the first level may be applied to the first semiconductor layer 111 and the second semiconductor layer 112 through the connection layer 120. With the first level, the resistance value of the connection portion between the first semiconductor layer 111 and the channel layer 330 becomes high, resulting in high resistance, and the resistance value of the connection portion between the second semiconductor layer 112 and the channel layer 330 becomes low, resulting in low resistance. The second semiconductor layer 112 is thus electrically conducted with the channel layer 330, and carriers mainly containing the second conductive type impurities flow toward the channel layer 330, so that the mobility of the carriers in the channel layer 330 can be always maintained at a high level, thereby improving the current-conducting capability of the channel layer.

In some embodiments of the present application, when the first semiconductor layer 111 includes an impurity of a P-type and the second semiconductor layer 112 includes an impurity of an N-type, the signal control source of the three-dimensional memory 2000 may be set to a second level, which is 16 to 20 volts, when the three-dimensional memory 2000 is in an erased state. Further, the second level may be applied to the first semiconductor layer 111 and the second semiconductor layer 112 through the connection layer 120. With the second level, the resistance value of the connection portion between the first semiconductor layer 111 and the channel layer 330 is low, and low resistance is formed, and the resistance value of the connection portion between the second semiconductor layer 112 and the channel layer 330 is high, and high resistance is formed. Therefore, the first semiconductor layer 111 is electrically conducted with the channel layer 330, and carriers mainly including the first conductive type impurity flow toward the channel layer 330, so that the mobility of the carriers in the channel layer 330 can be always maintained at a high level, thereby improving the current conduction capability of the channel layer.

Therefore, according to the electronic device provided by at least one embodiment of the present application, the channel layer is connected by using the double-layer semiconductor layers with opposite polarities, so that the double-array common source with the same potential and opposite polarities can be formed in the memory, thereby effectively improving the stability of the memory, enabling the memory to have double process windows when performing erase, read, write and program operations, and improving the stability of the memory system.

Since the contents and structures referred to in the above description of the manufacturing method 1000 are fully or partially applicable to the three-dimensional memory and the electronic device described herein, the contents related or similar thereto will not be described in detail.

The above description is only a preferred embodiment of the present application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A method of fabricating a three-dimensional memory, the method comprising:

forming a laminated structure on a substrate, and forming a channel structure which penetrates through the laminated structure and extends to the substrate in the laminated structure, wherein the channel structure comprises a channel hole, and a functional layer and a channel layer which are sequentially formed on the inner wall of the channel hole;

removing the substrate and removing a portion of the functional layer extending into the substrate to expose the channel layer corresponding to the removed portion of the functional layer; and

forming a first semiconductor layer and a second semiconductor layer connected to the exposed channel layer,

wherein the first semiconductor layer contains an impurity of a first conductivity type; and

the second semiconductor layer includes an impurity of a second conductivity type opposite to the first conductivity type.

2. The method of claim 1,

the channel layer is a non-doped semiconductor material layer; or

The channel layer is a semiconductor material layer containing impurities of the first conductive type or the second conductive type,

wherein an impurity doping concentration of the channel layer is less than an impurity doping concentration of the first semiconductor layer; and an impurity doping concentration of the channel layer is smaller than an impurity doping concentration of the second semiconductor layer.

3. The method of claim 2,

the impurity doping concentration of the first semiconductor layer is 10¹⁵～10¹⁷cm^-3(ii) a And

the second semiconductor layer has an impurity doping concentration of 10¹⁵～10¹⁷cm^-3。

4. The method according to claim 2 or 3,

the channel layer has an impurity doping concentration of 10 or less¹³cm^-3。

5. The method of claim 1, wherein forming a first semiconductor layer and a second semiconductor layer connected to the exposed channel layer comprises:

forming the first semiconductor layer on a bottom surface of the stacked structure and an exposed surface of the channel layer;

carrying out planarization treatment on the first semiconductor layer to expose part of the channel layer again; and

and forming the second semiconductor layer on the surface of the first semiconductor layer to connect the re-exposed portion of the channel layer.

6. The method of claim 1,

the first conductive type is a P type, the second conductive type is an N type, or the first conductive type is an N type, and the second conductive type is a P type.

7. The method of claim 1, wherein after forming the first semiconductor layer and the second semiconductor layer in connection with the exposed channel layer, the method further comprises:

and forming a connecting layer on one side departing from the laminated structure, wherein one end of the connecting layer comprises two connecting ends which are respectively used for electrically connecting the first semiconductor layer and the second semiconductor layer, and the other end of the connecting layer is used for connecting a signal control source of the memory.

8. The method of claim 7, wherein the connection ends of the connection layer are first and second connection ends, respectively, the method further comprising:

connecting the first connection terminal and the second connection terminal with a first portion of the first semiconductor layer and a second portion of the second semiconductor layer, respectively,

wherein the first portion is a portion of the first semiconductor layer other than a portion corresponding to the channel structure; and

the second portion is a portion of the second semiconductor layer corresponding to the channel structure.

9. The method of claim 8, wherein forming the connection layer comprises:

removing a portion of the second semiconductor layer corresponding to the first portion to expose the first portion;

forming a covering layer on the surface of the second semiconductor layer and the exposed surface of the first part;

removing portions of the cover layer corresponding to the first portion and the second portion, respectively, to form an opening; and

forming a connection layer electrically connecting the first portion and the second portion in the opening and a surface of the cover layer.

10. The method of claim 1, wherein forming the stacked structure on the substrate comprises:

forming a spacer layer on the substrate; and

forming the stacked layer structure on the spacer layer,

wherein the process of removing a portion of the functional layer extending into the substrate stops at the spacer layer.

11. The method of claim 1, wherein prior to removing the substrate, the method comprises:

and connecting a peripheral circuit chip on the side of the laminated structure far away from the substrate.

12. A three-dimensional memory, comprising:

a first semiconductor layer containing an impurity of a first conductivity type;

a second semiconductor layer formed on a first surface of the first semiconductor layer and including impurities of a second conductive type opposite to the first conductive type;

a dielectric stack structure formed on a second surface of the first semiconductor layer opposite to the first surface, the dielectric stack structure including gate layers and insulating layers alternately stacked; and

a channel structure extending through the dielectric stack and the first semiconductor layer,

wherein the channel layer of the channel structure includes sidewalls and a bottom surface in the first semiconductor layer;

the side wall is electrically connected with the first semiconductor layer; and

the bottom surface is electrically connected to the second semiconductor layer.

13. The memory of claim 12,

the channel layer is a non-doped semiconductor material layer; or

wherein an impurity doping concentration of the channel layer is less than an impurity doping concentration of the first semiconductor layer; and

the channel layer has an impurity doping concentration less than an impurity doping concentration of the second semiconductor layer.

14. The memory of claim 13,

15. The memory according to claim 13 or 14,

16. The memory of claim 12,

17. The memory of claim 12,

the memory further comprises a connecting layer, one end of the connecting layer comprises two connecting ends which are respectively used for connecting the first semiconductor layer and the second semiconductor layer, and the other end of the connecting layer is used for connecting a signal control source of the memory.

18. The memory of claim 17, wherein the connection ends of the connection layer are a first connection end and a second connection end, respectively,

the first connection terminal and the second connection terminal are connected to a first portion of the first semiconductor layer and a second portion of the second semiconductor layer, respectively,

19. The memory of claim 17,

the connecting layer is a metal material layer or a metal silicide layer.

20. The memory of claim 12,

the memory also includes a peripheral circuit chip disposed on a side of the dielectric stack structure away from the first semiconductor layer.

21. An electronic device, characterized in that the electronic device comprises a memory according to any of claims 12-20 and a processor for writing data into the memory and reading data.

22. A method of controlling the electronic device according to claim 21, wherein a first level or a second level is applied to a signal control source of the memory device when the memory device is in a read state, a program state, or an erase state to electrically conduct the first semiconductor layer or the second semiconductor layer with the channel layer,

wherein the first level is less than the second level.

23. The method of claim 22, wherein the first semiconductor layer contains an impurity of the N-type, wherein the second semiconductor layer contains an impurity of the P-type,

when the memory is in a read state or a program state, the first level is applied to a signal control source of the memory, a resistance value of a connection portion of the first semiconductor layer and the channel structure becomes low, and a resistance value of a connection portion of the second semiconductor layer and the channel structure becomes high, so that the first semiconductor layer and the channel layer are electrically conducted.

24. The method of claim 22, wherein the first semiconductor layer contains an impurity of the N-type, wherein the second semiconductor layer contains an impurity of the P-type,

when the memory is in an erased state, the second level is applied to the signal control source of the memory, the resistance value of the connection portion of the first semiconductor layer and the channel structure becomes high, and the resistance value of the connection portion of the second semiconductor layer and the channel structure becomes low, so that the second semiconductor layer and the channel layer are electrically conducted.

25. The method of claim 22, wherein the first semiconductor layer contains an impurity of the P type, the second semiconductor layer contains an impurity of the N type,

when the memory is in a read state or a program state, the first level is applied to a signal control source of the memory, a resistance value of a connection portion of the first semiconductor layer and the channel structure becomes high, and a resistance value of a connection portion of the second semiconductor layer and the channel structure becomes low, so that the second semiconductor layer and the channel layer are electrically conducted.

26. The method of claim 22, wherein the first semiconductor layer contains an impurity of the P type, the second semiconductor layer contains an impurity of the N type,

when the memory is in an erased state, the second level is applied to a signal control source of the memory, a resistance value of a connection portion of the first semiconductor layer and the channel structure becomes low, and a resistance value of a connection portion of the second semiconductor layer and the channel structure becomes high, so that the first semiconductor layer and the channel layer are electrically conducted.