CN114551470A

CN114551470A - Three-dimensional memory and preparation method thereof

Info

Publication number: CN114551470A
Application number: CN202210155298.8A
Authority: CN
Inventors: 吴继君
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-02-21
Filing date: 2022-02-21
Publication date: 2022-05-27

Abstract

The application provides a three-dimensional memory and a preparation method thereof, wherein the preparation method comprises the following steps: forming a stacked structure on a substrate; forming a channel hole through the stacked structure and extending into the substrate; sequentially forming a functional layer, a channel layer, a first insulating layer and a conductive layer on an inner wall of the channel hole to form a channel structure, wherein the conductive layer and the channel layer are separated by the first insulating layer; removing at least a portion of the substrate and a portion of the channel structure to expose the channel layer and the conductive layer; and forming a semiconductor layer in contact with the exposed channel layer and conductive layer.

Description

Three-dimensional memory and preparation method thereof

Technical Field

The application relates to the technical field of three-dimensional memories, in particular to a preparation method of a three-dimensional memory and the three-dimensional memory.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, three-dimensional memories (i.e., 3D memory devices) have been developed. The three-dimensional memory includes a plurality of memory cells stacked in a vertical direction, can increase the integration level by a multiple on a unit area of a wafer, and can reduce the cost.

In a three-dimensional memory of a NAND structure, which includes a stack structure formed by alternately stacking gate layers and dielectric layers, and in which a channel hole is formed, a functional layer of a silicon oxide-silicon nitride-silicon oxide (ONO) structure and a polysilicon channel layer are typically deposited in the channel hole to form a memory cell string, the gate layer in the stack structure serves as a Word Line (WL) of each memory cell, and carriers in the polysilicon channel layer are controlled by applying a voltage to the word line, thereby implementing a stacked 3D NAND memory device.

The current 3D NAND memory devices have the following problems: when the silicon oxide-silicon nitride-silicon oxide structure between the gate layer and the channel layer is thick, the control capability of the gate to the channel layer is weakened, thereby affecting the performance of the memory cell.

Disclosure of Invention

One aspect of the present application provides a method of fabricating a three-dimensional memory, the method including: forming a stacked structure on a substrate; forming a channel hole through the stacked structure and extending into the substrate; sequentially forming a functional layer, a channel layer, a first insulating layer and a conductive layer on an inner wall of the channel hole to form a channel structure, wherein the conductive layer and the channel layer are separated by the first insulating layer; removing at least a portion of the substrate and a portion of the channel structure to expose the channel layer and the conductive layer; and forming a semiconductor layer in contact with the exposed channel layer and conductive layer.

In one embodiment, the semiconductor layer is formed of an N-type or P-type doped semiconductor material and is electrically connected to the conductive layer.

In one embodiment, the semiconductor layer forms a PN junction contact with the channel layer.

In one embodiment, a channel plug is formed on a top of the channel structure away from the substrate, the channel plug being electrically connected to the channel layer and electrically isolated from the conductive layer.

In one embodiment, a method of forming a channel plug on top of the channel structure remote from the substrate comprises: removing a top part of the conductive layer far away from the substrate to form a first groove; forming a second insulating layer covering the conductive layer in the first groove, wherein the second insulating layer is in contact with the first insulating layer; removing a top part of the second insulating layer far away from the substrate to form a second groove; forming a filling layer in the second groove, wherein the filling layer is in electric contact with the channel layer; and patterning the filling layer to form a channel plug.

In one embodiment, the stacked structure includes sacrificial layers and dielectric layers alternately stacked, and the method further includes: the sacrificial layer is replaced with a gate layer.

In one embodiment, the method further comprises: and connecting a peripheral circuit chip on the side, far away from the substrate, of the stacked structure in which the gate layers and the dielectric layers are alternately stacked.

In one embodiment, the stacked structure and the peripheral circuit chip are connected by hybrid bonding.

In one embodiment, forming the functional layer comprises: and a blocking layer, a charge trapping layer and a tunneling layer are sequentially formed on the inner wall of the channel hole.

Another aspect of the present application also provides a three-dimensional memory, including: a stacked structure including opposing first and second sides; a semiconductor layer on a first side of the stacked structure; the channel structure penetrates through the stacked structure and comprises a functional layer, a channel layer, a first insulating layer and a conducting layer which are sequentially arranged from outside to inside in the radial direction; wherein the channel layer and the conductive layer are in contact with the semiconductor layer.

In one embodiment, the semiconductor layer comprises an N-type or P-type doped semiconductor material and is electrically connected to the conductive layer.

In one embodiment, the location where the channel layer contacts the semiconductor layer includes a PN junction contact.

In one embodiment, the three-dimensional memory further comprises: a second insulating layer in contact with the first insulating layer and covering a top of the conductive layer away from the semiconductor layer.

In one embodiment, the three-dimensional memory further comprises: and the channel plug is arranged at the top of the channel structure far away from the semiconductor layer, is electrically connected with the channel layer and is isolated from the conducting layer through the second insulating layer.

In one embodiment, the three-dimensional memory further comprises: and the peripheral circuit chip is positioned on the second side of the stacked structure.

In one embodiment, a hybrid bonding structure is included between the peripheral circuit chip and the stacked structure.

In one embodiment, the functional layer includes a blocking layer, a charge trapping layer, and a tunneling layer disposed in this order from the outside to the inside in the radial direction.

According to the three-dimensional memory and the preparation method thereof provided by the application, the conducting layer is added on the side, away from the gate, of the channel layer to serve as a back gate, and the control capability of the gate on the channel layer can be improved.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1 is a cross-sectional schematic view of a related art three-dimensional memory 1 a.

Fig. 2 is an enlarged view at a in fig. 1.

Fig. 3 is a flowchart of a method of fabricating a three-dimensional memory according to an exemplary embodiment of the present application.

Fig. 4 to 6 and 8a to 11B are process diagrams of a method for manufacturing a three-dimensional memory according to an exemplary embodiment of the present application.

Fig. 7 is a partial flow chart of a method of fabricating a three-dimensional memory according to an exemplary embodiment of the present application.

Fig. 12 is an enlarged view at B in fig. 11A or 11B.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that in this specification, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not represent any limitation on the features. Thus, a first insulating layer discussed below may also be referred to as a second insulating layer, and vice versa, without departing from the teachings of the present application.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. Such as the thickness of the substrate, the channel structure, and the stack structure, etc., are not in proportion to actual production. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that the terms "comprises," "comprising," "has," "having," "includes" and/or "including," when used in this specification, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Moreover, when a statement such as "at least one of" appears after a list of listed features, the entirety of the listed features is modified rather than modifying individual elements in the list. Furthermore, the use of "may" mean "one or more embodiments of the application" when describing embodiments of the application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Fig. 1 is a cross-sectional schematic view of a related art three-dimensional memory 1 a. As shown in fig. 1, the three-dimensional memory 1a may include a substrate 10a and a stack structure 20a formed on the substrate 10a, wherein the stack structure 20a includes dielectric layers 201a and gate layers 202a alternately stacked on the substrate 10 a. The three-dimensional memory 1a may further include a channel structure 30a, and specifically, the channel structure 30a may include a functional layer 301a, a channel layer 302a, and an insulating layer 303a sequentially disposed from outside to inside in a radial direction of the channel structure 30 a.

Fig. 2 is an enlarged view at a in fig. 1. Fig. 2 is a cross-sectional view of a memory cell of a three-dimensional memory 1a, which includes a gate layer 202a, a functional layer 301a, and a channel layer 302 a. Illustratively, the gate layer 202a may be made of a metal material (e.g., tungsten), the functional layer 301a may include a silicon oxide-silicon nitride-silicon oxide (ONO) structure disposed sequentially from outside to inside along a radial direction of the channel structure 30a, and the channel layer 302a may be formed of polysilicon. When the silicon oxide-silicon nitride-silicon oxide structure between the gate layer 202a and the channel layer 302a is relatively thick, the carrier control capability of the gate layer 202a to the channel layer 302a is weakened, thereby affecting the performance of the memory cell.

Some embodiments of the present application provide a method of fabricating a three-dimensional memory. Fig. 3 shows a flow chart of a method 1000 for fabricating a three-dimensional memory according to an exemplary embodiment of the present application. As shown in fig. 3, the method includes:

s110: forming a stacked structure on a substrate;

s120: forming a channel hole penetrating through the laminated structure and extending into the substrate;

s130: sequentially forming a functional layer, a channel layer, a first insulating layer and a conductive layer on an inner wall of the channel hole to form a channel structure, wherein the conductive layer and the channel layer are separated by the first insulating layer;

s140: removing at least a portion of the substrate and a portion of the channel structure to expose the channel layer and the conductive layer; and

s150: a semiconductor layer is formed in contact with the exposed channel layer and the conductive layer.

In the process of the method for preparing the three-dimensional memory, a plurality of steps such as preparing a step structure of the three-dimensional memory, word line contacts and the like are also included. However, in order to highlight the key points of the invention, the above steps are not described in the present application, and those skilled in the art can determine the subsequent preparation method related to the three-dimensional memory after the preparation of the channel structure disclosed in the present application is completed according to their knowledge.

It should be understood that the steps shown in method 1000 are not exclusive and that other steps may be performed before, after, or between any of the steps shown. Further, some of the steps may be performed simultaneously or may be performed in an order different from that shown in fig. 3.

Fig. 4 to 6 and 8a to 11B are schematic cross-sectional views illustrating a method 1000 for manufacturing a three-dimensional memory according to an embodiment of the present disclosure. The above steps S110 to S150 are described in detail below with reference to fig. 4 to 6 and 8a to 11B.

And S110, forming a laminated structure on the substrate.

Fig. 4 is a schematic cross-sectional view of a structure formed after forming a stacked structure 20 on a substrate 10 according to a fabrication method of an embodiment of the present application.

As shown in fig. 4, the step S110 of forming a stacked structure on a substrate may, for example, include: a substrate 10 is prepared and a stacked structure 20 is formed on one side of the substrate 10.

Specifically, in one embodiment of the present application, the substrate 10 may be made of any suitable semiconductor material, such as a group iii-v compound, such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide.

In one embodiment of the present application, the substrate 10 may be, for example, a composite substrate for supporting device structures thereon. The substrate 10 is only schematically shown in fig. 4 as comprising a first substrate layer 101 and a second substrate layer 102, but the application is not limited thereto and the substrate 10 may be provided as comprising a plurality of layers of different materials, depending on requirements. In one embodiment of the present application, a plurality of layers made of different materials may be sequentially disposed through a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof to form the substrate 10.

The substrate 10 has opposite first and second sides. After forming the substrate 10, the stacked structure 20 may be formed on the first side of the substrate 10 by one or more thin film deposition processes, which may include, but are not limited to, CVD, PVD, ALD, or any combination thereof, which is not limited in this application. The stacked structure 20 may include a plurality of pairs of sacrificial layers 200 and dielectric layers 201 alternately stacked on each other. For example, the stacked structure 20 may include 64 pairs, 128 pairs, or more than 128 pairs of the sacrificial layer 200 and the dielectric layer 201. In some embodiments, the sacrificial layer 200 and the dielectric layer 201 may include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. Illustratively, a silicon nitride layer may be used for the material forming the sacrificial layer 200, and a silicon oxide layer may be used for the material forming the dielectric layer 201.

The method of making the individual stacked structures is described above. In fact, as the storage requirement of the three-dimensional memory is increased, the storage stack is gradually increased. In order to break through the limitation of the conventional process limit, a stacked structure may also be formed by sequentially stacking a plurality of sub-stacked structures in the thickness direction of the stacked structure using a dual-stack technique or a multi-stack technique, wherein each sub-stacked structure may include a plurality of sacrificial layers and dielectric layers alternately stacked. The number of layers of each sub-stack may be the same or different. Since the matters and structures related to the process for preparing a single stacked structure described above may be fully or partially applied to the stacked structure formed by a plurality of sub-stacked structures described herein, the matters related or similar thereto will not be described in detail. However, it will be understood by those skilled in the art that subsequent fabrication processes may be performed on the basis of a multi-stack structure or a single-stack structure.

And S120, forming a channel hole penetrating through the laminated structure and extending into the substrate.

Fig. 5 shows a schematic cross-sectional view of a structure formed after forming a trench hole 300 extending through the stacked structure 20 and into the substrate 10 according to a fabrication method of an embodiment of the present application.

The channel hole 300 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes. Other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, may also be performed. The channel hole 300 may have a cylindrical shape penetrating the stacked structure 20 and extending to the substrate 10. In one embodiment of the present application, the channel hole 300 penetrates the stacked structure 20 and extends into the substrate 10. The number and arrangement of the channel holes 300 may be set according to actual needs.

Specifically, in one embodiment of the present application, the channel hole 300 may be formed by first forming a mask layer (not shown) on a top surface of the stacked structure 20 away from the substrate 10, wherein the mask layer may be made of a material such as silicon nitride or titanium nitride, the mask layer may expose a portion of the top surface of the stacked structure 20 for defining a position of a subsequent channel hole 300 on the top surface of the stacked structure 20, and then forming the channel hole 300 extending through the stacked structure 20 and into the substrate 10 by using an etching process such as reactive ion etching.

S130, forming a functional layer, a channel layer, a first insulating layer and a conductive layer in sequence on an inner wall of the channel hole to form a trench A channel structure, wherein the first insulating layer connects the conductive layer and the trenchThe track layers are spaced apart.

In some embodiments of step S130, as shown in fig. 6, in this step, a functional layer 301, a channel layer 302, a first insulating layer 303, and a conductive layer 304 are sequentially formed on an inner wall of a channel hole 300 to form a channel structure 30, wherein the first insulating layer 303 separates the conductive layer 304 and the channel layer 302.

In one embodiment of the present application, the functional layer 301, the channel layer 302, the first insulating layer 303, and the conductive layer 304 may be sequentially formed on the inner wall of the channel hole 300 through a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

The functional layer 301 may include: a blocking layer (not shown) formed on an inner wall of the channel hole 300 to block outflow of charges, a charge trapping layer (not shown) formed on a surface of the blocking layer to store charges during operation of the three-dimensional memory, and a tunneling layer (not shown) formed on a surface of the charge trapping layer. The barrier layer may include one or more layers, which may include one or more materials. Materials for the barrier layer may include silicon oxide, silicon nitride, silicon oxynitride, high-K dielectric materials such as aluminum oxide or hafnium oxide, and the like. The charge trapping layer may include one or more layers, which may include one or more materials. Materials for the charge trapping layer may include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide band gap material, and the like. The tunneling layer may include one or more layers, which may include one or more materials. Materials for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, and the like.

In some embodiments, the functional layer 301 may comprise an oxide-nitride-oxide (ONO) structure. For example, the functional layer 301 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer. However, in some other embodiments, the functional layer 301 may have a structure different from the ONO configuration.

The channel layer 302 can be used to transport desired charges (electrons or holes). According to an exemplary embodiment of the present application, the channel layer 302 may be formed on the surface of the tunneling layer in the functional layer 301 through a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

In some embodiments, the channel layer 302 may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The material of the channel layer 302 includes, but is not limited to, P-type doped polysilicon. Similar to the channel hole 300, the channel layer 302 also extends through the stacked structure 20 and into the substrate 10.

In one embodiment of the present application, the functional layer 301, the channel layer 302, the first insulating layer 303 and the conductive layer 304 penetrate the stacked-layer structure 20 and extend into the substrate 10.

The first insulating layer 303 is mainly used to form electrical isolation between the channel layer 302 and the conductive layer 304. The first insulating layer 303 may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide, or the like.

In one embodiment of the present application, referring again to fig. 6, a conductive layer 304 may be formed on the surface of the first insulating layer 303 through a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and such that the conductive layer 304 fills the inner core of the channel hole 300, and the conductive layer 304 may be selected from a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide.

In one embodiment of the present application, the conductive layer 304 may be a single-layer solid structure made of a conductive material, and alternatively, in another embodiment of the present application, the conductive layer 304 may also be a composite structure including a conductive material layer and a filling dielectric layer (not shown), for example, the conductive material layer may be formed on the surface of the first insulating layer 303, the conductive material layer fills a part of the space of the channel hole 300, and then the filling dielectric layer is used to continuously fill the remaining space of the channel hole 300. Further, during the filling process, a plurality of insulating gaps (not shown) may be formed in the filling dielectric layer by controlling the trench filling process to relieve the structural stress.

Fig. 7 illustrates a partial flow diagram of a method 1000 for fabricating a three-dimensional memory according to an exemplary embodiment of the present application. As shown in fig. 7, the method 1000 for manufacturing a three-dimensional memory according to some embodiments of the present application further includes, after step S130:

s1301: forming a channel plug on the top of the channel structure far away from the substrate;

s1302: replacing the sacrificial layer with a gate layer; and

s1303: and connecting a peripheral circuit chip on the side, far away from the substrate, of the stacked structure in which the gate layers and the dielectric layers are alternately stacked.

It should be understood that the steps shown in fig. 7 are not exclusive and that other steps may be performed before, after, or between any of the steps shown. Further, some of the steps shown in fig. 7 may be performed simultaneously or may be performed in an order different from that shown in fig. 7.

The above steps S1301 to S1303 are described in detail below with reference to fig. 8a to 8g and fig. 9.

S1301: and forming a channel plug on the top of the channel structure far away from the substrate.

Fig. 8a to 8g are schematic cross-sectional views of a part of a channel structure 30 during formation of a channel plug 3021 on top of the channel structure away from the substrate 10 according to a method of manufacturing an embodiment of the present application. It should be understood that the steps shown in fig. 8a to 8g are not exclusive and that other steps may be performed before, after or in between any of the steps shown. Further, some of the steps may be performed simultaneously or may be performed in an order different from that shown in fig. 8a to 8 g.

The method for forming the channel plug 3021 is described in detail below with reference to fig. 8a to 8g, and may mainly include the following steps:

as shown in fig. 8a, a top portion of the conductive layer 304 remote from the substrate 10 is removed to form a first recess 3001. According to an exemplary embodiment of the present application, a portion of the conductive layer 304 away from the top of the substrate 10 may be removed and a first recess 3001 may be formed over the conductive layer 304 by performing one or more etching processes, for example, using a process including, for example, a dry etching process or a combination of dry and wet etching processes.

As shown in fig. 8b, a second insulating layer 303 'covering the conductive layer 304 is formed in the first groove 3001, and the second insulating layer 303' is in contact with the first insulating layer 303. According to an exemplary embodiment of the present application, the second insulating layer 303' may be formed within the first groove 3001 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Illustratively, the material of the second insulating layer 303' may be the same as the material of the first insulating layer 303.

Referring to fig. 8b, when forming the second insulating layer 303 ', the second insulating layer 303' will be formed simultaneously on the surface of the stacked-layer structure 20 away from the substrate 10. Next, as shown in fig. 8c, the second insulating layer 303' on the surface of the stacked structure 20 may be removed by using, for example, a Chemical Mechanical Polishing (CMP) process, a dry etching process, or a dry etching process, a wet etching process, or a combination thereof, and the surface of the stacked structure 20 is planarized.

As shown in fig. 8d, a portion of the second insulating layer 303' away from the top of the substrate 10 is removed to form a second recess 3002. A portion of the second insulating layer 303 'away from the top of the substrate 10 may be removed to form the second recess 3002 by performing one or more etching processes, for example, using a process including, for example, a dry etching process or a combination of dry and wet etching processes, while still leaving a portion of the second insulating layer 303' to cover the conductive layer 304.

As shown in fig. 8e, a filling layer 302 ' covering the second insulating layer 303 ' is formed in the second recess 3002, the filling layer 302 ' being in contact with the channel layer 302. According to an exemplary embodiment of the present application, the filling layer 302' may be formed within the second groove 3002 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Illustratively, the fill layer 302 'may be made of the same material as the channel layer 302, and the fill layer 302' and the channel layer 302 may form an electrical contact.

Referring to fig. 8e, when forming the filling layer 302 ', the filling layer 302' will be formed simultaneously on the surface of the stacked structure 20 away from the substrate 10. Then, as shown in fig. 8f, the filling layer 302' on the surface of the stacked structure 20 can be planarized by using, for example, a Chemical Mechanical Polishing (CMP) process.

As shown in fig. 8g, the filling layer 302' is processed by patterning to form a channel plug 3021. Specifically, in one embodiment of the present application, a mask layer (not shown) may be first formed on the surface of the filling layer 302 ' away from the substrate 10 to cover the filling layer 302 ' at the top of the channel structure 30 corresponding to the position away from the substrate 10, for defining the position of the subsequent channel plug 3021 on the surface of the filling layer 302 '. The exposed filling layer 302 'may then be removed by an etching process, such as reactive ion etching, so that a portion of the filling layer 302' as the channel plug 3021 remains.

S1302: the sacrificial layer is replaced with a gate layer.

As shown in fig. 9, in this step, the sacrificial layer 200 is replaced with a gate layer 202. In an exemplary embodiment, the sacrificial layer 200 may be removed through a gate line slit (not shown) to form a sacrificial gap (not shown). Then, a gate layer 202 is formed in the sacrificial gap through the gate line gap. It is understood that after step S1302, the stacked structure 20 in which the sacrificial layer 200 and the dielectric layer 201 are alternately stacked becomes the stacked structure 21 in which the gate layer 202 and the dielectric layer 201 are alternately stacked.

In one embodiment of the present application, the gate line slit may be used as a path for providing an etchant and a chemical precursor, and a process such as wet etching is used to remove all the sacrificial layer 200 in the stacked-layer structure 20 to form a sacrificial gap. Then, as shown in fig. 9, a gate layer 202 may be formed in the sacrificial gap using a thin film deposition process, such as CVD, PVD, ALD, or any combination thereof. The gate layer 202 may be made of a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide.

In addition, before forming the gate layer 202, the method 1000 for fabricating a three-dimensional memory according to an embodiment of the present application further includes forming a barrier layer (not shown) on an inner wall of the sacrificial gap by using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, wherein the barrier layer may be a high-k dielectric layer. Further, an adhesion layer (e.g., a titanium nitride TiN layer, not shown) may also be formed between the barrier layer and the gate layer 202 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

Step S1302 may also be performed before, after, or between any steps of other embodiments of the present application, which is not limited in this application.

S1303: connecting peripheral circuit on the side far from the substrate of the stacked structure with alternately stacked gate layers and dielectric layers And (6) a road chip.

Fig. 9 is a schematic cross-sectional view of the structure after connecting a peripheral circuit chip 40 on the side of the stacked structure 21 away from the substrate 10 according to the manufacturing method of one embodiment of the present application. Specifically, the stacked structure 21 has an interconnection structure (not shown) on a side thereof away from the substrate 10, and the peripheral circuit chip 40 may include a peripheral circuit chip body 401 and a rear-end manufactured interconnection structure 402, where the interconnection structure of the stacked structure 21 is exemplarily electrically connected to the rear-end manufactured interconnection structure 402, and the stacked structure 21 and the peripheral circuit chip 40 are exemplarily electrically connected by a hybrid bonding method, which is not described herein again.

As shown in fig. 9, the channel plug 3021 is electrically connected to the channel layer 302 on the one hand and also electrically connected to the peripheral circuit chip 40 on the other hand. The channel plug 3021 functions include, but are not limited to, leading out the channel layer 302 to the surface of the stacked structure 21, and increasing a process window for electrical connection of the channel layer 302 to the peripheral circuit chip 40. In addition, the channel plug 3021 may also function as a portion of the drain of the corresponding memory string.

The peripheral circuit chips 40 may include one or more of page buffers, decoders (e.g., row and column decoders), drivers, charge pumps, current or voltage references, or any active or passive components (e.g., transistors, diodes, resistors, or capacitors) required in the circuit. In some embodiments, the peripheral circuit chip 40 may be formed by a CMOS technology, but is not limited thereto.

Those skilled in the art can understand that before the step S1303, a plurality of steps such as preparing a step structure of a three-dimensional memory, a word line contact, and the like can be performed, and the preparation can be performed according to actual situations, which is not described herein again.

Returning to fig. 3, the method 1000 of manufacturing a three-dimensional memory according to some embodiments of the present application further includes steps S140 and S150.

S140, removing at least a portion of the substrate and a portion of the channel structure to expose the channel layer and the conductive layer.

As shown in fig. 10A and 10B, at least a portion of the substrate 10 and a portion of the channel structure 30 are removed in step S140 to expose the channel layer 302 and the conductive layer 304. Fig. 10A is a schematic cross-sectional view of a structure formed after removing all of substrate 10 and portions of channel structure 30 extending into substrate 10 according to a fabrication method of one embodiment of the present application. Figure 10B is a cross-sectional schematic view of a structure formed after removing a portion of substrate 10 and a portion of channel structure 30 according to a fabrication method of one embodiment of the present application. Fig. 10A and 10B merely exemplarily show that in step S140, at least a portion of the substrate 10 and a portion of the channel structure 30 may be removed to expose the channel layer 302 and the conductive layer 304.

Referring to fig. 10A and 10B, at least a portion of the substrate 10 and a portion of the channel structure 30 extending into the substrate 10 may be removed using, for example, a chemical mechanical polishing process, a dry etching process, or a dry, wet etching process, or a combination thereof, to expose the channel layer 302 and the conductive layer 304 in the channel structure 30.

In one embodiment of the present application, in step S140, at least a portion of the substrate 10 may be removed by using a dry etching process or a combination of dry and wet etching processes to expose the channel structure 30, and then the exposed functional layer 301, the channel layer 302, the first insulating layer 303 and the conductive layer 304 may be sequentially removed by using a plurality of times, for example, a dry etching process or a combination of dry and wet etching processes.

In some embodiments, the functional layer 301 including the blocking layer (not shown), the charge storage layer (not shown), and the tunneling layer (not shown) may have an oxide-nitride-oxide (ONO) structure surrounding the channel layer 302. An ONO removal process may be performed that sequentially removes the exposed layers of the functional layer 301 until a portion of the channel layer 302 is exposed.

In one embodiment of the present application, a chemical mechanical polishing process may also be used to remove at least a portion of the substrate 10 and a portion of the channel structure 30.

And S150, forming a semiconductor layer in contact with the exposed channel layer and the conductive layer.

Fig. 11A and 11B are schematic cross-sectional views of structures formed after forming a semiconductor layer 50 in contact with an exposed channel layer 302 and conductive layer 304 according to a fabrication method of one embodiment of the present application. It is to be understood that fig. 11A is a view in which the semiconductor layer 50 is prepared on the basis of fig. 10A, and fig. 11B is a view in which the semiconductor layer 50 is prepared on the basis of fig. 10B, with the difference in whether or not a part of the substrate 10 remains.

In one embodiment of the present application, the functional layer 301, the channel layer 302, and the first insulating layer 303 are all in contact with the semiconductor layer 50.

Specifically, in one embodiment of the present application, in order to achieve good and stable electrical connection between the channel layer 302 and the semiconductor layer 50 and improve the electrical performance of the three-dimensional memory, the exposed channel layer 302 may be heavily doped after the step of removing at least a portion of the substrate 10 and a portion of the functional layer 301 in step S140. The exposed channel layer 302 may be doped, for example, N-type by a process such as ion implantation of IMP. The N-type doping may include any suitable N-type dopant, such as phosphorus (P), arsenic (Ar), or antimony (Sb), for example, to contribute free electrons and increase the conductivity of the intrinsic semiconductor.

Further, referring to fig. 11A and 11B, the semiconductor layer 50 connected to the exposed channel layer 302 and the conductive layer 304 may be formed using a thin film deposition process, for example, any one of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), and Metal Organic Chemical Vapor Deposition (MOCVD), or any combination thereof.

In one embodiment of the present application, the semiconductor layer 50 may be a composite structure formed by a multiple thin film deposition process and other processes, for example, a composite structure formed by wrapping an insulating layer with a semiconductor layer.

In another embodiment of the present application, the semiconductor layer 50 may also be a doped semiconductor layer formed on the stacked structure 21 by any one or a combination of processes including, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, and metal organic chemical vapor deposition. Semiconductor layer 50 may be doped with any suitable N-type dopant, such as phosphorus (P), arsenic (Ar), or antimony (Sb), to contribute free electrons and increase the conductivity of the intrinsic semiconductor. Further, the semiconductor layer 50 may be a polysilicon layer doped with N-type dopants (e.g., P, Ar or Sb).

In an exemplary embodiment, the semiconductor layer 50 may be made of any suitable semiconductor material, for example, a iii-v compound such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide. A partial region of semiconductor layer 50 may also form a well region formed by doping N-type or P-type dopants via an ion implantation or diffusion process. The dopant may include any one or combination of phosphorus (P), arsenic (As), and antimony (Sb).

In some embodiments of the present application, the well regions may be prepared by selecting the same dopant or different dopants, and further, the doping concentration of the well regions may be the same or different, which is not limited in the present application.

In some embodiments of the present application, the channel layer 302 may form a PN junction contact where the semiconductor layer 50 contacts, and illustratively, the channel layer 302 may be P-type doped polysilicon, and a portion of the semiconductor layer 50 contacting the channel layer 302 may form a well region formed by N-type dopant doping through an ion implantation or diffusion process. Alternatively, the channel layer 302 may also be N-type doped polysilicon, and a portion of the semiconductor layer 50 in contact with the channel layer 302 may form a well region doped with a P-type dopant through an ion implantation or diffusion process. The above is merely an exemplary description, and the present application does not limit the manner in which the PN junction contact is formed at the position where the channel layer 302 contacts the semiconductor layer 50.

In some embodiments of the present application, conductive layer 304 makes electrical contact with semiconductor layer 50. The conductive layer 304 may be made of a conductive material, such as any one or combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide. The semiconductor layer 50 may be made of any suitable semiconductor material, for example, a iii-v compound such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide. The regions of semiconductor layer 50 in contact with conductive layer 304 may also form well regions doped with N-type or P-type dopants, which may include any one or combination of phosphorus (P), arsenic (As), and antimony (Sb), via an ion implantation or diffusion process. Alternatively, in some embodiments of the present application, the conductive layer 304 may be formed of a conductive material, for example, a metal material such as tungsten (W), cobalt (Co), copper (Cu), or aluminum (Al), and may form an ohmic contact with the semiconductor layer 50. It will be appreciated by those skilled in the art that a barrier layer is formed when a semiconductor is in contact with a metal, but when the semiconductor doping concentration is high, electrons can tunnel through the barrier, thereby forming a low resistance ohmic contact.

Fig. 12 is an enlarged view at B in fig. 11A or 11B. Fig. 12 is a cross-sectional view illustrating a structure of a memory cell of a three-dimensional memory according to an exemplary embodiment of the present application, which includes a gate layer 202, a functional layer 301, a channel layer 302, a first insulating layer 303, and a conductive layer 304. Illustratively, the gate layer 202 may be a metal material (e.g., tungsten), the functional layer 301 may include a silicon oxide-silicon nitride-silicon oxide structure (ONO) disposed in a radial sequence from the outside to the inside, and the channel layer 302 may be polysilicon.

As shown in fig. 12, the Gate layer 202 serves as a Gate (Gate) of the memory cell, one end of the channel layer 302 connected to the semiconductor layer 50 serves as a Source (Source), and the other end of the channel layer 302 serves as a Drain (Drain), and the three-dimensional memory operates on the principle that a voltage is applied to the Gate to control carriers in the channel layer 302, thereby realizing the basic function of the memory cell. In the three-dimensional memory 1A shown in fig. 1 and fig. 2, when the functional layer 301A is relatively thick, the control capability of the gate layer 202a on carriers of the channel layer 302a is weakened, but in the method for manufacturing the three-dimensional memory provided by the present application, as shown in fig. 11A or fig. 11B, by adding the conductive layer 304 on the side of the channel layer 302 away from the gate layer 202, the conductive layer 304 is in electrical contact with the semiconductor layer 50, so that when a voltage bias is applied through the semiconductor layer 50 as a common source line, the conductive layer 304 and the semiconductor layer 50 are equipotential, which is equivalent to extending the semiconductor layer 50 to the inner side of the channel structure 30, which is beneficial to enhancing the control capability of the gate layer 202 on carriers of the channel layer 302, thereby improving the performance of the three-dimensional memory.

Another aspect of the present application further provides a three-dimensional memory, which can be prepared by any one of the above preparation methods. Referring again to fig. 11A or 11B, the three-dimensional memory includes: a stack structure 21, a semiconductor layer 50, and a plurality of channel structures 30. Only one channel structure 30 is exemplarily shown in fig. 11A and 11B.

Specifically, stacked structure 21 has a first side (not shown) and a second side (not shown) opposite, with semiconductor layer 50 located on the first side of stacked structure 21. The stack structure 21 includes dielectric layers 201 and gate layers 202 alternately stacked. The plurality of channel structures 30 penetrate the stacked structure 21 and include a functional layer 301, a channel layer 302, a first insulating layer 303, and a conductive layer 304, which are sequentially disposed from the outside to the inside in a radial direction of the channel structures 30. Wherein the first insulating layer 303 separates the conductive layer 304 from the channel layer 302, the channel layer 304 and the conductive layer 304 being in contact with the semiconductor layer 50.

In some embodiments of the present application, the three-dimensional memory may further include a peripheral circuit chip 40 located at the second side of the stacked structure 21. The stacked structure 21 has an interconnection structure (not shown) on a side thereof away from the semiconductor layer 50, and the peripheral circuit chip 40 may include a peripheral circuit chip body 401 and a back-end interconnection structure 402, and illustratively, a hybrid bonding structure (not shown) is included between the peripheral circuit chip 40 and the stacked structure 21, that is, the interconnection structure of the stacked structure 21 and the back-end interconnection structure 402 are connected by hybrid bonding.

The three-dimensional memory further includes: a second insulating layer 303' disposed on top of the conductive layer 304 away from the semiconductor layer 50 and a channel plug 3021 disposed on top of the channel structure 30 away from the semiconductor layer 50. The second insulating layer 303' isolates the conductive layer 304 from the channel plug 3021. Wherein the first insulating layer 303 and the second insulating layer 303 'are in contact, and in some embodiments of the present application, the materials of the first insulating layer 303 and the second insulating layer 303' may be the same.

In some embodiments of the present application, the channel plug 3021 is electrically connected to the channel layer 302. The channel plug 3021 and the channel layer 302 may have the same material.

In some embodiments of the present application, semiconductor layer 50 comprises an N-type or P-type doped semiconductor material and is electrically connected to conductive layer 304.

In some embodiments of the present application, the location where the channel layer 302 contacts the semiconductor layer 50 includes a PN junction contact.

In one embodiment of the present application, the semiconductor layer 50 may be a composite structure formed by a multiple thin film deposition process and other processes, for example, a composite structure formed by wrapping an insulating layer with a semiconductor layer. The material of the semiconductor layer 50 is not described in detail.

In one embodiment of the present application, the three-dimensional memory may include the substrate 10, as shown in fig. 11B, or may not include the substrate 10, as shown in fig. 11A. The material of substrate 10 may be selected from any suitable semiconductor material for supporting device structures thereon. The material of the substrate 10 is not described in detail.

In some embodiments of the present application, the channel plug 3021 is electrically connected to the peripheral circuit chip 40. The channel plug 3021 functions include, but are not limited to, leading out the channel layer 302 to the surface of the stacked structure 21, and increasing a process window for electrical connection of the channel layer 302 to the peripheral circuit chip 40. In addition, the channel plug 3021 may also function as a portion of the drain of the corresponding memory string.

In some embodiments of the present application, the functional layer 301 may include: a blocking layer (not shown) formed on an inner wall of the channel hole 300 to block outflow of charges, a charge trapping layer (not shown) formed on a surface of the blocking layer to store charges during operation of the three-dimensional memory, and a tunneling layer (not shown) formed on a surface of the charge trapping layer.

According to the three-dimensional memory, the conducting layer is added on the side, far away from the gate layer, of the channel layer to serve as the back gate, so that when the semiconductor layer serves as a common source line to apply voltage bias, the conducting layer and the semiconductor layer are in the same potential, namely the semiconductor layer extends to the inner side of the channel structure, the control capacity of the gate layer on current carriers of the channel layer is enhanced, and the performance of the three-dimensional memory is improved.

Since the contents and structures involved in describing the fabrication method 1000 above may be fully or partially applicable to the three-dimensional memory described herein, descriptions related or similar thereto are not repeated.

Although exemplary methods and structures of fabricating a three-dimensional memory are described herein, it will be understood that one or more features may be omitted, substituted, or added from the structure of the three-dimensional memory. For example, various well regions may be formed in the substrate as desired. Furthermore, the materials of the various layers illustrated are merely exemplary.

The above description is meant as an illustration of preferred embodiments of the application and of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea described above. For example, the above features and (but not limited to) features having similar functions in this application are mutually replaced to form the technical solution.

Claims

1. A method of fabricating a three-dimensional memory, the method comprising:

forming a stacked structure on a substrate;

forming a channel hole through the stacked structure and extending into the substrate;

sequentially forming a functional layer, a channel layer, a first insulating layer and a conductive layer on an inner wall of the channel hole to form a channel structure, wherein the conductive layer and the channel layer are separated by the first insulating layer;

removing at least a portion of the substrate and a portion of the channel structure to expose the channel layer and the conductive layer; and

forming a semiconductor layer in contact with the exposed channel layer and conductive layer.

2. The method of claim 1, wherein the semiconductor layer is formed of an N-type or P-type doped semiconductor material and is electrically connected to the conductive layer.

3. The method of claim 1, wherein the semiconductor layer forms a PN junction contact with the channel layer.

4. The method of claim 1, wherein the method further comprises:

forming a channel plug on a top of the channel structure away from the substrate, the channel plug being electrically connected to the channel layer and electrically isolated from the conductive layer.

5. The method of claim 4, wherein forming a channel plug on top of the channel structure away from the substrate comprises:

removing a top part of the conductive layer far away from the substrate to form a first groove;

forming a second insulating layer covering the conductive layer in the first groove, wherein the second insulating layer is in contact with the first insulating layer;

removing a top part of the second insulating layer far away from the substrate to form a second groove;

forming a filling layer in the second groove, wherein the filling layer is in electric contact with the channel layer; and

and patterning the filling layer to form a channel plug.

6. The method of claim 1, wherein the stacked structure comprises alternately stacked sacrificial layers and dielectric layers, the method further comprising:

the sacrificial layer is replaced with a gate layer.

7. The method of claim 6, wherein the method further comprises:

and connecting a peripheral circuit chip on the side, far away from the substrate, of the stacked structure in which the gate layers and the dielectric layers are alternately stacked.

8. The method of claim 7, wherein the stacked structure is connected with the peripheral circuit chip by hybrid bonding.

9. The method of any of claims 1 to 8, wherein forming the functional layer comprises: and a blocking layer, a charge trapping layer and a tunneling layer are sequentially formed on the inner wall of the channel hole.

10. A three-dimensional memory, comprising:

a stacked structure including opposing first and second sides;

a semiconductor layer on a first side of the stacked structure; and

the channel structures penetrate through the stacked structure and comprise a functional layer, a channel layer, a first insulating layer and a conducting layer which are sequentially arranged from outside to inside in the radial direction;

wherein the channel layer and the conductive layer are in contact with the semiconductor layer.

11. The three-dimensional memory of claim 10, wherein the semiconductor layer comprises an N-type or P-type doped semiconductor material and is electrically connected to the conductive layer.

12. The three-dimensional memory of claim 10, wherein the location where the channel layer contacts the semiconductor layer comprises a PN junction contact.

13. The three-dimensional memory of claim 10, further comprising: a second insulating layer in contact with the first insulating layer and covering a top of the conductive layer away from the semiconductor layer.

14. The three-dimensional memory of claim 13, further comprising:

a channel plug disposed on a top of the channel structure away from the semiconductor layer,

wherein the channel plug is electrically connected to the channel layer, and the channel plug is isolated from the conductive layer by the second insulating layer.

15. The three-dimensional memory of claim 10, further comprising:

and the peripheral circuit chip is positioned on the second side of the stacked structure.

16. The three-dimensional memory according to claim 15, wherein a hybrid bonding structure is included between the peripheral circuit chip and the stacked structure.

17. The three-dimensional memory according to any of claims 10-16, wherein the functional layer comprises a blocking layer, a charge trapping layer, and a tunneling layer disposed in that order radially from the outside-in.