JP2006012889A - Method for manufacturing semiconductor chip and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor chip with improved productivity, by reducing the formation time of a through hole for a through electrode. <P>SOLUTION: First, a first trench 7a is formed at the upper surface side of a silicon substrate 1 with a first insulating film 3 as a mask member by using, for example, a Bosch process. Then, a second trench 7b communicating with the first trench 7a is formed at the back side of the silicon substrate 1 with a second insulating film 5 as a mask member by using the Bosch process. Then, after forming an insulating film in a formed through hole 8, a conductive material is filled into the through hole 8 and the through electrode 2 is formed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor chip having a through electrode penetrating a semiconductor substrate. The present invention also relates to a method of manufacturing a semiconductor device in which such semiconductor chips are stacked.

  In recent years, various semiconductor devices have been proposed in order to reduce the size and increase the density of multi-function and high-function semiconductor integrated circuits. Among them, not only miniaturization and higher density of semiconductor chips by means of semiconductor element miniaturization technology and multilayer wiring technology, but also a three-dimensional semiconductor integrated circuit in which a large number of semiconductor chips themselves are stacked and electrically connected. Devices have also been proposed.

  FIG. 8 is a cross-sectional view showing an example of such a semiconductor device.

  As illustrated in FIG. 8, the semiconductor device 150 includes three stacked semiconductor chips 121 to 123, and the chips are bonded to each other with an anisotropic conductive film 106. The semiconductor chips 121 to 123 have substantially the same configuration, and the semiconductor chip 121 will be described below as an example.

  The semiconductor chip 121 is electrically connected to, for example, a silicon substrate 101 having a semiconductor element or wiring layer (not shown) formed on the upper surface of the substrate and the wiring layer on the upper surface of the substrate, and the chips are electrically connected to each other. And a conductive member 110 for connection to the.

  The conductive member 110 includes a through electrode 102 formed so as to penetrate through the silicon substrate 101, and a protruding electrode 104 a formed on the upper surface side and the back surface side of the silicon substrate 101 and electrically connected to the through electrode 102, 104b.

  A first insulating film 103 and a second insulating film 105 for insulating the silicon substrate 101 and the conductive member 110 are formed on the upper surface side and the back surface side of the silicon substrate 101, respectively.

  The semiconductor chips 121 to 123 configured as described above are stacked in the thickness direction of the silicon substrate 101, and the chips are electrically connected by the conductive member 110 and the anisotropic conductive film 106.

  Next, a method for manufacturing the semiconductor chip as described above will be described with reference to FIG.

  First, as shown in FIG. 9A, a silicon substrate 101 is prepared, a semiconductor element (not shown) and a wiring layer (not shown) are formed on the upper surface thereof, and then the upper surface of the silicon substrate 101 is covered. A first insulating film 103 is formed.

  Next, as shown in FIG. 9B, the first insulating film 103 is patterned to form a mask opening 103 a for the mask in the first insulating film 103.

  Next, as shown in FIG. 9C, the silicon substrate 101 is etched from the upper surface side using the first insulating film 103 as a mask member. Thereby, a part of the silicon substrate 101 is removed, and a trench 107 having a predetermined depth is formed.

  Next, as shown in FIG. 9D, the silicon substrate 101 is ground from the back surface side, and the trench 107 is opened to the back surface side, thereby forming the through hole 108 penetrating the silicon substrate 101.

  Next, as shown in FIG. 9E, a second insulating film 105 is formed on the entire back surface of the silicon substrate 101 and the inner wall surface of the through hole 108 by, for example, CVD. In FIG. 9, only the second insulating film 105 formed on the back surface of the silicon substrate 1 is shown, and the second insulating film 105 formed on the inner wall surface of the through hole 108 is not shown.

  Next, as shown in FIG. 9F, a conductive member 110z made of a conductive material such as metal is formed by plating, sputtering, CVD, or the like. The conductive member 110z is formed so as to fill the through hole 108 and cover the first insulating film 103 and the second insulating film 105, respectively.

  Next, as shown in FIG. 9G, the conductive member 110z formed on the first insulating film 103 and the second insulating film 105 is patterned to protrude from the insulating films 103 and 105. The protruding electrodes 104a and 104b are formed, whereby the conductive member 110 composed of the through electrode 102 and the protruding electrodes 104a and 104b is formed.

  Through the above steps, one semiconductor chip 121 is manufactured. Further, by stacking the semiconductor chips 121 to 123 manufactured in the same process through the anisotropic conductive film 106, the semiconductor device 150 as shown in FIG. 8 is manufactured.

  Next, a method for forming the trench 107 described in the step of FIG. 9C will be described in more detail.

  In the manufacturing method as described above, the through hole 108 is formed by opening the trench 107 on the back surface side of the substrate. Therefore, when forming the trench 107, the silicon substrate has a depth dimension on the order of several tens to several hundreds of μm. 101 needs to be etched. There are two methods for this etching: wet etching using TMAH or KOH and dry etching using plasma.

  Comparing these two methods, first, wet etching is more advantageous than dry etching in terms of throughput because batch processing is possible. However, since the shape to be etched depends on the crystal orientation of silicon, it is disadvantageous in terms of miniaturization of the element.

  For example, when a silicon substrate having a crystal orientation <100> plane is etched from the upper surface side using TMAH, the inner wall of the trench has a forward taper angle of about 55 °. That is, the trench is formed in a shape that tapers from the upper surface side to the back surface side. Such a shape of the trench is disadvantageous in that the interval between the trenches, in other words, the interval between the through electrodes cannot be reduced.

  Also, for example, in order to provide a 100 μm square opening on the back surface of a 625 μm thick silicon substrate, the opening on the top surface should be 875 μm square when etching from the top surface side to the back surface side using TMAH. I must. Therefore, the interval between the through electrodes must be 975 μm or more, for example. Further, when the opening is 100 μm square on the top surface, the etching stops when the depth from the top surface is 71.4 μm, and it is not possible to dig deeper further.

  On the other hand, although dry etching can be performed only for single wafer processing, etching can be performed without producing the taper shape as described above, which is advantageous in terms of miniaturization of elements. Also, if the inner wall of the trench is tapered, the taper angle is determined by the crystal orientation of the substrate used in wet etching, but the taper angle is controlled by changing the etching parameters in dry etching. It is possible.

There is a Bosch process as a typical silicon deep-drilling method by dry etching (see Patent Document 1). This is because the plasma etching step using SF ₆ gas and the plasma deposition step of depositing a fluorocarbon polymer as a protective film on the inner wall surface of the trench using C ₄ F ₈ gas are alternately repeated. This process enables high-speed anisotropic etching of silicon. In the Bosch process, an etching rate of, for example, 20 μm / min or more can be realized depending on conditions, and a trench shape in which the inner wall is perpendicular to the substrate surface can be obtained.
US Pat. No. 5,501,893

  However, the above-described manufacturing method of the Bosch process has the following problems.

  That is, in the Bosch process, when etching is performed to form a deep trench, the etching rate gradually decreases, and in some cases, the etching may not proceed further. This is because as the trench becomes deeper, the range of the incident angle of F radicals contributing to etching becomes narrower, and the density of F radicals reaching the bottom surface of the trench decreases. In order to form the above-described through-hole in the silicon substrate, as described above, it is necessary to perform etching to form a trench having a depth dimension of about several hundred μm, but the etching rate gradually decreases. As a result, the time required for etching becomes long, resulting in a decrease in productivity.

  In addition, when the etching time is increased as described above, it is necessary to increase the thickness of the mask member to such an extent that it can withstand long-time etching. For example, assuming that the etching selectivity ratio between a silicon thermal oxide film (mask member) and silicon is about 1: 100, in order to form a trench having a depth of 300 μm, the thickness of the mask member is calculated to be 3 μm. It is necessary to do it above. When the film thickness of the mask member is increased, the internal stress of the laminated film on the surface of the silicon substrate is increased, and in some cases, there is a risk of causing problems such as generation of cracks. On the other hand, it is possible to reduce the film thickness by densifying the film quality of the mask member so that it can withstand long-time etching. However, even if such a dense film is thin, its internal stress becomes large, and as a result, there is a possibility of causing the same problem as described above.

  In addition, it is conceivable to improve the productivity by reducing the depth of the trench, but when the trench is made shallow, the silicon substrate must be ground to a thinner thickness in order to provide a through hole. As a result, the mechanical strength decreases. Therefore, the silicon substrate is warped by an insulating film or the like laminated on the device surface on the upper surface side of the silicon substrate, or is easily broken only by applying a small force.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor chip manufacturing method in which productivity is improved by shortening the formation time of a through hole for a through electrode. There is. Another object of the present invention is to provide a method of manufacturing the conductor device using such a manufacturing method. Still another object of the present invention is to provide a semiconductor chip and a semiconductor device which have improved reliability by using the manufacturing method as described above.

  In order to achieve the above object, a method for manufacturing a semiconductor chip according to the present invention is a method for manufacturing a semiconductor chip having a through electrode penetrating a semiconductor substrate, and is first anisotropically etched from one surface of the semiconductor substrate. Forming a second trench, forming a second trench communicating with the first trench by anisotropic etching from a surface opposite to the one surface of the semiconductor substrate, and the first A step of forming an insulating film made of an insulating material on the inner wall surface of the through-hole formed by communication between the first trench and the second trench; and a conductive layer in the through-hole in which the insulating film is formed. A step of filling the conductive material to form the through electrode.

  Also, the semiconductor device manufacturing method of the present invention includes stacking a plurality of semiconductor chips manufactured by the semiconductor chip manufacturing method so that the semiconductor chips are electrically connected to each other through the through electrodes. Thus, a semiconductor device is obtained.

  Further, the semiconductor chip of the present invention can be manufactured by the manufacturing method of the present invention, wherein the through electrode is formed by anisotropic etching from one surface of the semiconductor substrate, and the one And a second trench formed by anisotropic etching from the surface on the opposite side of the surface in the through hole formed. The semiconductor device of the present invention is configured by stacking such semiconductor chips.

  According to the manufacturing method of the present invention, the first trench is formed from one surface of the semiconductor substrate, and the second trench is formed from the opposite surface, thereby forming a through-hole penetrating the semiconductor substrate. Compared to the conventional manufacturing method in which the through hole is formed by performing etching only from one side and grinding the semiconductor substrate from the opposite side, the time for forming the through hole is shortened. Turn into.

  In addition, the semiconductor chip of the present invention is manufactured by the above-described manufacturing method of the present invention, and compared with the conventional method, the etching on the device surface side of the chip performed for forming the through hole may be less. Therefore, the adverse effect on the device (semiconductor element) due to etching is reduced. Moreover, since the manufacturing method of the present invention does not grind the substrate to form a through hole to form a through hole, the semiconductor substrate is sufficiently thick and the mechanical strength is not lowered. And the semiconductor device of this invention manufactured using such a semiconductor chip becomes highly reliable as a result by the above effects of the semiconductor chip of this invention.

  As described above, according to the manufacturing method of the present invention for manufacturing a semiconductor chip and a semiconductor device, a trench formed from one surface of a semiconductor substrate and a trench formed from the surface on the opposite side communicate with each other. Since the hole is formed, the time for forming the through hole is shortened, and as a result, the semiconductor chip and the semiconductor device can be manufactured with high productivity. Further, the semiconductor chip of the present invention manufactured by such a method has high reliability in which damage to the device due to etching is suppressed and sufficient mechanical strength is ensured, and a book using such a semiconductor chip is used. The semiconductor device of the invention also becomes highly reliable as a result.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view showing an example of a semiconductor device manufactured by the manufacturing method according to the first embodiment of the present invention. FIG. 2 is a diagram for explaining a method of manufacturing a semiconductor chip according to the first embodiment of the present invention.

  The semiconductor device 50 shown in FIG. 1 has substantially the same configuration as the semiconductor device 150 shown in FIG. That is, the semiconductor device 50 includes three semiconductor chips 20a to 20c (hereinafter, referred to as semiconductor chips 20) that are bonded and stacked using the anisotropic conductive film 6. Each semiconductor chip 20 is electrically connected to each other through the conductive member 10 and the anisotropic conductive film 6.

  A configuration of one semiconductor chip 20 will be described below as an example.

  The upper surface side of the semiconductor chip 20 is a device surface. Although not shown, a semiconductor element and a wiring layer electrically connected thereto are formed on the upper surface of the silicon substrate 1. The semiconductor chip 20 has a conductive member 10 made of a conductive material. The conductive member 10 includes a through electrode 2 formed so as to penetrate the silicon substrate 1 and an upper surface side of the silicon substrate 1. And projecting electrodes 4a and 4b respectively formed on the back surface side.

  In the illustrated configuration, only one through electrode 2 is formed, but a plurality of through electrodes 2 may be formed.

  The shape of the outer peripheral surface of the through-electrode 2, in other words, the shape of the inner wall surface of the through-hole 8 (see FIG. 2) provided in the silicon substrate 1 is uneven as shown in the drawing, as described later. This is because the through-hole 8 is provided using a process. FIG. 1 schematically shows the uneven shape exaggeratedly, and is actually flatter.

  As in the semiconductor device 150 shown in FIG. 8, a first insulating film 3 for insulating the silicon substrate 1 and the protruding electrode 4a is formed between the upper surface of the silicon substrate 1 and the protruding electrode 4a. Further, a second insulating film 5 is also formed between the back surface of the silicon substrate 1 and the protruding electrode 4b to insulate the silicon substrate 1 and the protruding electrode 4b. Although not shown, a third insulating film for insulating the through electrode 2 and the silicon substrate 1 is also formed around the through electrode 2. As described above, the conductive member 10 is in a state where most of the portions thereof are insulated from the silicon substrate 1 by the insulating film. However, a wiring layer (not shown) is partially formed on the upper surface of the silicon substrate 1 at a connection portion (not shown). As a result, external electric power can be supplied to a semiconductor element (not shown) formed on the silicon substrate 1.

  Next, the semiconductor chip manufacturing method according to the present embodiment will be explained with reference to FIG.

  First, as shown in FIG. 2A, a silicon substrate 1 is prepared, a semiconductor element (not shown) and a wiring layer (not shown) are formed on the upper surface of the substrate, and then the entire upper surface of the silicon substrate 1 is covered. Then, the first insulating film 3 is formed.

  Next, as shown in FIG. 2B, the first insulating film 3 is patterned to form a mask opening 3 a for the mask in the first insulating film 3. Thereby, a part of upper surface of the silicon substrate 1 is exposed.

  Next, as shown in FIG. 2C, the silicon substrate 1 is etched from the upper surface side using the first insulating film 3 as a mask member, and the depth dimension is about half of the thickness of the silicon substrate 1. One trench 7a is formed using a Bosch process.

  Next, as shown in FIG. 2D, a second insulating film 5 serving as a mask member is formed on the entire back surface of the silicon substrate 1. The second insulating film 5 is formed by using the same method as the method for forming the first insulating film 3, for example, with the same material and the same film thickness as the first insulating film 3. Also good.

  Next, as shown in FIG. 2E, a mask opening 5 a for a mask is formed in the second insulating film 5. The size of the mask opening 5a is substantially the same as that of the mask opening 3a on the upper surface side, and the position of each mask opening 5a is projected in the thickness direction of the silicon substrate 1. The positions are such that the portions 3a and 5a match.

  Next, as shown in FIG. 2F, the silicon substrate 1 is etched from the back surface side using, for example, a Bosch process using the second insulating film 5 as a mask member. By this etching, a second trench 7b communicating with the bottom surface of the first trench 7a is formed, and finally a through-hole 8 composed of the first and second trenches 7a and 7b is formed. When the through hole 8 is formed, a third insulating film (not shown) for insulating the silicon substrate 1 and the through electrode 2 is formed on the inner wall surface of the through hole 8.

  Next, as shown in FIG. 2G, a conductive member 10z made of a conductive material such as metal is formed using plating, sputtering, CVD, or the like. The conductive member 10z is formed so as to fill the inside of the through hole 8 and cover the entire surfaces of the first insulating film 3 and the second insulating film 5. Thus, the conductive material becomes the through electrode 2 by filling the through hole 8 with the conductive material.

  Next, as shown in FIG. 2 (h), by patterning each of the conductive members 10z formed on the first insulating film 3 and the second insulating film 5, the insulating films 3 and 5 can be patterned. The protruding electrodes 4a and 4b are formed in a protruding form, and finally the conductive member 10 composed of the through electrode 2 and the protruding electrodes 4a and 4b is formed.

  The semiconductor chip 20 is manufactured through the above series of steps.

  The semiconductor device 50 shown in FIG. 1 is manufactured by stacking the semiconductor chips 20 manufactured in this way so that the chips are electrically connected via the anisotropic conductive film 6.

  The first insulating film 3 and the second insulating film 5 are not only used as insulating members but also used as mask members at the time of etching as described above. In particular, the film thickness is such that the insulating films 3 and 5 are not removed by etching until the trenches 7a and 7b are formed. It is necessary to be.

  The trenches 7a and 7b are not limited to those having substantially the same inner diameter, and the inner diameter of the first trench 7a may be different from the inner diameter of the second trench 7b. In this case, the inner diameter shapes of the trenches 7a and 7b may be changed by changing the sizes of the mask openings 3a and 5a formed in the insulating films 3 and 5, respectively.

Example 1
A more specific example of the manufacturing method according to the first embodiment of the present invention will be described below in correspondence with the steps shown in FIGS.

(A) A silicon wafer having a diameter of 150 mm and a thickness of 625 μm was prepared as the silicon substrate 1. Then, as the first insulating film 3, a plasma oxide film having a thickness of 4 μm was formed using a plasma CVD method. The conditions at this time were a substrate temperature of 380 ° C., a pressure of 1.8 Torr, SiH ₄ = 250 cc / min, N ₂ O = 1200 cc / min, N ₂ = 4000 cc / min, a high frequency output of 13.56 MHz, 1800 W, and a film formation rate. Was 4100 kg / min.

(B) The mask opening 3a was formed by partially etching the plasma oxide film (first insulating film 3). Etching conditions at this time are: substrate temperature 25 ° C., pressure 0.5 Torr, CF ₄ = 20 cc / min, CHF ₃ = 25 cc / min, Ar = 300 cc / min, high frequency output 800 W of 13.56 MHz, and etching rate is 5000 Å. / Min.

(C) The first trench 7a was formed using a Bosch process in which deposition and etching are alternately repeated. At this time, the substrate temperature is 23 ° C., the pressure is 3.1 Pa, C ₄ F ₈ = 200 cc / min, the deposition of a high frequency output of 2800 W at 13.56 MHz, the substrate temperature is 23 ° C., the pressure is 8.3 Pa, and SF ₆ = Etching with a high frequency output of 2800 W at 750 cc / min and 13.56 MHz was performed for 68 min at a cycle of 2 sec / 7 sec. As a result, a first trench 7 a having a depth dimension of 315 μm and an inner wall perpendicular to the substrate surface of the silicon substrate 1 was obtained. At this time, the selection ratio between silicon and the plasma oxide film (first insulating film 3) was 150: 1, and the plasma oxide film remained with a thickness of 0.9 μm.

(D) (e) (f) The second insulating film 5, the mask opening 5a, and the second trench 7b are formed by the same process and the same conditions as the above (a) to (c), and penetrated. Hole 8 was formed. Like the first trench 7a, the inner wall of the second trench 7b is perpendicular to the substrate surface of the silicon substrate 1. Therefore, the inner wall of the finally formed through hole 8 is also on the substrate surface. On the other hand, it became vertical. Thereafter, as a third insulating film (not shown), a plasma oxide film having a thickness of 1 μm was formed on the inner wall surface of the through-hole 8 using a plasma CVD method. The film formation conditions at this time were a substrate temperature of 400 ° C., a pressure of 8.2 Torr, TEOS / He = 1600 cc / min, O ₂ = 550 cc / min, a high frequency output of 700 W at 13.56 MHz, and a film formation rate of 6500 Å / min. there were.

(G) Cu was formed into a film by the electroplating method as the electroconductive member 10z. The film forming conditions at this time were a solution temperature of 25 ° C., a current density of 18 mA / cm ² , and a distance between electrodes of 20 mm.

  (H) The conductive member 10 was formed by patterning Cu formed as the conductive member 10z.

  The semiconductor chip 20 was manufactured as Example 1 by the series of steps described above.

  In the Bosch process, deposition and etching are alternately repeated at a constant period to perform anisotropic etching of silicon, and minute irregularities are formed on the inner walls of the trenches 7a and 7b according to this period. . In addition, in the Bosch process, the etching rate decreases as the depth of digging deepens, and the uneven shapes of the inner walls of the trenches 7a and 7b change accordingly. This change means that the height of the unevenness is lowered although the period of the unevenness does not change. For this reason, in the vicinity of the bottom surface of the trench, the unevenness of the inner wall becomes inconspicuous as compared with the vicinity of the opening, and the shape is almost close to a mirror surface.

  In this embodiment, various numerical values (for example, numerical values such as etching conditions and trench depth dimensions) are given as specific examples, but these are not limited to the numerical values listed here, and can be freely set according to the purpose. It is possible to select.

  As described above, according to the manufacturing method of the present embodiment, the first trench 7a is formed from one surface of the silicon substrate 1, and the second trench 7b is formed from the opposite surface to form a through hole. 8 is formed, the formation time of the through hole 8 is shortened as compared with the conventional manufacturing method described with reference to FIG. The reason for this is that the depth dimensions of the trenches 7a and 7b are both about half of the substrate thickness, and even if etching is performed using the Bosch process, the etching rate generated due to the decrease in the density of F radicals. This is because it is not easily affected by the decline.

  In addition, since the etching for forming the through holes 8 is performed from both sides of the substrate, each mask member (the first insulating film 3 and the second insulating film 3 is compared with the etching performed only from one side). The thickness of the insulating film 5) can be reduced.

  Further, according to the manufacturing method of the present embodiment, the through-hole 8 can be formed even if the silicon substrate 1 is relatively thick, and the back surface side grinding can be performed as in the conventional method of FIG. Therefore, the thickness of the silicon substrate 1 can be sufficiently secured, and the mechanical strength of the semiconductor chip 20 is not reduced.

(Second Embodiment)
FIG. 3 is a sectional view showing an example of a semiconductor device manufactured by the manufacturing method according to the second embodiment of the present invention. FIG. 4 is a view for explaining a method of manufacturing a semiconductor chip according to the second embodiment of the present invention.

  The semiconductor device 51 in FIG. 3 is different from the semiconductor device 50 in FIG. 1 in that the shape of the through electrode 12 is changed. Since the other configuration is the same as that of the semiconductor device 50 of FIG. 1, the same reference numerals as those in FIG.

In the first embodiment (Example 1), the method of forming the first trench 7a on the upper surface side and the second trench 7b on the rear surface side using the Bosch process has been described, but the present invention is not limited thereto. For example, the trench may be formed by using plasma etching with SF ₆ / O ₂ gas.

In plasma etching with SF ₆ / O ₂ gas, the inner wall surface of the trench is mirror-like, and unevenness as seen in the Bosch process does not occur. Further, the taper angle of the inner wall of the trench can be changed by changing the parameters of the etching process. Therefore, the trench according to the present embodiment has a shape that tapers toward the center of the substrate as illustrated, in other words, a shape in which the aperture diameter gradually decreases toward the center of the substrate. However, conversely, it is possible to form a trench having a shape in which the aperture diameter gradually increases toward the center of the substrate.

  Next, the semiconductor chip manufacturing method according to the present embodiment will be explained with reference to FIG. The detailed description of the same steps as the manufacturing method of the first embodiment is omitted, and the manufacturing method of the first embodiment is also provided in that trenches are formed from both sides of the substrate to form through holes. As a whole, the overall explanation is also simple.

The manufacturing method of the second embodiment shown in FIG. 4 is as follows.
(A) A first insulating film 3 is formed on the upper surface of the silicon substrate 1, and a mask opening 3a is formed.
(B) Plasma etching is performed from the upper surface side of the substrate using the first insulating film 3 as a mask member to form a first trench 17a. The depth dimension of the first trench 17a is about half of the thickness of the silicon substrate 1.
(C) A second insulating film 5 is formed on the back surface of the silicon substrate 1 by the same process as in the above (a).
(D) A mask opening 5 a is formed in the second insulating film 5.
(E) From the substrate rear surface side, the second trench 17b is formed by the same process as the above (c), and the through hole 18 is formed. Then, a third insulating film (not shown) is formed in the through hole 18.
(F) The conductive member 11z is formed.
(G) The conductive member 11z is patterned to form the conductive member 11 including the through electrode 12 and the protruding electrodes 4a and 4b.

  The semiconductor chip 21 is manufactured through the series of steps described above.

In plasma etching using SF ₆ / O ₂ gas, the degree to which the etching rate decreases when the trench is deeply drilled is larger than that in the Bosch process. Therefore, the effect of shortening the through-hole forming step by applying the plasma etching process to the present invention is greater than when the Bosch process is applied.

(Example 2)
A more specific example of the manufacturing method according to the second embodiment of the present invention will be described below. The difference between the present embodiment and the first embodiment is that the trench is formed not by the Bosch process but by SF ₆ / O ₂ etching, and other processes, materials of the respective structural portions, etc. Since it is the same as that of Example 1, the description thereof is omitted, and only FIGS. 4B and 4E which are characteristic steps of the present embodiment will be described.

(B) The first trench 17a was formed by plasma etching using SF ₆ / O ₂ gas. Etching conditions at this time were a substrate temperature of −100 ° C., a pressure of 2.0 Pa, SF ₆ = 55 cc / min, O ₂ = 30 cc / min, a 2.5 GHz high frequency output of 800 W, and an 800 kHz bias low frequency of 45 W. As a result, a first trench 17a having a depth dimension of 350 μm was obtained. The taper angle of the inner wall of the trench was 91 degrees with respect to the substrate surface. At this time, the selection date of silicon and the plasma oxide film (first insulating film 3) was 350: 1, and the plasma oxide film remained 2 μm thick.

  (E) The second trench 17b was formed and the through hole 18 was formed by the same process as in the above (b). The cross-sectional shape of the through-hole 18 was symmetric between the upper surface side and the back surface side of the silicon substrate 1 in the thickness direction of the substrate.

  In the present embodiment, various numerical values (such as etching conditions, taper angles, and trench depth dimensions) are given as specific examples. However, all of the numerical values are not limited to the numerical values listed here, depending on the purpose. Can be selected freely.

(Third embodiment)
FIG. 5 is a diagram for explaining a method of manufacturing a semiconductor chip according to the third embodiment of the present invention.

  In each of the two embodiments described above, the first trenches 7a and 17a on the substrate upper surface side (device surface side) are first formed. However, the present invention is not limited to this, and the first trench on the back surface side. Two trenches may be formed first. In addition, the manufacturing method of this embodiment replaces the order of the formation process of the 1st trench 7a (refer FIG. 2) and the formation process of the 2nd trench 7b in the manufacturing method of 1st Embodiment, Other processes and materials of each structure are the same as those in the first embodiment.

The manufacturing method of the third embodiment shown in FIG. 5 is as follows.
(A) A second insulating film 5 is formed on the back surface of the silicon substrate 1, and a mask opening 5a is formed.
(B) Using the second insulating film 5 as a mask member, etching by a Bosch process is performed to form a second trench 7b on the back side of the substrate.
(C) A first insulating film 3 is formed on the upper surface of the silicon substrate 1.
(D) A mask opening 3 a is formed in the first insulating film 3.
(E) Using the first insulating film 3 as a mask member, etching by a Bosch process is performed to form a first trench 7a on the upper surface side of the substrate, and a through hole 8 is formed. Then, a third insulating film (not shown) is formed in the through hole 8.
(F) The conductive member 10z is formed.
(G) The conductive member 10z is patterned to form the conductive member 10 including the through electrode 2 and the protruding electrodes 4a and 4b.

  The semiconductor chip 22 is manufactured through the series of steps described above.

  In addition, the process of forming a semiconductor element (not shown) on the upper surface of the silicon substrate 1 includes, for example, a process of forming a second trench 7b shown in FIG. 5B and a first insulation shown in FIG. It is possible to carry out between the process of forming the film 3. For example, in the manufacturing method according to the first embodiment described with reference to FIG. 2, the semiconductor element is formed in the initial process (the process shown in FIG. 2A) in the manufacturing process. Since the semiconductor element formation process is performed after the second trench 7b is formed, the number of processes from the formation of the semiconductor element to the completion is reduced. For example, some device or the like collides with the device surface. Thus, the occurrence rate of damage to the semiconductor element caused by the above can be reduced.

In this embodiment, etching by the Bosch process is applied to the formation of the trenches 7a and 7b. However, the present invention is not limited to this, and plasma etching using SF ₆ / O ₂ gas may be applied. Alternatively, the Bosch process and plasma may be used. It is also possible to combine etching. For example, the first trench 7a may be formed by a Bosch process and may be formed by plasma etching with the second trench 7b.

(Fourth embodiment)
When the second trench 7b on the back surface side is formed first as in the third embodiment, the second trench 7b may be formed deeper than the first trench 7a.

  FIG. 6 is a diagram for explaining a semiconductor chip manufacturing method according to the fourth embodiment of the present invention.

  In the manufacturing method of the present embodiment, as shown in FIG. 6A, prior to the formation of the first trench 27a, the second trench whose depth dimension is relatively larger than that of the first trench 27a. 27b is formed on the back side of the substrate.

  Then, as shown in FIG. 6B, the first trench 27a having a relatively small depth dimension is formed on the substrate upper surface side, and the through hole 28 is formed.

  Thus, by relatively increasing the depth dimension of the second trench 27b, the depth dimension of the first trench 27a is relatively decreased. Therefore, the etching amount for forming the first trench 27a can be reduced. The fact that the etching amount is small means that, for example, the etching time is short, and thus the etching time is shortened, thereby reducing the influence of etching on the semiconductor element (not shown) formed on the upper surface of the substrate. Can be made. Therefore, according to the manufacturing method of the present embodiment, it is possible to obtain an effect of suppressing the deterioration of the characteristics of the semiconductor element and the accompanying yield reduction.

Example 3
In order to form the second trench 27b having a relatively large depth dimension, for example, a Bosch process is used, the substrate temperature is 23 ° C., the pressure is 3.1 Pa, C ₄ F ₈ = 200 cc / min, and 13. Deposition of a high frequency output of 2800 W at 56 MHz and etching at a substrate temperature of 23 ° C., a pressure of 8.3 Pa, SF ₆ = 750 cc / min, and a high frequency output of 2800 W of 13.56 MHz for 86 min under the condition of a cycle of 2 sec / 7 sec. Etching was performed to obtain a trench 27b having a depth of 400 μm. At this time, the selection ratio between silicon and the plasma oxide film (second insulating film 5) was 150: 1, and the plasma oxide film remained with a thickness of 0.4 μm. Note that numerical values such as etching conditions and trench depth dimensions given in this embodiment are not limited to the numerical values given here, and can be freely selected according to the purpose.

  As described above, the representative manufacturing method of the present invention has been described as the first to fourth embodiments. However, in the manufacturing method according to the present invention, for example, the first trench on the upper surface side can be used as an alignment mark. is there.

  Usually, in manufacturing this type of semiconductor chip, an alignment mark is provided on a silicon substrate in advance in order to achieve alignment during mask exposure. In this case, in order to easily identify the alignment mark with high contrast, a predetermined step is often formed on the substrate and used as the alignment mark. Since the trench formed by the manufacturing method of the present invention is formed by deeply digging a silicon substrate, it can be suitably used as an alignment mark. In addition, while the alignment mark has no function other than alignment, using the trench in common with the alignment mark has the effect of effectively utilizing the device region within a limited area on the substrate. is there. Furthermore, since the mask is aligned with respect to the trench by using the trench as an alignment mark, according to such a method, a dedicated alignment mark is provided and alignment is performed based on the alignment mark. In comparison, there is an effect that the alignment accuracy of the silicon substrate can be improved. More specifically, it is particularly effective for the alignment of the first trench on the upper surface side and the second trench on the rear surface side, and the silicon substrate 1 is positioned with reference to the first trench, By forming the mask opening on the side with high positional accuracy, the second trench can be formed with high positional accuracy relative to the first trench.

(Fifth embodiment)
FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.

  The semiconductor device 52 in FIG. 7 includes a CMOS sensor chip 24 and a timing generator chip 25 stacked in two layers, and is used as an imaging system such as a digital camera.

  Each of the chips 24 and 25 includes a conductive member 40 including a through electrode 42 formed through the silicon substrate 1 and a protruding electrode 44 formed so as to protrude from the back surface of the silicon substrate 1. have. The conductive member 40 is formed so as to be electrically connected to a wiring layer (not shown) on the upper surface of each silicon substrate 1, and the portions other than the connection portion will be described in, for example, the first embodiment. Similar to the conductive member 10, the silicon substrate 1 is insulated.

  The two chips 24 and 25 are fixed in a stacked state by an adhesive 33 and are electrically connected to each other via the conductive member 40 in this state. Further, a flexible wiring 31 electrically connected to the protruding electrode 44 is disposed on the back side of the timing generator chip 25. Thereby, electric power is supplied to both chips 24 and 25 from the outside.

  A protective cover glass 30 is disposed above the CMOS sensor chip 24, and the side surfaces of the cover glass 30 and the stacked chips 24 and 25 are sealed with a sealing material 32.

  When semiconductor chips are arranged side by side on a plane, the mounting size usually increases on the order of several mm square, but when the chips 24 and 25 are three-dimensionally stacked as in the present embodiment. The mounting size in the stacking direction only increases by approximately the thickness of the substrate, and the size of the mounting region in the plane does not increase. In addition, since the thickness of a board | substrate is about 1 mm or less normally, the increase amount of the mounting size in the lamination direction is also suppressed to about 1 mm or less.

  In the present embodiment, the CMOS sensor chip 24 and the timing generator chip 25 are stacked. However, the present invention is not limited to this, for example, a stack of different types of memories (for example, flash memory and SRAM), a memory, The present invention is applicable to ASIC stacking, analog IC and digital IC stacking, arithmetic processing circuit and power IC stacking, and the like. In addition, the present invention can be applied to a display module such as a cellular phone, and as a specific example, for example, a liquid crystal display panel, a driver, a controller, a gray scale IC and other image processing circuits stacked in order from the upper surface side.

  In any of these cases, there is an effect that the module can be miniaturized and highly functionalized by high integration. Further, by applying the present invention, the productivity in the process of forming the through electrode can be improved, so that the module productivity can be improved. Furthermore, as shown in the fourth embodiment, the rear surface side trench is formed deeper and the etching amount of the upper surface side trench is reduced, so that damage to the semiconductor element due to plasma etching can be reduced, Degradation of the characteristics of the semiconductor element is suppressed, and there is an effect that a semiconductor chip provided with a through electrode can be manufactured with a high yield.

  The semi-invention relates to a semiconductor chip having a through electrode penetrating a semiconductor substrate, and a method of manufacturing a semiconductor device in which the chips are stacked. The semiconductor chip and the semiconductor device manufactured by the manufacturing method of the present invention include, for example, a cellular phone It can be suitably applied to devices that require small and high-density mounting technology such as robots and robots.

It is sectional drawing which shows an example of the semiconductor device manufactured with the manufacturing method by the 1st Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor chip by the 1st Embodiment of this invention. It is sectional drawing which shows an example of the semiconductor device manufactured with the manufacturing method by the 2nd Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor chip by the 2nd Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor chip by the 3rd Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor chip by the 4th Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device by one Embodiment of this invention. It is sectional drawing which shows an example of the conventional semiconductor device. It is a figure for demonstrating the manufacturing method of the conventional semiconductor chip.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2, 12, 42 Through electrode 3 1st insulating film 3a Mask opening part 4a, 4b, 44 Protruding electrode 5 2nd insulating film 6 Anisotropic conductive film 7a, 7b, 17a, 17b, 27a, 27b Trench 8, 18, 28 Through hole 10, 10z, 11, 11z, 40 Conductive member 20, 21, 22 Semiconductor chip 50, 51, 52 Semiconductor device

Claims (10)

A method for manufacturing a semiconductor chip having a through electrode penetrating a semiconductor substrate,
Forming a first trench by anisotropic etching from one surface of the semiconductor substrate;
Forming a second trench communicating with the first trench by anisotropic etching from a surface opposite to the one surface of the semiconductor substrate;
Forming an insulating film made of an insulating material on an inner wall surface of a through-hole formed by communication between the first trench and the second trench;
A method of manufacturing a semiconductor chip, comprising the step of filling the through hole in which the insulating film is formed with a conductive material to form the through electrode. Further comprising forming a semiconductor element on the semiconductor substrate;
Forming the first trench includes forming the first trench from a surface opposite to a surface on which the semiconductor element is formed;
2. The method of manufacturing a semiconductor chip according to claim 1, wherein the step of forming the second trench includes forming the second trench from a surface on the side where the semiconductor element is formed.   The semiconductor chip manufacturing method according to claim 1, wherein a depth dimension of the first trench and a depth dimension of the second trench are substantially the same.   The semiconductor chip manufacturing method according to claim 2, wherein a depth dimension of the first trench is larger than a depth dimension of the second trench.   5. The semiconductor chip according to claim 2, wherein the step of forming the semiconductor element is performed between the step of forming the first trench and the step of forming the second trench. 6. Manufacturing method.   6. The semiconductor according to claim 1, wherein the step of forming the second trench includes aligning the semiconductor substrate with reference to the previously formed first trench. Chip manufacturing method.   7. The method according to claim 1, wherein the step of forming the first trench and the step of forming the second trench include forming a trench using etching by Bosch process or plasma etching. The manufacturing method of the semiconductor chip of description.   A step of laminating a plurality of semiconductor chips manufactured by the manufacturing method according to claim 1 so that the semiconductor chips are electrically connected to each other through the through electrodes. A method for manufacturing a semiconductor device. A semiconductor chip having a through electrode penetrating a semiconductor substrate,
The through electrode includes a first trench formed by anisotropic etching from one surface of the semiconductor substrate and a second trench formed by anisotropic etching from a surface opposite to the one surface. A semiconductor chip provided in a through-hole formed by communicating with a trench. A semiconductor device in which a plurality of semiconductor chips according to claim 9 are stacked, and the semiconductor chips are electrically connected to each other through respective through electrodes.

Images