JPH04280453A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce number of steps of a manufacturing process and to prevent short circuit between wirings in a manufacturing method for a semiconductor integrated circuit device. CONSTITUTION:In a manufacturing method for a semiconductor integrated circuit device having the steps of selectively burying a high melting point metal material 7 in a connecting hole 6 formed in an interlayer insulating film 5 on a lower layer interconnection 4 by a vapor chemical growing method, and electrically connecting an upper layer interconnection 10 formed on the film 5 to the interconnection 4 through the material 7, the steps of forming the interconnection 10, and then selectively removing a foreign matter 8 adhered between the interconnections 10 on the film 5 with hydrogen peroxide water, are provided. The material 7 is formed of any of W, Mo and Ti.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular, the present invention relates to a semiconductor integrated circuit device, and in particular, the present invention relates to a semiconductor integrated circuit device. The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device in which a gold layer material is buried and the upper layer wiring formed on the interlayer insulating film and the lower layer wiring are electrically connected through the high melting point metal material.

0002

2. Description of the Related Art Wiring that electrically connects semiconductor elements of a circuit system mounted on a semiconductor integrated circuit device tends to be miniaturized as the circuit systems become more highly integrated. For example, in a semiconductor integrated circuit device having a two-layer wiring structure, the miniaturization of wiring is related to the aspect ratio (depth/diameter) of a contact hole formed in an interlayer insulating film for electrically connecting an upper layer wiring to a lower layer wiring. ) is increasing. For this reason, there is a problem in that the step coverage of the upper layer wiring is reduced at the connection hole portion, resulting in connection failure (disconnection).

As a technique for solving such technical problems between wiring layers, for example, high melting point tungsten (W) film is selectively injected into the connection hole formed in the interlayer insulating film on the lower wiring layer using selective CVD. A method of manufacturing a semiconductor integrated circuit device has been developed in which a metal material is embedded and an upper layer wiring formed in the interlayer insulating film is electrically connected to the lower layer wiring through the high melting point metal material.

However, in the method for manufacturing a semiconductor integrated circuit device, when the high melting point material of the W film is selectively embedded in the contact hole of the interlayer insulating film by the selective CVD method, if the selectivity decreases,
There is a problem in that foreign matter with W as its nucleus is generated on the interlayer insulating film, and this foreign matter causes a short circuit between upper layer wirings.

Therefore, as a technique for solving the technical problem between upper layer wirings, a method for manufacturing a semiconductor integrated circuit device in which foreign matter is removed by lift-off, for example, is disclosed in Japanese Unexamined Patent Publication No. 2-2.
It is described in Publication No. 35331.

The method for manufacturing a semiconductor integrated circuit device includes forming an interlayer insulating film on the lower wiring, applying a PIQ film, for example, on the entire surface of the interlayer insulating film by a spin coating method, and then performing a baking process to form a second layer. Form an insulating film. Next, after forming a photoresist film in a predetermined pattern on the second insulating film, this photoresist film is used as an etching mask, and the surface of the lower wiring is exposed to the second insulating film and the interlayer insulating film. Form a connection hole. Next, a high melting point metal material such as a W film is selectively filled into the connection hole using a selective CVD method. At this time, if the selectivity decreases, foreign matter will be generated on the second insulating film. Next, the second insulating film is etched to remove the second insulating film and the foreign matter. Next, for example, an aluminum film is deposited on the entire surface of the interlayer insulating film including the high melting point metal material, and then the aluminum film is patterned using an etching mask with a predetermined pattern to form an upper layer wiring.

[0007] This makes it possible to remove foreign matter generated when selectively embedding the W film into the connection hole formed in the interlayer insulating film, thereby preventing short circuits between upper layer wirings.

[0008]

[Problems to be Solved by the Invention] However, in the method for manufacturing a semiconductor integrated circuit device, a second layer for removal is formed on the interlayer insulating film.
Since an insulating film is formed, the number of steps equivalent to this number is
There was a problem in that the number of steps in the manufacturing process increased.

An object of the present invention is to selectively embed a high melting point metal material into the connection hole formed in the interlayer insulating film on the lower layer wiring by selective CVD method, and to connect the upper layer wiring formed on the interlayer insulating film. It is an object of the present invention to provide a technology capable of reducing the number of manufacturing process steps and preventing short circuits between upper layer wirings in a semiconductor integrated circuit device that is electrically connected to the lower layer wiring through the high melting point metal material. .

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0011]

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions will be as follows.
It is as follows.

[0012] A high melting point metal material is selectively embedded in the connection hole formed in the interlayer insulating film on the lower wiring by selective CVD method,
In a method for manufacturing a semiconductor integrated circuit device in which an upper layer wiring formed on the interlayer insulating film is electrically connected to the lower layer wiring through the high melting point metal material, forming an interlayer insulating film on the lower layer wiring; A step of forming a connection hole in which the surface of the lower layer wiring is exposed on a part of the lower layer wiring of the interlayer insulating film, and a step of forming a selected C on the lower layer wiring exposed from inside the connection hole.
A step of selectively forming a high melting point metal material by a VD method, forming a wiring layer on the interlayer insulating film, and connecting a part of this wiring layer to the high melting point metal material formed in the connection hole. This wiring layer is selectively patterned using anisotropic etching, except for the connection part with the refractory metal material in the connection hole of the wiring layer, and the remaining wiring layer is used to connect the upper layer wiring. and a step of selectively removing foreign matter that adheres when the high melting point metal material is selectively formed by the selective CVD method in the area where the wiring layer on the interlayer insulating film has been removed by patterning. Equipped with. The high melting point metal material is W, M
It is formed of either O or Ti. The step of removing the foreign matter is performed by etching using hydrogen peroxide.

[0013]

[Operation] According to the above-mentioned means, foreign matter generated when selectively forming a high melting point metal material in areas other than the upper layer wiring on the interlayer insulating film by the selective CVD method is removed once after the upper layer wiring is formed. Since it can be removed during the process, it is possible to reduce the number of steps in the manufacturing process of semiconductor integrated circuit devices, and after embedding the high melting point metal material in the connection hole and covering the high melting point metal material with the upper layer wiring, it is attached to the interlayer insulating film. Since the foreign matter is selectively removed, the upper layer wiring serves as a mask when removing the foreign matter, and damage to the surface of the high melting point metal material can be eliminated.

Furthermore, since foreign matter between the upper layer wirings on the interlayer insulating film can be removed, short circuits between the upper layer wirings due to foreign matter can be prevented.

The structure of the present invention will be described below along with an embodiment in which the present invention is applied to a semiconductor integrated circuit device having a two-layer wiring structure.

In all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[0017]

[Embodiment] FIG. 1 (cross-sectional view of essential parts) shows a schematic configuration of a semiconductor integrated circuit device having a two-layer wiring structure, which is an embodiment of the present invention.
Shown below.

As shown in FIG. 1, a semiconductor integrated circuit device having a two-layer wiring structure is mainly composed of a p-type semiconductor substrate 1 made of single crystal silicon. Although not shown, an active region (element formation region) is provided on the main surface of the p-type semiconductor substrate 1.

Semiconductor elements such as MOS transistors and capacitive elements constituting memory cells are formed in the active region. This active region is electrically isolated from other active regions mainly by a p-type semiconductor substrate 1 and a field insulating film (element isolation insulating film) 2.

The field insulating film 2 is formed in a non-active region on the main surface of the p-type semiconductor substrate 1. A first layer wiring 4 extends over the field insulating film 2 and the semiconductor element with an interlayer insulating film 3 interposed therebetween. The wiring 4 is electrically connected to a pair of semiconductor regions, which are the source region and drain region of the MOS transistor, through a contact hole (not shown) formed in the interlayer insulating film 3. That is, the interlayer insulating film 3 is used for the purpose of insulating and separating the semiconductor element and the wiring 4.

An interlayer insulating film 5 is formed on the first layer wiring 4.
A second layer wiring 10 extends between the two layers. Wiring 1
0 is selective CVD in the connection hole 6 formed in the interlayer insulating film 5.
It is electrically connected to the wiring 4 through a high melting point metal material 7 that is selectively embedded using a (vapor phase chemical growth) method. Although not shown, the wiring 10 is electrically connected to an external terminal (bonding pad) formed in the same manufacturing process as the wiring 10.

The wiring 10 and external terminals are covered with a final protective film 1.
Covered by 1. A bonding opening (not shown) is formed in a region of this final protective film 11 where an external terminal is arranged.

Next, a method for manufacturing the semiconductor integrated circuit device will be briefly explained using FIGS. 2 to 6 (cross-sectional views of main parts shown for each manufacturing process).

First, a p-type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, after forming a well region (not shown) in the active region on the main surface of the p-type semiconductor substrate 1, a well region (not shown) is formed on the main surface of the p-type semiconductor substrate 1 by a well-known selective oxidation method. A field insulating film 2 is formed in the non-active region.

Next, after semiconductor elements such as MOS transistors and capacitive elements are formed in the active region of the main surface of the p-type semiconductor substrate 1, an interlayer is formed on the entire surface of the substrate including the active region and the inactive region. An insulating film 3 is formed. The interlayer insulating film 3 is formed of, for example, a silicon oxide film deposited by the CVD method.

Next, after forming a photoresist film with a predetermined pattern on the interlayer insulating film 3 by photolithography, this photoresist film is used as an etching mask, and the source of the MOS transistor is formed on the interlayer insulating film 3. A contact hole (not shown) is formed to expose the surfaces of a pair of semiconductor regions, which are a region and a drain region.

Next, after removing the photoresist film, a W film is deposited over the entire surface of the interlayer insulating film 3, including the surface of the semiconductor region, by, for example, sputtering. A part of this W film is electrically connected to the semiconductor region of the MOS transistor through the connection hole.

Next, after forming a photoresist film with a predetermined pattern on the W film, this photoresist film is used as an etching mask, and the W film is patterned by anisotropic etching to remove the remaining The first layer wiring 4 is formed using a W film.

Next, after removing the photoresist film, an interlayer insulating film 5 is formed on the entire surface of the interlayer insulating film 3 including the wiring 4.
form. This interlayer insulating film 5 is formed of a silicon oxide film having a three-layer structure, for example. First, a first layer of silicon oxide film is deposited on the entire surface of the interlayer insulating film 3 including the wiring 4 by plasma CVD. Next, a second layer of silicon oxide film is coated on the entire surface of the first layer of silicon oxide film using the SOG method, and after baking, the entire surface is etched to remove the first layer of silicon oxide film. Alleviate surface level differences. Next, a third silicon oxide film is deposited again on the entire surface of the second silicon oxide film by plasma CVD. As a result, a silicon oxide film having a three-layer structure is formed. Note that the interlayer insulating film 5 may be formed of, for example, a PSG (phosphosilicate glass) film deposited by a CVD method.

Next, a photoresist film having a predetermined pattern is formed on the interlayer insulating film 5. Thereafter, using the photoresist film as an etching mask, as shown in FIG. 2, a connection hole 6 is formed in a part of the wiring 4 under the interlayer insulating film 5, exposing the surface of the wiring 4.

Next, the photoresist film is removed, and N
After pretreatment with F3 plasma, the interlayer insulating film 5
A high melting point metal material 7 is selectively formed in the connection hole 6 of. The high melting point metal material 7 is a W film selectively deposited on the surface of the wiring 4 exposed in the connection hole 6 by a selective CVD method using monosilane (SiH4) and tungsten hexafluoride (WF6) as reaction gases. It is formed. In this manufacturing process,
When the selectivity decreases, as shown in FIG. 3, foreign matter 8 with W as its nucleus is generated (attached) on the interlayer insulating film 5. Incidentally, the high melting point metal material 7 is molybdenum (Mo) or titanium (T).
It may be formed of a metal film such as i).

Next, as shown in FIG. 4, a wiring layer 9 is formed over the entire surface of the interlayer insulating film 5 including the high melting point metal material 7. The wiring layer 9 is formed of an aluminum (Al) film deposited by sputtering, for example. A part of the wiring layer 9 is
It is electrically connected to a high melting point metal material 7 formed in the connection hole 6 of the interlayer insulating film 5 . The foreign matter 8 is in the wiring layer 9
covered with. Note that the wiring layer 9 may be formed of an alloy film such as an Al alloy film or a metal film such as a copper (Cu) film.

Next, after forming a photoresist film in a predetermined pattern on the wiring layer 9, this photoresist film is used as an etching mask to remove the high melting point metal material 7 in the connection hole 6 of the wiring layer 9. The wiring layer 9 is patterned by anisotropic etching except for the connection portion with the wiring layer 9, and as shown in FIG.
0 and also form external terminals (not shown). The wiring 10 passes through the high melting point metal material 7 to the first layer wiring 4.
and is also electrically connected to an external terminal. In other words, the wiring 10 covers the surface of the high melting point metal material 7. In this manufacturing process, the foreign matter 8 that was attached when the high melting point material 7 was formed in the area where the wiring layer 9 on the interlayer insulating film 5 was removed by patterning is exposed between the wirings 10.

Next, foreign matter 8 adhering between the wirings 10 on the interlayer insulating film 5 is removed using hydrogen peroxide (H2O2) as shown in FIG. Hydrogen peroxide solution is W,
High melting point metals such as Mo and Ti can be selectively etched. In this manufacturing process, the surface of the high melting point metal material 7 is
0, the high melting point metal material 7 is not etched. Note that the foreign matter 8 attached below the wiring 10 remains as it is.

Next, a final protective film 11 of a PSG film deposited by sputtering, for example, is formed on the entire surface of the wiring 10 and the interlayer insulating film 5. Thereafter, bonding openings are formed in the regions of the final protective film 11 where external terminals are to be arranged, and as shown in FIG. 1, a semiconductor integrated circuit device with a two-wire structure is almost completed.

In this way, the first layer wiring (lower layer wiring)
A selective CV is formed in the connection hole 6 formed in the interlayer insulating film 5 on the
A high melting point metal material 7 is selectively embedded using method D, and a second layer wiring (upper layer wiring) 10 formed on the interlayer insulating film 5 is electrically connected to the wiring 4 through the high melting point metal material 7. In the method for manufacturing a semiconductor integrated circuit device to be connected, the wiring 4
a step of forming an interlayer insulating film 5 thereon; and a step of forming an interlayer insulating film 5 thereon;
A step of forming a connection hole 6 in which the surface of the wiring 4 is exposed on a part of the wiring 4 in the lower layer, and selectively using a high melting point metal material on the wiring 4 exposed from inside the connection hole 6 using a selective CVD method. 7, forming a wiring layer 9 on the interlayer insulating film 5, and connecting a part of this wiring layer 9 to the high melting point material 7 formed in the connection hole 6; Connection hole 6 in layer 9
This wiring layer 9 except for the connection part with the high melting point metal material 7 inside
selectively patterning using anisotropic etching to form wiring 10 using the remaining wiring layer 9; and a step of selectively removing foreign matter 8 that is attached when the high melting point metal material 7 is selectively formed by the selective CVD method. The high melting point metal material 7 is made of W, Mo, or Ti. The step of removing the foreign matter 8 is performed by etching using hydrogen peroxide. As a result, the foreign matter 8 generated when the high melting point metal material 7 is formed on the interlayer insulating film 5 other than the wiring 10 by the selective CVD method can be removed in a single removal step after the wiring 10 is formed. , the number of steps in the manufacturing process of a semiconductor integrated circuit device can be reduced, and the high melting point metal material 7 is embedded in the connection hole 6, the surface of the high melting point metal material 7 is covered with the wiring 10, and then it is attached on the interlayer insulating film. Since we selectively removed the foreign matter 8,
The wiring 10 serves as a mask when removing the foreign matter 8, and damage to the surface of the high melting point metal material 7 can be eliminated.

Furthermore, since the foreign matter 8 between the wirings 10 on the interlayer insulating film 5 can be removed, short circuits between the wirings 10 due to the foreign matter 8 can be prevented.

As described above, the invention made by the present inventor is as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, it goes without saying that the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the gist thereof.

For example, the present invention can be applied to a semiconductor integrated circuit device having a three-layer wiring structure or more.

The present invention also provides a method for selectively embedding a high-melting point metal material into a contact hole formed in an interlayer insulating film on a semiconductor region constituting a semiconductor element, and forming wirings formed on the interlayer insulating film. can be applied to a semiconductor integrated circuit device that is electrically connected to the semiconductor region through the high melting point metal material.

[0042]

Effects of the Invention A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

[0043] The number of steps in the manufacturing process of a semiconductor integrated circuit device can be reduced, and short circuits between wirings can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of main parts showing a schematic configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a main part showing each manufacturing process of the method for manufacturing the semiconductor integrated circuit device.

FIG. 3 is a cross-sectional view of a main part showing each manufacturing process of the method for manufacturing the semiconductor integrated circuit device.

FIG. 4 is a cross-sectional view of a main part showing each manufacturing process of the method for manufacturing the semiconductor integrated circuit device.

FIG. 5 is a cross-sectional view of a main part showing each manufacturing process of the method for manufacturing the semiconductor integrated circuit device.

FIG. 6 is a cross-sectional view of a main part showing each manufacturing process of the method for manufacturing the semiconductor integrated circuit device.

[Explanation of symbols]

1 p-type semiconductor substrate 3 Interlayer insulation film 4 First layer wiring 5 Interlayer insulation film 6 Connection hole 7 High melting point metal material 8 Foreign matter 10 Second layer wiring 11 Final protective film

Claims (3)

[Claims] 1. A high melting point metal material is selectively buried in a contact hole formed in an interlayer insulating film on a lower layer wiring by a vapor phase chemical growth method, and the upper layer wiring formed on the interlayer insulating film is In a method of manufacturing a semiconductor integrated circuit device in which a semiconductor integrated circuit device is electrically connected to the lower wiring through a melting point metal material, the step of forming an interlayer insulating film on the lower wiring; A step of forming a connection hole through which the surface of the wiring is exposed, a step of selectively forming a high melting point metal material on the lower layer wiring exposed from inside the connection hole by a vapor phase chemical growth method, and a step of forming a high melting point metal material on the interlayer insulating film. Excluding the step of forming a wiring layer and connecting a part of this wiring layer to the high melting point metal material formed in the connection hole, and the connecting part of the wiring layer to the high melting point metal material in the connection hole, This wiring layer is selectively patterned using anisotropic etching, and the remaining wiring layer is used to form an upper layer wiring. A method for manufacturing a semiconductor integrated circuit device, comprising the step of selectively removing foreign matter that adheres when the high melting point metal material is selectively formed by the vapor phase chemical growth method. 2. The high melting point metal material is W, Mo or T.
2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed of any one of i. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step of removing the foreign matter is performed by etching using a hydrogen peroxide solution.